From nobody Thu Nov 28 11:30:01 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 19A6D1C8FB2; Tue, 1 Oct 2024 14:39:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727793568; cv=none; b=aTbPyQV3NvqoPkAxc3JCuWyLj/dh2ZpL8L3VugMP3px2XxDeTJPuq5bN3IS/3O+GYyPXYXJs9IWty79eveFsyL3VDkMI9Yvj1b19MK+WKExehj/ab7Wv8IRTfyFTv2J7AdQi8imsZzxVjZBaP63chZE2h5BM7pDw16AySmRhSvs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727793568; c=relaxed/simple; bh=j7cEcKzext16oP7OAxC9breMWXfoaROVojla+gdYgKc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JBKUuCgN8KOWUsgDDg1e7C2dGV+nBpIP3N7ylmmNe0aKUXf6VMQ2Tooef/nyGs5gfZTHcaJAVin8EUuvUIIsTgcWMdbbr1IDZAFmzS/Gz3q9kt6MsxmxgWluIaVdgd/OFzgNKMevDn96TiqL+JSXTpPQWcfRFCEYHlZ4645d3Ek= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Rns/Cat+; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Rns/Cat+" Received: by smtp.kernel.org (Postfix) with ESMTPS id D5BACC4CEC7; Tue, 1 Oct 2024 14:39:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1727793567; bh=j7cEcKzext16oP7OAxC9breMWXfoaROVojla+gdYgKc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Rns/Cat+AEOQeI7jP+6zWAml/O1enmAsX7qaQrxXji7zas0R8q7Hhrs/pGvR7v1yf uApP6dMeVZcOgDWUazNZCKswuk6WpEiKN5CPHUrOpQg0nbGoO0LJg+68vSKg0/cPjT dwYA6oB8d0OJ4nhdXmFRFAHCeA74tpIdNQMj3Ku4saVSj1kcAPLS8uKAjKo4BBex2J F+fca2XkzWmz+WlLh6mnPTXuWMWdUFS5xdcLLPdYXikXRQYAaw5qV91Y8h2kzyd2oc Qmapj1u/oqhPPAIRuszs98lKW4dceyLiJ83TqFzMkSUkub97bhRGZko9kUbf3SNJ6X DBji+piSiWtBA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C453ACEACD0; Tue, 1 Oct 2024 14:39:27 +0000 (UTC) From: =?utf-8?q?Duje_Mihanovi=C4=87_via_B4_Relay?= Date: Tue, 01 Oct 2024 16:37:31 +0200 Subject: [PATCH v13 01/12] clk: mmp: Switch to use struct u32_fract instead of custom one Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241001-pxa1908-lkml-v13-1-6b9a7f64f9ae@skole.hr> References: <20241001-pxa1908-lkml-v13-0-6b9a7f64f9ae@skole.hr> In-Reply-To: <20241001-pxa1908-lkml-v13-0-6b9a7f64f9ae@skole.hr> To: Michael Turquette , Stephen Boyd , Linus Walleij , Rob Herring , Conor Dooley , Tony Lindgren , Haojian Zhuang , =?utf-8?q?Duje_Mihanovi=C4=87?= , Lubomir Rintel , Catalin Marinas , Will Deacon , Rob Herring , Krzysztof Kozlowski Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Karel Balej , David Wronek , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andy Shevchenko X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=10838; i=duje.mihanovic@skole.hr; s=20240706; h=from:subject:message-id; bh=aUPxtF04qTKpLPEJgHiKaCixpSaCfAFycFxZA5nFzBw=; b=owGbwMvMwCW21nBykGv/WmbG02pJDGl/OCeV5Ly+/fDZncaCu7/kA27Zek551tboHX3A7cR7a TGugoqOjlIWBjEuBlkxRZbc/47XeD+LbN2evcwAZg4rE8gQBi5OAZiIpxojw1k+gV9P2VYlme4/ bHAi8/u7J+vVZttZxgkd/MMj5jDd9SbDP8PIyK9/tnHt0rt3u61jjt+yn1v/zk/XOCznmbVOfZV zFhMA X-Developer-Key: i=duje.mihanovic@skole.hr; a=openpgp; fpr=6DFF41D60DF314B5B76BA630AD319352458FAD03 X-Endpoint-Received: by B4 Relay for duje.mihanovic@skole.hr/20240706 with auth_id=191 X-Original-From: =?utf-8?q?Duje_Mihanovi=C4=87?= Reply-To: duje.mihanovic@skole.hr From: Andy Shevchenko The struct mmp_clk_factor_tbl repeats the generic struct u32_fract. Kill the custom one and use the generic one instead. Signed-off-by: Andy Shevchenko Tested-by: Duje Mihanovi=C4=87 Reviewed-by: Linus Walleij Reviewed-by: Stephen Boyd Signed-off-by: Duje Mihanovi=C4=87 --- drivers/clk/mmp/clk-frac.c | 57 ++++++++++++++++++++----------------= ---- drivers/clk/mmp/clk-of-mmp2.c | 26 +++++++++--------- drivers/clk/mmp/clk-of-pxa168.c | 4 +-- drivers/clk/mmp/clk-of-pxa1928.c | 6 ++--- drivers/clk/mmp/clk-of-pxa910.c | 4 +-- drivers/clk/mmp/clk.h | 10 +++---- 6 files changed, 51 insertions(+), 56 deletions(-) diff --git a/drivers/clk/mmp/clk-frac.c b/drivers/clk/mmp/clk-frac.c index 1b90867b60c4b5b2582cc92b0050221330a3c003..6556f6ada2e830178b9525462f6= 84bad683db454 100644 --- a/drivers/clk/mmp/clk-frac.c +++ b/drivers/clk/mmp/clk-frac.c @@ -26,14 +26,15 @@ static long clk_factor_round_rate(struct clk_hw *hw, un= signed long drate, { struct mmp_clk_factor *factor =3D to_clk_factor(hw); u64 rate =3D 0, prev_rate; + struct u32_fract *d; int i; =20 for (i =3D 0; i < factor->ftbl_cnt; i++) { - prev_rate =3D rate; - rate =3D *prate; - rate *=3D factor->ftbl[i].den; - do_div(rate, factor->ftbl[i].num * factor->masks->factor); + d =3D &factor->ftbl[i]; =20 + prev_rate =3D rate; + rate =3D (u64)(*prate) * d->denominator; + do_div(rate, d->numerator * factor->masks->factor); if (rate > drate) break; } @@ -52,23 +53,22 @@ static unsigned long clk_factor_recalc_rate(struct clk_= hw *hw, { struct mmp_clk_factor *factor =3D to_clk_factor(hw); struct mmp_clk_factor_masks *masks =3D factor->masks; - unsigned int val, num, den; + struct u32_fract d; + unsigned int val; u64 rate; =20 val =3D readl_relaxed(factor->base); =20 /* calculate numerator */ - num =3D (val >> masks->num_shift) & masks->num_mask; + d.numerator =3D (val >> masks->num_shift) & masks->num_mask; =20 /* calculate denominator */ - den =3D (val >> masks->den_shift) & masks->den_mask; - - if (!den) + d.denominator =3D (val >> masks->den_shift) & masks->den_mask; + if (!d.denominator) return 0; =20 - rate =3D parent_rate; - rate *=3D den; - do_div(rate, num * factor->masks->factor); + rate =3D (u64)parent_rate * d.denominator; + do_div(rate, d.numerator * factor->masks->factor); =20 return rate; } @@ -82,18 +82,18 @@ static int clk_factor_set_rate(struct clk_hw *hw, unsig= ned long drate, int i; unsigned long val; unsigned long flags =3D 0; + struct u32_fract *d; u64 rate =3D 0; =20 for (i =3D 0; i < factor->ftbl_cnt; i++) { - rate =3D prate; - rate *=3D factor->ftbl[i].den; - do_div(rate, factor->ftbl[i].num * factor->masks->factor); + d =3D &factor->ftbl[i]; =20 + rate =3D (u64)prate * d->denominator; + do_div(rate, d->numerator * factor->masks->factor); if (rate > drate) break; } - if (i > 0) - i--; + d =3D i ? &factor->ftbl[i - 1] : &factor->ftbl[0]; =20 if (factor->lock) spin_lock_irqsave(factor->lock, flags); @@ -101,10 +101,10 @@ static int clk_factor_set_rate(struct clk_hw *hw, uns= igned long drate, val =3D readl_relaxed(factor->base); =20 val &=3D ~(masks->num_mask << masks->num_shift); - val |=3D (factor->ftbl[i].num & masks->num_mask) << masks->num_shift; + val |=3D (d->numerator & masks->num_mask) << masks->num_shift; =20 val &=3D ~(masks->den_mask << masks->den_shift); - val |=3D (factor->ftbl[i].den & masks->den_mask) << masks->den_shift; + val |=3D (d->denominator & masks->den_mask) << masks->den_shift; =20 writel_relaxed(val, factor->base); =20 @@ -118,7 +118,8 @@ static int clk_factor_init(struct clk_hw *hw) { struct mmp_clk_factor *factor =3D to_clk_factor(hw); struct mmp_clk_factor_masks *masks =3D factor->masks; - u32 val, num, den; + struct u32_fract d; + u32 val; int i; unsigned long flags =3D 0; =20 @@ -128,23 +129,22 @@ static int clk_factor_init(struct clk_hw *hw) val =3D readl(factor->base); =20 /* calculate numerator */ - num =3D (val >> masks->num_shift) & masks->num_mask; + d.numerator =3D (val >> masks->num_shift) & masks->num_mask; =20 /* calculate denominator */ - den =3D (val >> masks->den_shift) & masks->den_mask; + d.denominator =3D (val >> masks->den_shift) & masks->den_mask; =20 for (i =3D 0; i < factor->ftbl_cnt; i++) - if (den =3D=3D factor->ftbl[i].den && num =3D=3D factor->ftbl[i].num) + if (d.denominator =3D=3D factor->ftbl[i].denominator && + d.numerator =3D=3D factor->ftbl[i].numerator) break; =20 if (i >=3D factor->ftbl_cnt) { val &=3D ~(masks->num_mask << masks->num_shift); - val |=3D (factor->ftbl[0].num & masks->num_mask) << - masks->num_shift; + val |=3D (factor->ftbl[0].numerator & masks->num_mask) << masks->num_shi= ft; =20 val &=3D ~(masks->den_mask << masks->den_shift); - val |=3D (factor->ftbl[0].den & masks->den_mask) << - masks->den_shift; + val |=3D (factor->ftbl[0].denominator & masks->den_mask) << masks->den_s= hift; } =20 if (!(val & masks->enable_mask) || i >=3D factor->ftbl_cnt) { @@ -168,8 +168,7 @@ static const struct clk_ops clk_factor_ops =3D { struct clk *mmp_clk_register_factor(const char *name, const char *parent_n= ame, unsigned long flags, void __iomem *base, struct mmp_clk_factor_masks *masks, - struct mmp_clk_factor_tbl *ftbl, - unsigned int ftbl_cnt, spinlock_t *lock) + struct u32_fract *ftbl, unsigned int ftbl_cnt, spinlock_t *lock) { struct mmp_clk_factor *factor; struct clk_init_data init; diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c index eaad36ee323d14ff3d0f61c917d57d1501359db1..a4f15cee630ee65bcedba3975cf= 337ff765d3b2d 100644 --- a/drivers/clk/mmp/clk-of-mmp2.c +++ b/drivers/clk/mmp/clk-of-mmp2.c @@ -143,9 +143,9 @@ static struct mmp_clk_factor_masks uart_factor_masks = =3D { .den_shift =3D 0, }; =20 -static struct mmp_clk_factor_tbl uart_factor_tbl[] =3D { - {.num =3D 8125, .den =3D 1536}, /*14.745MHZ */ - {.num =3D 3521, .den =3D 689}, /*19.23MHZ */ +static struct u32_fract uart_factor_tbl[] =3D { + { .numerator =3D 8125, .denominator =3D 1536 }, /* 14.745MHZ */ + { .numerator =3D 3521, .denominator =3D 689 }, /* 19.23MHZ */ }; =20 static struct mmp_clk_factor_masks i2s_factor_masks =3D { @@ -157,16 +157,16 @@ static struct mmp_clk_factor_masks i2s_factor_masks = =3D { .enable_mask =3D 0xd0000000, }; =20 -static struct mmp_clk_factor_tbl i2s_factor_tbl[] =3D { - {.num =3D 24868, .den =3D 511}, /* 2.0480 MHz */ - {.num =3D 28003, .den =3D 793}, /* 2.8224 MHz */ - {.num =3D 24941, .den =3D 1025}, /* 4.0960 MHz */ - {.num =3D 28003, .den =3D 1586}, /* 5.6448 MHz */ - {.num =3D 31158, .den =3D 2561}, /* 8.1920 MHz */ - {.num =3D 16288, .den =3D 1845}, /* 11.2896 MHz */ - {.num =3D 20772, .den =3D 2561}, /* 12.2880 MHz */ - {.num =3D 8144, .den =3D 1845}, /* 22.5792 MHz */ - {.num =3D 10386, .den =3D 2561}, /* 24.5760 MHz */ +static struct u32_fract i2s_factor_tbl[] =3D { + { .numerator =3D 24868, .denominator =3D 511 }, /* 2.0480 MHz */ + { .numerator =3D 28003, .denominator =3D 793 }, /* 2.8224 MHz */ + { .numerator =3D 24941, .denominator =3D 1025 }, /* 4.0960 MHz */ + { .numerator =3D 28003, .denominator =3D 1586 }, /* 5.6448 MHz */ + { .numerator =3D 31158, .denominator =3D 2561 }, /* 8.1920 MHz */ + { .numerator =3D 16288, .denominator =3D 1845 }, /* 11.2896 MHz */ + { .numerator =3D 20772, .denominator =3D 2561 }, /* 12.2880 MHz */ + { .numerator =3D 8144, .denominator =3D 1845 }, /* 22.5792 MHz */ + { .numerator =3D 10386, .denominator =3D 2561 }, /* 24.5760 MHz */ }; =20 static DEFINE_SPINLOCK(acgr_lock); diff --git a/drivers/clk/mmp/clk-of-pxa168.c b/drivers/clk/mmp/clk-of-pxa16= 8.c index c5a7ba1deaa3a1d42cd85cf462b7eed79c5d9ba1..5f250427e60d25b24208d02322a= 441d86faf346b 100644 --- a/drivers/clk/mmp/clk-of-pxa168.c +++ b/drivers/clk/mmp/clk-of-pxa168.c @@ -106,8 +106,8 @@ static struct mmp_clk_factor_masks uart_factor_masks = =3D { .den_shift =3D 0, }; =20 -static struct mmp_clk_factor_tbl uart_factor_tbl[] =3D { - {.num =3D 8125, .den =3D 1536}, /*14.745MHZ */ +static struct u32_fract uart_factor_tbl[] =3D { + { .numerator =3D 8125, .denominator =3D 1536 }, /* 14.745MHZ */ }; =20 static void pxa168_pll_init(struct pxa168_clk_unit *pxa_unit) diff --git a/drivers/clk/mmp/clk-of-pxa1928.c b/drivers/clk/mmp/clk-of-pxa1= 928.c index 9def4b5f10e910b18065647dcde2a44c43b8185d..ebb6e278eda33c551abce893051= bf52e97f898c4 100644 --- a/drivers/clk/mmp/clk-of-pxa1928.c +++ b/drivers/clk/mmp/clk-of-pxa1928.c @@ -61,9 +61,9 @@ static struct mmp_clk_factor_masks uart_factor_masks =3D { .den_shift =3D 0, }; =20 -static struct mmp_clk_factor_tbl uart_factor_tbl[] =3D { - {.num =3D 832, .den =3D 234}, /*58.5MHZ */ - {.num =3D 1, .den =3D 1}, /*26MHZ */ +static struct u32_fract uart_factor_tbl[] =3D { + { .numerator =3D 832, .denominator =3D 234 }, /* 58.5MHZ */ + { .numerator =3D 1, .denominator =3D 1 }, /* 26MHZ */ }; =20 static void pxa1928_pll_init(struct pxa1928_clk_unit *pxa_unit) diff --git a/drivers/clk/mmp/clk-of-pxa910.c b/drivers/clk/mmp/clk-of-pxa91= 0.c index 7a38c424782e619347c44b75edb1938cb7a27dc9..fe65e7bdb411fe9be93e8dd5d57= 1e1c62b12909f 100644 --- a/drivers/clk/mmp/clk-of-pxa910.c +++ b/drivers/clk/mmp/clk-of-pxa910.c @@ -86,8 +86,8 @@ static struct mmp_clk_factor_masks uart_factor_masks =3D { .den_shift =3D 0, }; =20 -static struct mmp_clk_factor_tbl uart_factor_tbl[] =3D { - {.num =3D 8125, .den =3D 1536}, /*14.745MHZ */ +static struct u32_fract uart_factor_tbl[] =3D { + { .numerator =3D 8125, .denominator =3D 1536 }, /* 14.745MHZ */ }; =20 static void pxa910_pll_init(struct pxa910_clk_unit *pxa_unit) diff --git a/drivers/clk/mmp/clk.h b/drivers/clk/mmp/clk.h index 55ac053797819e791d62e5f950779c56a957c994..c83cec169ddc5e3fcd0561cf857= f248178c25b68 100644 --- a/drivers/clk/mmp/clk.h +++ b/drivers/clk/mmp/clk.h @@ -3,6 +3,7 @@ #define __MACH_MMP_CLK_H =20 #include +#include #include #include =20 @@ -20,16 +21,11 @@ struct mmp_clk_factor_masks { unsigned int enable_mask; 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a=openpgp; fpr=6DFF41D60DF314B5B76BA630AD319352458FAD03 X-Endpoint-Received: by B4 Relay for duje.mihanovic@skole.hr/20240706 with auth_id=191 X-Original-From: =?utf-8?q?Duje_Mihanovi=C4=87?= Reply-To: duje.mihanovic@skole.hr From: Duje Mihanovi=C4=87 Add the "marvell,pxa1908-padconf" compatible to allow migrating to a separate pinctrl driver later. Reviewed-by: Rob Herring Acked-by: Linus Walleij Signed-off-by: Duje Mihanovi=C4=87 --- Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml = b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml index e02595316c9f4939ca5a7c61115f23ca4dc5e1b8..f83dbf32ad1838f25429e22bae1= 4f6c74cb38d96 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml @@ -33,6 +33,10 @@ properties: - ti,omap5-padconf - ti,j7200-padconf - const: pinctrl-single + - items: + - enum: + - marvell,pxa1908-padconf + - const: pinconf-single =20 reg: maxItems: 1 --=20 2.46.2 From nobody Thu Nov 28 11:30:01 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5020C1C8FCE; Tue, 1 Oct 2024 14:39:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727793568; cv=none; b=k38VCG0ZL5VFroqlTxb4ENn1eivryUzb/S3SubIARMOlvwX1yUVtX6/0mv/RFzWSGJmDRyiuPaHzM5267B2WiIuE7bLvr0SM/6VgNqdbhuyDOYbEi7ryViJVqdBFLbzGM3xJZNpDlq7sQNLFdSsXtSFc6FS5qGQY+1hDxGqrGeE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727793568; c=relaxed/simple; bh=waEIGljs+kpXr7H6X7w1X9tSVRKCK5G7Rv5oX7oaIWQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rwEHj8DP5BTI/lV39/e7O9xBjGYw5IdWOjTJIQ03jutfegfUa87J7QSB1618rEuqW+Kcjm4NRO4Y8t9PIOyxyFvQMrtgxlqRetFqPaYgPjYL1/2WzQMHJhrcLIPdkek++o2dk5s4Bo2hwxx1dist6q8rQVdVdJPomCQqFkWAxnI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dkCPnvWN; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dkCPnvWN" Received: by smtp.kernel.org (Postfix) with ESMTPS id 24441C4CED9; Tue, 1 Oct 2024 14:39:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1727793568; bh=waEIGljs+kpXr7H6X7w1X9tSVRKCK5G7Rv5oX7oaIWQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=dkCPnvWNITR+Zlj+Dy0CKUybafYTdDm8UuFP3UHIrgCR+m8bpt4qvLV11UPabxOXN hm29TnWSE+gEQm9wE7MLevH0WNfsgzO5n5HEF6e8ZfwbMx+cA9p95JmtyOP1pjZKZT 9o9SKAGsJ8D2siae06PLPqXAL320OF5BE+z5Hq7/fzstFOF9v751pP94Yv2F2y2/dU gxmpTRZQn0Sod0d6inhTYfnvxz6uSvVovbvj6FeaV7HE+8k0rJwpKEGDtTn6N+L1yS zRu5E7yyO2mTBPHUSgV4WbMetys6UqbYrM2BZD2ZQDjEplGNiyUHGUdtUCz1QRn8rB 6Z4Hzl1J2pn4w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 180F5CEACD2; Tue, 1 Oct 2024 14:39:28 +0000 (UTC) From: =?utf-8?q?Duje_Mihanovi=C4=87_via_B4_Relay?= Date: Tue, 01 Oct 2024 16:37:33 +0200 Subject: [PATCH v13 03/12] pinctrl: single: add marvell,pxa1908-padconf compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241001-pxa1908-lkml-v13-3-6b9a7f64f9ae@skole.hr> References: <20241001-pxa1908-lkml-v13-0-6b9a7f64f9ae@skole.hr> In-Reply-To: <20241001-pxa1908-lkml-v13-0-6b9a7f64f9ae@skole.hr> To: Michael Turquette , Stephen Boyd , Linus Walleij , Rob Herring , Conor Dooley , Tony Lindgren , Haojian Zhuang , =?utf-8?q?Duje_Mihanovi=C4=87?= , Lubomir Rintel , Catalin Marinas , Will Deacon , Rob Herring , Krzysztof Kozlowski Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Karel Balej , David Wronek , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=994; i=duje.mihanovic@skole.hr; s=20240706; h=from:subject:message-id; bh=wmllmkXuy52PZE0mmFVA4U83iFJjDnJw2/MynI3ODOQ=; b=owGbwMvMwCW21nBykGv/WmbG02pJDGl/OCfdMvizNOeYzcdZO07nZccd2P37ePn5bY/elAY3b PoixDr1f0cpC4MYF4OsmCJL7n/Ha7yfRbZuz15mADOHlQlkCAMXpwBM5GoyI8OC/67Hc+yU+Gb+ mOx1s9bd9oDZZMeyZcFCZ9b3swQZdqgw/C+eMP9D4sFmqYj3HlflK172Heaf8XNZzILY9Yfqw4W 4jNgA X-Developer-Key: i=duje.mihanovic@skole.hr; a=openpgp; fpr=6DFF41D60DF314B5B76BA630AD319352458FAD03 X-Endpoint-Received: by B4 Relay for duje.mihanovic@skole.hr/20240706 with auth_id=191 X-Original-From: =?utf-8?q?Duje_Mihanovi=C4=87?= Reply-To: duje.mihanovic@skole.hr From: Duje Mihanovi=C4=87 Add the "marvell,pxa1908-padconf" compatible to allow migrating to a separate pinctrl driver later. Acked-by: Linus Walleij Signed-off-by: Duje Mihanovi=C4=87 --- drivers/pinctrl/pinctrl-single.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-sin= gle.c index 2ec599e383e4b2d463725b8baf4bb8bbcdc4c9f1..09fe7e6233f00d83de385c3a0f4= 49bc4a709681f 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -1966,6 +1966,7 @@ static const struct pcs_soc_data pinconf_single =3D { }; =20 static const struct of_device_id pcs_of_match[] =3D { + { .compatible =3D "marvell,pxa1908-padconf", .data =3D &pinconf_single }, { .compatible =3D "ti,am437-padconf", .data =3D &pinctrl_single_am437x }, { .compatible =3D "ti,am654-padconf", .data =3D &pinctrl_single_am654 }, { .compatible =3D "ti,dra7-padconf", .data =3D &pinctrl_single_dra7 }, --=20 2.46.2 From nobody Thu Nov 28 11:30:01 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 735C81C8FDC; Tue, 1 Oct 2024 14:39:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727793568; cv=none; b=kMhx2GcxG/evcNMWv0pF+81vAS6yiyV/z2hpRqaY0fcvqxnTD6yQ2A0z8c1VdhJ3qTHEvfiQK9JMTSqW4TASGFVRiC0AjA0evXSoKQNMqrxiIZ/yiAlohGWHY4Val0bv3L5F6+g+u7B14bhiQHNn1/6/bp40gz/xBGdXSvk3TRk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727793568; c=relaxed/simple; bh=xRKZsSbMkPuauoeApBaSWMeBF9J6EJER1zS21DadUP4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PoLE0fgD5EMgKkFrE15C9YM3A2bTcjTi3yQ7QQYXeKNdctoxuewxlpq7zptmiwqHE80lWrRqmPlATDkcOVVPLKQovzxvQ+JhEiUOJmi2hQzoSAoflcmQJU7Xl8hL4g3lKd41rSThq/wHLDZtshIxZU5NfzjslDM8e+Rj+BakQ6o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RJ72vvmI; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RJ72vvmI" Received: by smtp.kernel.org (Postfix) with ESMTPS id 3490AC4CEDF; Tue, 1 Oct 2024 14:39:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1727793568; bh=xRKZsSbMkPuauoeApBaSWMeBF9J6EJER1zS21DadUP4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=RJ72vvmICkgm/iCJqcz4yJZe1xvk9zmDXSsqc2GvvZxlYceAZnP1xSbl+6QYlMJ30 iSpFcs8+bjT1rEYVtGOEVS1eMNXU3U7XoOOmm8xDS4ZQMzFJ5qYnyWYHXyu/AvOrE0 ATZoGKES/5lubBobdgsIL8qrV412HQxw+tPO/mzPwuby3ir9SmkFznNnPAXW+4vnV4 /uRdVBVPC+1KgDXMdsqd7jquy8ttBu6lTEcK8z8mOvV4bXotHG4hivocwssPQUIuKw WGiAmGpOvJy7nOL6XOkcOsLY4E2efD/b/sfdkyq1VnE308j/DnBXR8gv7xhPDu3R2L 8GJUQwthdO4Ow== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AF26CEACCE; Tue, 1 Oct 2024 14:39:28 +0000 (UTC) From: =?utf-8?q?Duje_Mihanovi=C4=87_via_B4_Relay?= Date: Tue, 01 Oct 2024 16:37:34 +0200 Subject: [PATCH v13 04/12] dt-bindings: clock: Add Marvell PXA1908 clock bindings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241001-pxa1908-lkml-v13-4-6b9a7f64f9ae@skole.hr> References: <20241001-pxa1908-lkml-v13-0-6b9a7f64f9ae@skole.hr> In-Reply-To: <20241001-pxa1908-lkml-v13-0-6b9a7f64f9ae@skole.hr> To: Michael Turquette , Stephen Boyd , Linus Walleij , Rob Herring , Conor Dooley , Tony Lindgren , Haojian Zhuang , =?utf-8?q?Duje_Mihanovi=C4=87?= , Lubomir Rintel , Catalin Marinas , Will Deacon , Rob Herring , Krzysztof Kozlowski Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Karel Balej , David Wronek , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Conor Dooley X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5085; i=duje.mihanovic@skole.hr; s=20240706; h=from:subject:message-id; bh=+wiZmG7RML75ebWcpNqefQgETbMc7ztfxKlJgaoEc7E=; b=owGbwMvMwCW21nBykGv/WmbG02pJDGl/OCdt89Jg7gy0TfeRuyUQ9U7Tt9GJ/VWT1KSy8/Etl j43lRo6SlkYxLgYZMUUWXL/O17j/SyydXv2MgOYOaxMIEMYuDgFYCLXdjMyHLlSfXJ2eEh6ZIRm 1OPC8Lei825ydTCkPz/9oJQlt2qZBCPD5BUTa19WmnjxnW5IWfNvTvdKY9acS3qTtVu268yJ2P6 PFwA= X-Developer-Key: i=duje.mihanovic@skole.hr; a=openpgp; fpr=6DFF41D60DF314B5B76BA630AD319352458FAD03 X-Endpoint-Received: by B4 Relay for duje.mihanovic@skole.hr/20240706 with auth_id=191 X-Original-From: =?utf-8?q?Duje_Mihanovi=C4=87?= Reply-To: duje.mihanovic@skole.hr From: Duje Mihanovi=C4=87 Add dt bindings and documentation for the Marvell PXA1908 clock controller. Reviewed-by: Conor Dooley Reviewed-by: Stephen Boyd Signed-off-by: Duje Mihanovi=C4=87 --- .../devicetree/bindings/clock/marvell,pxa1908.yaml | 48 ++++++++++++ include/dt-bindings/clock/marvell,pxa1908.h | 88 ++++++++++++++++++= ++++ 2 files changed, 136 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml b= /Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml new file mode 100644 index 0000000000000000000000000000000000000000..4e78933232b6b925811425f853b= edf6e9f01a27d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/marvell,pxa1908.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell PXA1908 Clock Controllers + +maintainers: + - Duje Mihanovi=C4=87 + +description: | + The PXA1908 clock subsystem generates and supplies clock to various + controllers within the PXA1908 SoC. The PXA1908 contains numerous clock + controller blocks, with the ones currently supported being APBC, APBCP, = MPMU + and APMU roughly corresponding to internal buses. + + All these clock identifiers could be found in . + +properties: + compatible: + enum: + - marvell,pxa1908-apbc + - marvell,pxa1908-apbcp + - marvell,pxa1908-mpmu + - marvell,pxa1908-apmu + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + # APMU block: + - | + clock-controller@d4282800 { + compatible =3D "marvell,pxa1908-apmu"; + reg =3D <0xd4282800 0x400>; + #clock-cells =3D <1>; + }; diff --git a/include/dt-bindings/clock/marvell,pxa1908.h b/include/dt-bindi= ngs/clock/marvell,pxa1908.h new file mode 100644 index 0000000000000000000000000000000000000000..fb15b0d0cd4c1cd5760a78ea16a= 1980cd305ea21 --- /dev/null +++ b/include/dt-bindings/clock/marvell,pxa1908.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +#ifndef __DTS_MARVELL_PXA1908_CLOCK_H +#define __DTS_MARVELL_PXA1908_CLOCK_H + +/* plls */ +#define PXA1908_CLK_CLK32 1 +#define PXA1908_CLK_VCTCXO 2 +#define PXA1908_CLK_PLL1_624 3 +#define PXA1908_CLK_PLL1_416 4 +#define PXA1908_CLK_PLL1_499 5 +#define PXA1908_CLK_PLL1_832 6 +#define PXA1908_CLK_PLL1_1248 7 +#define PXA1908_CLK_PLL1_D2 8 +#define PXA1908_CLK_PLL1_D4 9 +#define PXA1908_CLK_PLL1_D8 10 +#define PXA1908_CLK_PLL1_D16 11 +#define PXA1908_CLK_PLL1_D6 12 +#define PXA1908_CLK_PLL1_D12 13 +#define PXA1908_CLK_PLL1_D24 14 +#define PXA1908_CLK_PLL1_D48 15 +#define PXA1908_CLK_PLL1_D96 16 +#define PXA1908_CLK_PLL1_D13 17 +#define PXA1908_CLK_PLL1_32 18 +#define PXA1908_CLK_PLL1_208 19 +#define PXA1908_CLK_PLL1_117 20 +#define PXA1908_CLK_PLL1_416_GATE 21 +#define PXA1908_CLK_PLL1_624_GATE 22 +#define PXA1908_CLK_PLL1_832_GATE 23 +#define PXA1908_CLK_PLL1_1248_GATE 24 +#define PXA1908_CLK_PLL1_D2_GATE 25 +#define PXA1908_CLK_PLL1_499_EN 26 +#define PXA1908_CLK_PLL2VCO 27 +#define PXA1908_CLK_PLL2 28 +#define PXA1908_CLK_PLL2P 29 +#define PXA1908_CLK_PLL2VCODIV3 30 +#define PXA1908_CLK_PLL3VCO 31 +#define PXA1908_CLK_PLL3 32 +#define PXA1908_CLK_PLL3P 33 +#define PXA1908_CLK_PLL3VCODIV3 34 +#define PXA1908_CLK_PLL4VCO 35 +#define PXA1908_CLK_PLL4 36 +#define PXA1908_CLK_PLL4P 37 +#define PXA1908_CLK_PLL4VCODIV3 38 + +/* apb (apbc) peripherals */ +#define PXA1908_CLK_UART0 1 +#define PXA1908_CLK_UART1 2 +#define PXA1908_CLK_GPIO 3 +#define PXA1908_CLK_PWM0 4 +#define PXA1908_CLK_PWM1 5 +#define PXA1908_CLK_PWM2 6 +#define PXA1908_CLK_PWM3 7 +#define PXA1908_CLK_SSP0 8 +#define PXA1908_CLK_SSP1 9 +#define PXA1908_CLK_IPC_RST 10 +#define PXA1908_CLK_RTC 11 +#define PXA1908_CLK_TWSI0 12 +#define PXA1908_CLK_KPC 13 +#define PXA1908_CLK_SWJTAG 14 +#define PXA1908_CLK_SSP2 15 +#define PXA1908_CLK_TWSI1 16 +#define PXA1908_CLK_THERMAL 17 +#define PXA1908_CLK_TWSI3 18 + +/* apb (apbcp) peripherals */ +#define PXA1908_CLK_UART2 1 +#define PXA1908_CLK_TWSI2 2 +#define PXA1908_CLK_AICER 3 + +/* axi (apmu) peripherals */ +#define PXA1908_CLK_CCIC1 1 +#define PXA1908_CLK_ISP 2 +#define PXA1908_CLK_DSI1 3 +#define PXA1908_CLK_DISP1 4 +#define PXA1908_CLK_CCIC0 5 +#define PXA1908_CLK_SDH0 6 +#define PXA1908_CLK_SDH1 7 +#define PXA1908_CLK_USB 8 +#define PXA1908_CLK_NF 9 +#define PXA1908_CLK_CORE_DEBUG 10 +#define PXA1908_CLK_VPU 11 +#define PXA1908_CLK_GC 12 +#define PXA1908_CLK_SDH2 13 +#define PXA1908_CLK_GC2D 14 +#define PXA1908_CLK_TRACE 15 +#define PXA1908_CLK_DVC_DFC_DEBUG 16 + +#endif --=20 2.46.2 From nobody Thu Nov 28 11:30:01 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA7881C9B8F; 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a=openpgp; fpr=6DFF41D60DF314B5B76BA630AD319352458FAD03 X-Endpoint-Received: by B4 Relay for duje.mihanovic@skole.hr/20240706 with auth_id=191 X-Original-From: =?utf-8?q?Duje_Mihanovi=C4=87?= Reply-To: duje.mihanovic@skole.hr From: Duje Mihanovi=C4=87 Add driver for the APBC controller block found on Marvell's PXA1908 SoC. Signed-off-by: Duje Mihanovi=C4=87 --- drivers/clk/mmp/Makefile | 2 +- drivers/clk/mmp/clk-pxa1908-apbc.c | 130 +++++++++++++++++++++++++++++++++= ++++ 2 files changed, 131 insertions(+), 1 deletion(-) diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile index 441bf83080a12b89dd8afca11236ba2a2199795e..685bb80f8ae1f16d967dc4f6f5a= 6ce4e3f52d2bd 100644 --- a/drivers/clk/mmp/Makefile +++ b/drivers/clk/mmp/Makefile @@ -11,4 +11,4 @@ obj-$(CONFIG_MACH_MMP_DT) +=3D clk-of-pxa168.o clk-of-pxa= 910.o obj-$(CONFIG_COMMON_CLK_MMP2) +=3D clk-of-mmp2.o clk-pll.o pwr-island.o obj-$(CONFIG_COMMON_CLK_MMP2_AUDIO) +=3D clk-audio.o =20 -obj-y +=3D clk-of-pxa1928.o +obj-$(CONFIG_ARCH_MMP) +=3D clk-of-pxa1928.o clk-pxa1908-apbc.o diff --git a/drivers/clk/mmp/clk-pxa1908-apbc.c b/drivers/clk/mmp/clk-pxa19= 08-apbc.c new file mode 100644 index 0000000000000000000000000000000000000000..b93d08466198569a975f580a1a3= c27aae2b838c2 --- /dev/null +++ b/drivers/clk/mmp/clk-pxa1908-apbc.c @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include +#include +#include +#include + +#include + +#include "clk.h" + +#define APBC_UART0 0x0 +#define APBC_UART1 0x4 +#define APBC_GPIO 0x8 +#define APBC_PWM0 0xc +#define APBC_PWM1 0x10 +#define APBC_PWM2 0x14 +#define APBC_PWM3 0x18 +#define APBC_SSP0 0x1c +#define APBC_SSP1 0x20 +#define APBC_IPC_RST 0x24 +#define APBC_RTC 0x28 +#define APBC_TWSI0 0x2c +#define APBC_KPC 0x30 +#define APBC_SWJTAG 0x40 +#define APBC_SSP2 0x4c +#define APBC_TWSI1 0x60 +#define APBC_THERMAL 0x6c +#define APBC_TWSI3 0x70 + +#define APBC_NR_CLKS 19 + +struct pxa1908_clk_unit { + struct mmp_clk_unit unit; + void __iomem *base; +}; + +static DEFINE_SPINLOCK(pwm0_lock); +static DEFINE_SPINLOCK(pwm2_lock); + +static DEFINE_SPINLOCK(uart0_lock); +static DEFINE_SPINLOCK(uart1_lock); + +static const char * const uart_parent_names[] =3D {"pll1_117", "uart_pll"}; +static const char * const ssp_parent_names[] =3D {"pll1_d16", "pll1_d48", = "pll1_d24", "pll1_d12"}; + +static struct mmp_param_gate_clk apbc_gate_clks[] =3D { + {PXA1908_CLK_TWSI0, "twsi0_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_TWS= I0, 0x7, 3, 0, 0, NULL}, + {PXA1908_CLK_TWSI1, "twsi1_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_TWS= I1, 0x7, 3, 0, 0, NULL}, + {PXA1908_CLK_TWSI3, "twsi3_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_TWS= I3, 0x7, 3, 0, 0, NULL}, + {PXA1908_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, = 0x7, 3, 0, 0, NULL}, + {PXA1908_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x7,= 3, 0, MMP_CLK_GATE_NEED_DELAY, NULL}, + {PXA1908_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x87= , 0x83, 0, MMP_CLK_GATE_NEED_DELAY, NULL}, + {PXA1908_CLK_PWM0, "pwm0_clk", "pwm01_apb_share", CLK_SET_RATE_PARENT, AP= BC_PWM0, 0x2, 2, 0, 0, &pwm0_lock}, + {PXA1908_CLK_PWM1, "pwm1_clk", "pwm01_apb_share", CLK_SET_RATE_PARENT, AP= BC_PWM1, 0x6, 2, 0, 0, NULL}, + {PXA1908_CLK_PWM2, "pwm2_clk", "pwm23_apb_share", CLK_SET_RATE_PARENT, AP= BC_PWM2, 0x2, 2, 0, 0, NULL}, + {PXA1908_CLK_PWM3, "pwm3_clk", "pwm23_apb_share", CLK_SET_RATE_PARENT, AP= BC_PWM3, 0x6, 2, 0, 0, NULL}, + {PXA1908_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_U= ART0, 0x7, 3, 0, 0, &uart0_lock}, + {PXA1908_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_U= ART1, 0x7, 3, 0, 0, &uart1_lock}, + {PXA1908_CLK_THERMAL, "thermal_clk", NULL, 0, APBC_THERMAL, 0x7, 3, 0, 0,= NULL}, + {PXA1908_CLK_IPC_RST, "ipc_clk", NULL, 0, APBC_IPC_RST, 0x7, 3, 0, 0, NUL= L}, + {PXA1908_CLK_SSP0, "ssp0_clk", "ssp0_mux", 0, APBC_SSP0, 0x7, 3, 0, 0, NU= LL}, + {PXA1908_CLK_SSP2, "ssp2_clk", "ssp2_mux", 0, APBC_SSP2, 0x7, 3, 0, 0, NU= LL}, +}; + +static struct mmp_param_mux_clk apbc_mux_clks[] =3D { + {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SE= T_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock}, + {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SE= T_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock}, + {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), 0, APBC_S= SP0, 4, 3, 0, NULL}, + {0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), 0, APBC_S= SP2, 4, 3, 0, NULL}, +}; + +static void pxa1908_apb_periph_clk_init(struct pxa1908_clk_unit *pxa_unit) +{ + struct mmp_clk_unit *unit =3D &pxa_unit->unit; + struct clk *clk; + + mmp_clk_register_gate(NULL, "pwm01_apb_share", "pll1_d48", + CLK_SET_RATE_PARENT, + pxa_unit->base + APBC_PWM0, + 0x5, 1, 0, 0, &pwm0_lock); + mmp_clk_register_gate(NULL, "pwm23_apb_share", "pll1_d48", + CLK_SET_RATE_PARENT, + pxa_unit->base + APBC_PWM2, + 0x5, 1, 0, 0, &pwm2_lock); + clk =3D mmp_clk_register_apbc("swjtag", NULL, + pxa_unit->base + APBC_SWJTAG, 10, 0, NULL); + mmp_clk_add(unit, PXA1908_CLK_SWJTAG, clk); + mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->base, + ARRAY_SIZE(apbc_mux_clks)); + mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->base, + ARRAY_SIZE(apbc_gate_clks)); +} + +static int pxa1908_apbc_probe(struct platform_device *pdev) +{ + struct pxa1908_clk_unit *pxa_unit; + + pxa_unit =3D devm_kzalloc(&pdev->dev, sizeof(*pxa_unit), GFP_KERNEL); + if (IS_ERR(pxa_unit)) + return PTR_ERR(pxa_unit); + + pxa_unit->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pxa_unit->base)) + return PTR_ERR(pxa_unit->base); + + mmp_clk_init(pdev->dev.of_node, &pxa_unit->unit, APBC_NR_CLKS); + + pxa1908_apb_periph_clk_init(pxa_unit); + + return 0; +} + +static const struct of_device_id pxa1908_apbc_match_table[] =3D { + { .compatible =3D "marvell,pxa1908-apbc" }, + { } +}; +MODULE_DEVICE_TABLE(of, pxa1908_apbc_match_table); + +static struct platform_driver pxa1908_apbc_driver =3D { + .probe =3D pxa1908_apbc_probe, + .driver =3D { + .name =3D "pxa1908-apbc", + .of_match_table =3D pxa1908_apbc_match_table + } +}; +module_platform_driver(pxa1908_apbc_driver); + +MODULE_AUTHOR("Duje Mihanovi=C4=87 "); +MODULE_DESCRIPTION("Marvell PXA1908 APBC Clock Driver"); +MODULE_LICENSE("GPL"); --=20 2.46.2 From nobody Thu Nov 28 11:30:01 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 94E061C9B76; Tue, 1 Oct 2024 14:39:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727793568; cv=none; b=hw7wLOlFRL069wEnC633Wf6MUxwB6xTyvXxILIBBAPgYRCxveA6yhKf5kPZsgHCF3lFCXLzSHQYCPWjrEyRsK7AmekeL6uzKPBg8cMQctnmmE5yciq3J5bl9jE2LJEJbUmEX02E/N1xG7nVSzoNvraVvcnM2REqfZZ56jS1tNEc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727793568; c=relaxed/simple; bh=pOVGf9oma8m/uk8UYl/aTmt4jeyftpA7nP589qoLT7Q=; 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Tue, 1 Oct 2024 14:39:28 +0000 (UTC) From: =?utf-8?q?Duje_Mihanovi=C4=87_via_B4_Relay?= Date: Tue, 01 Oct 2024 16:37:36 +0200 Subject: [PATCH v13 06/12] clk: mmp: Add Marvell PXA1908 APBCP driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241001-pxa1908-lkml-v13-6-6b9a7f64f9ae@skole.hr> References: <20241001-pxa1908-lkml-v13-0-6b9a7f64f9ae@skole.hr> In-Reply-To: <20241001-pxa1908-lkml-v13-0-6b9a7f64f9ae@skole.hr> To: Michael Turquette , Stephen Boyd , Linus Walleij , Rob Herring , Conor Dooley , Tony Lindgren , Haojian Zhuang , =?utf-8?q?Duje_Mihanovi=C4=87?= , Lubomir Rintel , Catalin Marinas , Will Deacon , Rob Herring , Krzysztof Kozlowski Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Karel Balej , David Wronek , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3743; i=duje.mihanovic@skole.hr; s=20240706; h=from:subject:message-id; bh=2YEQvX+kbOqYyF1VUDj2VpxW3KDCmlPyBE8tlQ5VbOU=; b=owGbwMvMwCW21nBykGv/WmbG02pJDGl/OCe5J/MYcyw4qSfwUbL1lLXfqUN3dkdtWL3HbG5GW vvC7LaujlIWBjEuBlkxRZbc/47XeD+LbN2evcwAZg4rE8gQBi5OAZhI+nOGfwb/f3fNLPnopn7V T6/n7z3DE3MuTYl5Fl51vSCvQ7taaDHDH94E56LO999CJPzkjDir3/NeU3uSknh05+u9wTuz8iY 7cgAA X-Developer-Key: i=duje.mihanovic@skole.hr; a=openpgp; fpr=6DFF41D60DF314B5B76BA630AD319352458FAD03 X-Endpoint-Received: by B4 Relay for duje.mihanovic@skole.hr/20240706 with auth_id=191 X-Original-From: =?utf-8?q?Duje_Mihanovi=C4=87?= Reply-To: duje.mihanovic@skole.hr From: Duje Mihanovi=C4=87 Add driver for the APBCP controller block found on Marvell's PXA1908 SoC. Signed-off-by: Duje Mihanovi=C4=87 --- drivers/clk/mmp/Makefile | 2 +- drivers/clk/mmp/clk-pxa1908-apbcp.c | 82 +++++++++++++++++++++++++++++++++= ++++ 2 files changed, 83 insertions(+), 1 deletion(-) diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile index 685bb80f8ae1f16d967dc4f6f5a6ce4e3f52d2bd..038bcd4d035e1807973f5094db5= 565fe437e0650 100644 --- a/drivers/clk/mmp/Makefile +++ b/drivers/clk/mmp/Makefile @@ -11,4 +11,4 @@ obj-$(CONFIG_MACH_MMP_DT) +=3D clk-of-pxa168.o clk-of-pxa= 910.o obj-$(CONFIG_COMMON_CLK_MMP2) +=3D clk-of-mmp2.o clk-pll.o pwr-island.o obj-$(CONFIG_COMMON_CLK_MMP2_AUDIO) +=3D clk-audio.o =20 -obj-$(CONFIG_ARCH_MMP) +=3D clk-of-pxa1928.o clk-pxa1908-apbc.o +obj-$(CONFIG_ARCH_MMP) +=3D clk-of-pxa1928.o clk-pxa1908-apbc.o clk-pxa190= 8-apbcp.o diff --git a/drivers/clk/mmp/clk-pxa1908-apbcp.c b/drivers/clk/mmp/clk-pxa1= 908-apbcp.c new file mode 100644 index 0000000000000000000000000000000000000000..08f3845cbb1becfa08e82e6e7fd= 8cb8aac7a0385 --- /dev/null +++ b/drivers/clk/mmp/clk-pxa1908-apbcp.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include +#include +#include +#include + +#include + +#include "clk.h" + +#define APBCP_UART2 0x1c +#define APBCP_TWSI2 0x28 +#define APBCP_AICER 0x38 + +#define APBCP_NR_CLKS 4 + +struct pxa1908_clk_unit { + struct mmp_clk_unit unit; + void __iomem *base; +}; + +static DEFINE_SPINLOCK(uart2_lock); + +static const char * const uart_parent_names[] =3D {"pll1_117", "uart_pll"}; + +static struct mmp_param_gate_clk apbcp_gate_clks[] =3D { + {PXA1908_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBCP_= UART2, 0x7, 0x3, 0x0, 0, &uart2_lock}, + {PXA1908_CLK_TWSI2, "twsi2_clk", "pll1_32", CLK_SET_RATE_PARENT, APBCP_TW= SI2, 0x7, 0x3, 0x0, 0, NULL}, + {PXA1908_CLK_AICER, "ripc_clk", NULL, 0, APBCP_AICER, 0x7, 0x2, 0x0, 0, N= ULL}, +}; + +static struct mmp_param_mux_clk apbcp_mux_clks[] =3D { + {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SE= T_RATE_PARENT, APBCP_UART2, 4, 3, 0, &uart2_lock}, +}; + +static void pxa1908_apb_p_periph_clk_init(struct pxa1908_clk_unit *pxa_uni= t) +{ + struct mmp_clk_unit *unit =3D &pxa_unit->unit; + + mmp_register_mux_clks(unit, apbcp_mux_clks, pxa_unit->base, + ARRAY_SIZE(apbcp_mux_clks)); + mmp_register_gate_clks(unit, apbcp_gate_clks, pxa_unit->base, + ARRAY_SIZE(apbcp_gate_clks)); +} + +static int pxa1908_apbcp_probe(struct platform_device *pdev) +{ + struct pxa1908_clk_unit *pxa_unit; + + pxa_unit =3D devm_kzalloc(&pdev->dev, sizeof(*pxa_unit), GFP_KERNEL); + if (IS_ERR(pxa_unit)) + return PTR_ERR(pxa_unit); + + pxa_unit->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pxa_unit->base)) + return PTR_ERR(pxa_unit->base); + + mmp_clk_init(pdev->dev.of_node, &pxa_unit->unit, APBCP_NR_CLKS); + + pxa1908_apb_p_periph_clk_init(pxa_unit); + + return 0; +} + +static const struct of_device_id pxa1908_apbcp_match_table[] =3D { + { .compatible =3D "marvell,pxa1908-apbcp" }, + { } +}; +MODULE_DEVICE_TABLE(of, pxa1908_apbcp_match_table); + +static struct platform_driver pxa1908_apbcp_driver =3D { + .probe =3D pxa1908_apbcp_probe, + .driver =3D { + .name =3D "pxa1908-apbcp", + .of_match_table =3D pxa1908_apbcp_match_table + } +}; +module_platform_driver(pxa1908_apbcp_driver); + +MODULE_AUTHOR("Duje Mihanovi=C4=87 "); +MODULE_DESCRIPTION("Marvell PXA1908 APBCP Clock Driver"); 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Tue, 1 Oct 2024 14:39:28 +0000 (UTC) From: =?utf-8?q?Duje_Mihanovi=C4=87_via_B4_Relay?= Date: Tue, 01 Oct 2024 16:37:37 +0200 Subject: [PATCH v13 07/12] clk: mmp: Add Marvell PXA1908 APMU driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241001-pxa1908-lkml-v13-7-6b9a7f64f9ae@skole.hr> References: <20241001-pxa1908-lkml-v13-0-6b9a7f64f9ae@skole.hr> In-Reply-To: <20241001-pxa1908-lkml-v13-0-6b9a7f64f9ae@skole.hr> To: Michael Turquette , Stephen Boyd , Linus Walleij , Rob Herring , Conor Dooley , Tony Lindgren , Haojian Zhuang , =?utf-8?q?Duje_Mihanovi=C4=87?= , Lubomir Rintel , Catalin Marinas , Will Deacon , Rob Herring , Krzysztof Kozlowski Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Karel Balej , David Wronek , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5711; i=duje.mihanovic@skole.hr; s=20240706; h=from:subject:message-id; bh=/e1QDBHbcqt1WTOt/jn7y8ePbKdHC3S7QBtRcOByp3w=; b=owGbwMvMwCW21nBykGv/WmbG02pJDGl/OCdFlhQ/PxjWwy7lt0/9/NqdS84H3OOZ6bfq4+/7z zLf28g+6ihlYRDjYpAVU2TJ/e94jfezyNbt2csMYOawMoEMYeDiFICJbDZhZLgyNc/xyuluBs+X vkvVmtW1zp0Skrzop3e8beWXTzf/rBZn+CtV7XlO4XtT40H2YIOjG6Z/vn1IY5uViX+Z+re0N/G 5l/gA X-Developer-Key: i=duje.mihanovic@skole.hr; a=openpgp; fpr=6DFF41D60DF314B5B76BA630AD319352458FAD03 X-Endpoint-Received: by B4 Relay for duje.mihanovic@skole.hr/20240706 with auth_id=191 X-Original-From: =?utf-8?q?Duje_Mihanovi=C4=87?= Reply-To: duje.mihanovic@skole.hr From: Duje Mihanovi=C4=87 Add driver for the APMU controller block found on Marvell's PXA1908 SoC. This driver is incomplete, lacking support for (at least) GPU, VPU, DSI and CCIC (camera related) clocks. Signed-off-by: Duje Mihanovi=C4=87 --- drivers/clk/mmp/Makefile | 2 +- drivers/clk/mmp/clk-pxa1908-apmu.c | 121 +++++++++++++++++++++++++++++++++= ++++ 2 files changed, 122 insertions(+), 1 deletion(-) diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile index 038bcd4d035e1807973f5094db5565fe437e0650..a8b1a4b08824bc0ee7e6541a670= 808f31bf40240 100644 --- a/drivers/clk/mmp/Makefile +++ b/drivers/clk/mmp/Makefile @@ -11,4 +11,4 @@ obj-$(CONFIG_MACH_MMP_DT) +=3D clk-of-pxa168.o clk-of-pxa= 910.o obj-$(CONFIG_COMMON_CLK_MMP2) +=3D clk-of-mmp2.o clk-pll.o pwr-island.o obj-$(CONFIG_COMMON_CLK_MMP2_AUDIO) +=3D clk-audio.o =20 -obj-$(CONFIG_ARCH_MMP) +=3D clk-of-pxa1928.o clk-pxa1908-apbc.o clk-pxa190= 8-apbcp.o +obj-$(CONFIG_ARCH_MMP) +=3D clk-of-pxa1928.o clk-pxa1908-apbc.o clk-pxa190= 8-apbcp.o clk-pxa1908-apmu.o diff --git a/drivers/clk/mmp/clk-pxa1908-apmu.c b/drivers/clk/mmp/clk-pxa19= 08-apmu.c new file mode 100644 index 0000000000000000000000000000000000000000..8cfb1258202f6f312a7c01128ad= 91d1b02b3cffc --- /dev/null +++ b/drivers/clk/mmp/clk-pxa1908-apmu.c @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include +#include +#include +#include + +#include + +#include "clk.h" + +#define APMU_CLK_GATE_CTRL 0x40 +#define APMU_CCIC1 0x24 +#define APMU_ISP 0x38 +#define APMU_DSI1 0x44 +#define APMU_DISP1 0x4c +#define APMU_CCIC0 0x50 +#define APMU_SDH0 0x54 +#define APMU_SDH1 0x58 +#define APMU_USB 0x5c +#define APMU_NF 0x60 +#define APMU_VPU 0xa4 +#define APMU_GC 0xcc +#define APMU_SDH2 0xe0 +#define APMU_GC2D 0xf4 +#define APMU_TRACE 0x108 +#define APMU_DVC_DFC_DEBUG 0x140 + +#define APMU_NR_CLKS 17 + +struct pxa1908_clk_unit { + struct mmp_clk_unit unit; + void __iomem *base; +}; + +static DEFINE_SPINLOCK(pll1_lock); +static struct mmp_param_general_gate_clk pll1_gate_clks[] =3D { + {PXA1908_CLK_PLL1_D2_GATE, "pll1_d2_gate", "pll1_d2", 0, APMU_CLK_GATE_CT= RL, 29, 0, &pll1_lock}, + {PXA1908_CLK_PLL1_416_GATE, "pll1_416_gate", "pll1_416", 0, APMU_CLK_GATE= _CTRL, 27, 0, &pll1_lock}, + {PXA1908_CLK_PLL1_624_GATE, "pll1_624_gate", "pll1_624", 0, APMU_CLK_GATE= _CTRL, 26, 0, &pll1_lock}, + {PXA1908_CLK_PLL1_832_GATE, "pll1_832_gate", "pll1_832", 0, APMU_CLK_GATE= _CTRL, 30, 0, &pll1_lock}, + {PXA1908_CLK_PLL1_1248_GATE, "pll1_1248_gate", "pll1_1248", 0, APMU_CLK_G= ATE_CTRL, 28, 0, &pll1_lock}, +}; + +static DEFINE_SPINLOCK(sdh0_lock); +static DEFINE_SPINLOCK(sdh1_lock); +static DEFINE_SPINLOCK(sdh2_lock); + +static const char * const sdh_parent_names[] =3D {"pll1_416", "pll1_624"}; + +static struct mmp_clk_mix_config sdh_mix_config =3D { + .reg_info =3D DEFINE_MIX_REG_INFO(3, 8, 2, 6, 11), +}; + +static struct mmp_param_gate_clk apmu_gate_clks[] =3D { + {PXA1908_CLK_USB, "usb_clk", NULL, 0, APMU_USB, 0x9, 0x9, 0x1, 0, NULL}, + {PXA1908_CLK_SDH0, "sdh0_clk", "sdh0_mix_clk", CLK_SET_RATE_PARENT | CLK_= SET_RATE_UNGATE, APMU_SDH0, 0x12, 0x12, 0x0, 0, &sdh0_lock}, + {PXA1908_CLK_SDH1, "sdh1_clk", "sdh1_mix_clk", CLK_SET_RATE_PARENT | CLK_= SET_RATE_UNGATE, APMU_SDH1, 0x12, 0x12, 0x0, 0, &sdh1_lock}, + {PXA1908_CLK_SDH2, "sdh2_clk", "sdh2_mix_clk", CLK_SET_RATE_PARENT | CLK_= SET_RATE_UNGATE, APMU_SDH2, 0x12, 0x12, 0x0, 0, &sdh2_lock} +}; + +static void pxa1908_axi_periph_clk_init(struct pxa1908_clk_unit *pxa_unit) +{ + struct mmp_clk_unit *unit =3D &pxa_unit->unit; + + mmp_register_general_gate_clks(unit, pll1_gate_clks, + pxa_unit->base, ARRAY_SIZE(pll1_gate_clks)); + + sdh_mix_config.reg_info.reg_clk_ctrl =3D pxa_unit->base + APMU_SDH0; + mmp_clk_register_mix(NULL, "sdh0_mix_clk", sdh_parent_names, + ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, + &sdh_mix_config, &sdh0_lock); + sdh_mix_config.reg_info.reg_clk_ctrl =3D pxa_unit->base + APMU_SDH1; + mmp_clk_register_mix(NULL, "sdh1_mix_clk", sdh_parent_names, + ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, + &sdh_mix_config, &sdh1_lock); + sdh_mix_config.reg_info.reg_clk_ctrl =3D pxa_unit->base + APMU_SDH2; + mmp_clk_register_mix(NULL, "sdh2_mix_clk", sdh_parent_names, + ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, + &sdh_mix_config, &sdh2_lock); + + mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->base, + ARRAY_SIZE(apmu_gate_clks)); +} + +static int pxa1908_apmu_probe(struct platform_device *pdev) +{ + struct pxa1908_clk_unit *pxa_unit; + + pxa_unit =3D devm_kzalloc(&pdev->dev, sizeof(*pxa_unit), GFP_KERNEL); + if (IS_ERR(pxa_unit)) + return PTR_ERR(pxa_unit); + + pxa_unit->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pxa_unit->base)) + return PTR_ERR(pxa_unit->base); + + mmp_clk_init(pdev->dev.of_node, &pxa_unit->unit, APMU_NR_CLKS); + + pxa1908_axi_periph_clk_init(pxa_unit); + + return 0; +} + +static const struct of_device_id pxa1908_apmu_match_table[] =3D { + { .compatible =3D "marvell,pxa1908-apmu" }, + { } +}; +MODULE_DEVICE_TABLE(of, pxa1908_apmu_match_table); + +static struct platform_driver pxa1908_apmu_driver =3D { + .probe =3D pxa1908_apmu_probe, + .driver =3D { + .name =3D "pxa1908-apmu", + .of_match_table =3D pxa1908_apmu_match_table + } +}; +module_platform_driver(pxa1908_apmu_driver); + +MODULE_AUTHOR("Duje Mihanovi=C4=87 "); +MODULE_DESCRIPTION("Marvell PXA1908 APMU Clock Driver"); +MODULE_LICENSE("GPL"); --=20 2.46.2 From nobody Thu Nov 28 11:30:01 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BEBAB1C9B97; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241001-pxa1908-lkml-v13-8-6b9a7f64f9ae@skole.hr> References: <20241001-pxa1908-lkml-v13-0-6b9a7f64f9ae@skole.hr> In-Reply-To: <20241001-pxa1908-lkml-v13-0-6b9a7f64f9ae@skole.hr> To: Michael Turquette , Stephen Boyd , Linus Walleij , Rob Herring , Conor Dooley , Tony Lindgren , Haojian Zhuang , =?utf-8?q?Duje_Mihanovi=C4=87?= , Lubomir Rintel , Catalin Marinas , Will Deacon , Rob Herring , Krzysztof Kozlowski Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Karel Balej , David Wronek , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5045; i=duje.mihanovic@skole.hr; s=20240706; h=from:subject:message-id; bh=zfBMzyW2I685n3ooZjWXhrcGIijp9n//AC06yR6x3YA=; b=owGbwMvMwCW21nBykGv/WmbG02pJDGl/OCepn2v7WTBfaG9fZa2w9ekTzF38f9/d+NP42K9Sg Mv2UDpXRykLgxgXg6yYIkvuf8drvJ9Ftm7PXmYAM4eVCWQIAxenAEzkqxrD/5Kfa7U0Cq7fufWH 8eW+HXNOWU1eJuKh3sn0ifWX/fp8v/8M/+vyAkqXC1zcUt7GtjFPWjhTOWTu4+7zt6dHf8qwm36 jlwkA X-Developer-Key: i=duje.mihanovic@skole.hr; a=openpgp; fpr=6DFF41D60DF314B5B76BA630AD319352458FAD03 X-Endpoint-Received: by B4 Relay for duje.mihanovic@skole.hr/20240706 with auth_id=191 X-Original-From: =?utf-8?q?Duje_Mihanovi=C4=87?= Reply-To: duje.mihanovic@skole.hr From: Duje Mihanovi=C4=87 Add driver for the MPMU controller block on Marvell's PXA1908 SoC. The driver is incomplete, currently only supporting the fixed PLL1; dynamic PLLs 2-4 and CPU/DDR/AXI clock support is missing. Signed-off-by: Duje Mihanovi=C4=87 --- drivers/clk/mmp/Makefile | 2 +- drivers/clk/mmp/clk-pxa1908-mpmu.c | 112 +++++++++++++++++++++++++++++++++= ++++ 2 files changed, 113 insertions(+), 1 deletion(-) diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile index a8b1a4b08824bc0ee7e6541a670808f31bf40240..062cd87fa8ddcc6808b6236f8c4= dd524aaf02030 100644 --- a/drivers/clk/mmp/Makefile +++ b/drivers/clk/mmp/Makefile @@ -11,4 +11,4 @@ obj-$(CONFIG_MACH_MMP_DT) +=3D clk-of-pxa168.o clk-of-pxa= 910.o obj-$(CONFIG_COMMON_CLK_MMP2) +=3D clk-of-mmp2.o clk-pll.o pwr-island.o obj-$(CONFIG_COMMON_CLK_MMP2_AUDIO) +=3D clk-audio.o =20 -obj-$(CONFIG_ARCH_MMP) +=3D clk-of-pxa1928.o clk-pxa1908-apbc.o clk-pxa190= 8-apbcp.o clk-pxa1908-apmu.o +obj-$(CONFIG_ARCH_MMP) +=3D clk-of-pxa1928.o clk-pxa1908-apbc.o clk-pxa190= 8-apbcp.o clk-pxa1908-apmu.o clk-pxa1908-mpmu.o diff --git a/drivers/clk/mmp/clk-pxa1908-mpmu.c b/drivers/clk/mmp/clk-pxa19= 08-mpmu.c new file mode 100644 index 0000000000000000000000000000000000000000..e3337bacaadd5ad49b1258ba386= 32c7e5f103d93 --- /dev/null +++ b/drivers/clk/mmp/clk-pxa1908-mpmu.c @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include +#include +#include +#include +#include + +#include + +#include "clk.h" + +#define MPMU_UART_PLL 0x14 + +#define MPMU_NR_CLKS 39 + +struct pxa1908_clk_unit { + struct mmp_clk_unit unit; + void __iomem *base; +}; + +static struct mmp_param_fixed_rate_clk fixed_rate_clks[] =3D { + {PXA1908_CLK_CLK32, "clk32", NULL, 0, 32768}, + {PXA1908_CLK_VCTCXO, "vctcxo", NULL, 0, 26 * HZ_PER_MHZ}, + {PXA1908_CLK_PLL1_624, "pll1_624", NULL, 0, 624 * HZ_PER_MHZ}, + {PXA1908_CLK_PLL1_416, "pll1_416", NULL, 0, 416 * HZ_PER_MHZ}, + {PXA1908_CLK_PLL1_499, "pll1_499", NULL, 0, 499 * HZ_PER_MHZ}, + {PXA1908_CLK_PLL1_832, "pll1_832", NULL, 0, 832 * HZ_PER_MHZ}, + {PXA1908_CLK_PLL1_1248, "pll1_1248", NULL, 0, 1248 * HZ_PER_MHZ}, +}; + +static struct mmp_param_fixed_factor_clk fixed_factor_clks[] =3D { + {PXA1908_CLK_PLL1_D2, "pll1_d2", "pll1_624", 1, 2, 0}, + {PXA1908_CLK_PLL1_D4, "pll1_d4", "pll1_d2", 1, 2, 0}, + {PXA1908_CLK_PLL1_D6, "pll1_d6", "pll1_d2", 1, 3, 0}, + {PXA1908_CLK_PLL1_D8, "pll1_d8", "pll1_d4", 1, 2, 0}, + {PXA1908_CLK_PLL1_D12, "pll1_d12", "pll1_d6", 1, 2, 0}, + {PXA1908_CLK_PLL1_D13, "pll1_d13", "pll1_624", 1, 13, 0}, + {PXA1908_CLK_PLL1_D16, "pll1_d16", "pll1_d8", 1, 2, 0}, + {PXA1908_CLK_PLL1_D24, "pll1_d24", "pll1_d12", 1, 2, 0}, + {PXA1908_CLK_PLL1_D48, "pll1_d48", "pll1_d24", 1, 2, 0}, + {PXA1908_CLK_PLL1_D96, "pll1_d96", "pll1_d48", 1, 2, 0}, + {PXA1908_CLK_PLL1_32, "pll1_32", "pll1_d13", 2, 3, 0}, + {PXA1908_CLK_PLL1_208, "pll1_208", "pll1_d2", 2, 3, 0}, + {PXA1908_CLK_PLL1_117, "pll1_117", "pll1_624", 3, 16, 0}, +}; + +static struct u32_fract uart_factor_tbl[] =3D { + {.numerator =3D 8125, .denominator =3D 1536}, /* 14.745MHz */ +}; + +static struct mmp_clk_factor_masks uart_factor_masks =3D { + .factor =3D 2, + .num_mask =3D GENMASK(12, 0), + .den_mask =3D GENMASK(12, 0), + .num_shift =3D 16, + .den_shift =3D 0, +}; + +static void pxa1908_pll_init(struct pxa1908_clk_unit *pxa_unit) +{ + struct mmp_clk_unit *unit =3D &pxa_unit->unit; + + mmp_register_fixed_rate_clks(unit, fixed_rate_clks, + ARRAY_SIZE(fixed_rate_clks)); + + mmp_register_fixed_factor_clks(unit, fixed_factor_clks, + ARRAY_SIZE(fixed_factor_clks)); + + mmp_clk_register_factor("uart_pll", "pll1_d4", + CLK_SET_RATE_PARENT, + pxa_unit->base + MPMU_UART_PLL, + &uart_factor_masks, uart_factor_tbl, + ARRAY_SIZE(uart_factor_tbl), NULL); +} + +static int pxa1908_mpmu_probe(struct platform_device *pdev) +{ + struct pxa1908_clk_unit *pxa_unit; + + pxa_unit =3D devm_kzalloc(&pdev->dev, sizeof(*pxa_unit), GFP_KERNEL); + if (IS_ERR(pxa_unit)) + return PTR_ERR(pxa_unit); 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a=openpgp; fpr=6DFF41D60DF314B5B76BA630AD319352458FAD03 X-Endpoint-Received: by B4 Relay for duje.mihanovic@skole.hr/20240706 with auth_id=191 X-Original-From: =?utf-8?q?Duje_Mihanovi=C4=87?= Reply-To: duje.mihanovic@skole.hr From: Duje Mihanovi=C4=87 Add dt bindings for the Marvell PXA1908 SoC and the Samsung Galaxy Core Prime VE LTE phone (model number SM-G361F) using the SoC. The SoC comes with 4 Cortex-A53 cores clocked up to ~1.2GHz and a Vivante GC7000UL GPU. The phone also has a 4.5" 480x800 touchscreen, 8GB eMMC and 1GB of LPDDR3 RAM. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Duje Mihanovi=C4=87 --- Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml b/Documen= tation/devicetree/bindings/arm/mrvl/mrvl.yaml index 4c43eaf3632e4ec8e7d9aeac62f7204e2af4405a..f73bb8ec3a1a1b9594eb059b72d= 95dcbf8c87c6b 100644 --- a/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml +++ b/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml @@ -35,6 +35,11 @@ properties: - enum: - dell,wyse-ariel - const: marvell,mmp3 + - description: PXA1908 based boards + items: + - enum: + - samsung,coreprimevelte + - const: marvell,pxa1908 =20 additionalProperties: true =20 --=20 2.46.2 From nobody Thu Nov 28 11:30:01 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB1061C9DE6; Tue, 1 Oct 2024 14:39:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727793569; cv=none; b=DBJg0/MgH3MV7R8PyaIDJC0eU6A5h/Yrzur81pU9UnjAZR8AduibgODbLc7wiG7+UZLv7pHhsa+ZRnu7+NP2Uyq/m2AWKpXFsqE1qfsLlJD5y/03DIjHBJ7gJuvUZln3Br3kibsx83nrmf4D8IfKh7A+T89XOnm8q3dp3DC9n10= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727793569; c=relaxed/simple; bh=mYWEdE//FULK0qxAD5yB/3zDFvbyDKytJVQXMmCHOpw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rAswrTfUPEsDJb9msvrsi2YgseyylRHDyuyLWBN6aYEkA4FR/L6utDkADro7RVuddP6IBHrPviVoqmesCcELwqtJffJ+TWTwO2wy3TasM/NgeyjEY140vIw9214q6cL/cpmyRxUaLfbEnJNogAlt2sXEQlIpz/BKaXGhhTZdOp4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=h1M1F9yP; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="h1M1F9yP" Received: by smtp.kernel.org (Postfix) with ESMTPS id C0D1BC4DDE2; Tue, 1 Oct 2024 14:39:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1727793568; bh=mYWEdE//FULK0qxAD5yB/3zDFvbyDKytJVQXMmCHOpw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=h1M1F9yPuTTr0WIRhAgC0ZkiIKfxDoIwzOPAEcmmAPlVpyvXq1f81PJWIW+Zfg/rc ORIgO20Fvo05uS8pqF16q1CxExmv9AKZ0pcwBd2VFMF2mG3inYPamo6GxFbVAWE+oy Mj14q8WlyPy1VJ8LCyQ5koHmD1voaJWhScVE78ozR8z10DpItIrUcI6uGwsXyLTl8d k09yZFUyJjAcfi1TN89vj8GWNHVmzBJoeCWxY92V+dsAnnw9Dctpdd3qMOcgOTe5tE SenTk+KywpQsIoLcmFQoOU3F1N5p7BLbmQJuAJ6szBC/9Nyeyw96sDaS1BvK3CSCSn MGIRl9MjTNgKg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2AFECEACD6; Tue, 1 Oct 2024 14:39:28 +0000 (UTC) From: =?utf-8?q?Duje_Mihanovi=C4=87_via_B4_Relay?= Date: Tue, 01 Oct 2024 16:37:40 +0200 Subject: [PATCH v13 10/12] arm64: Kconfig.platforms: Add config for Marvell PXA1908 platform Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241001-pxa1908-lkml-v13-10-6b9a7f64f9ae@skole.hr> References: <20241001-pxa1908-lkml-v13-0-6b9a7f64f9ae@skole.hr> In-Reply-To: <20241001-pxa1908-lkml-v13-0-6b9a7f64f9ae@skole.hr> To: Michael Turquette , Stephen Boyd , Linus Walleij , Rob Herring , Conor Dooley , Tony Lindgren , Haojian Zhuang , =?utf-8?q?Duje_Mihanovi=C4=87?= , Lubomir Rintel , Catalin Marinas , Will Deacon , Rob Herring , Krzysztof Kozlowski Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Karel Balej , David Wronek , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=911; i=duje.mihanovic@skole.hr; s=20240706; h=from:subject:message-id; bh=tQRucUNiycqO1XW8ycQFY99fu+HGVhgzKCsVcf8lGtE=; b=owGbwMvMwCW21nBykGv/WmbG02pJDGl/OCeHN/r1HVB7uJiBv+Kb45Wt8zZsXK356rKbEsvCp zdYRd56dJSyMIhxMciKKbLk/ne8xvtZZOv27GUGMHNYmUCGMHBxCsBE5I4wMsxuPtC1/8vHHdpq S1O+FPDeqH7EL3W0Z9V9kR7PjRuV99xh+O+ydmbDDN6qGb495SUvvj/VWn/f45qNhm+Z9vNECQW R14wA X-Developer-Key: i=duje.mihanovic@skole.hr; a=openpgp; fpr=6DFF41D60DF314B5B76BA630AD319352458FAD03 X-Endpoint-Received: by B4 Relay for duje.mihanovic@skole.hr/20240706 with auth_id=191 X-Original-From: =?utf-8?q?Duje_Mihanovi=C4=87?= Reply-To: duje.mihanovic@skole.hr From: Duje Mihanovi=C4=87 Add ARCH_MMP configuration option for Marvell PXA1908 SoC. Signed-off-by: Duje Mihanovi=C4=87 --- arch/arm64/Kconfig.platforms | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 6c6d11536b42ec6e878db8d355c17994c2500d7b..6cb21a27844718d8dfbdc49cc76= 4a6ca39296484 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -175,6 +175,14 @@ config ARCH_MESON This enables support for the arm64 based Amlogic SoCs such as the s905, S905X/D, S912, A113X/D or S905X/D2 =20 +config ARCH_MMP + bool "Marvell MMP SoC Family" + select PINCTRL + select PINCTRL_SINGLE + help + This enables support for Marvell MMP SoC family, currently + supporting PXA1908 aka IAP140. + config ARCH_MVEBU bool "Marvell EBU SoC Family" select ARMADA_AP806_SYSCON --=20 2.46.2 From nobody Thu Nov 28 11:30:01 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 296EF1C9EBB; Tue, 1 Oct 2024 14:39:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727793569; cv=none; b=De3PLFsxhoT4h5dK9BtpwzSew8KEBDXyCgdeWNedvzCXqs6XxY2rmQuIebueDHoerJAoeaccNAjbNVU+cN+xiKWi7Ak1FVPGkZQo1spJ1FjhCQGP0I0Gc1rCCnFPU8XvIaPdhxv1j3eKeC9xZXFuyAc7cEYaw/6aH87GahFxhrY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727793569; c=relaxed/simple; bh=NJM1RcLZvj5mqANrJ2dJ5/WPTCQDqC7Sy+dC3a2Ic2g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=c42jv9PN65R6yvxxxFmYsKSYwyUn65Q2cS+VDs7FjNrx2ZVsDqmt3ow4P9W06Mmh7LBPdiXyfqYKxVDV12yKwePO61+1GCZypc96Qp1W3aLn7B0KywInwAZX10xCeoM/rr5VVWd91AmhMZIGNvfHyoolA5PJR/Wrym9iM7IcjqY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GFhjJltP; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GFhjJltP" Received: by smtp.kernel.org (Postfix) with ESMTPS id D7DECC4DDE4; Tue, 1 Oct 2024 14:39:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1727793568; bh=NJM1RcLZvj5mqANrJ2dJ5/WPTCQDqC7Sy+dC3a2Ic2g=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=GFhjJltPzvFtgLBHsNa7Pu1IXpYsg10LCYTVBwFo9AUXZ/8h056awS7q4xVjKJY5i VZUGyF6KGb9i2UJP63nBTcWhi/iBk3MlN3IhV4oVFA0RmSsDt1E4KDnj5BkkV2GF3F afOfbEB6s2007Tef+Tdqhy+LSOGcgKj8JzCIdQMD6SpCKiKpDM2MzxP2q3V0+0MQyw FZSDMLerOwRgEkmsDJdsD1isHIu2UMCEJgHSGLCm4/dgRpW4JhiAbbL+REZyuQdzkC A7ZWvcowd0NTkjMnRUB2cywNUdiTiMtlmvcOupbMic8eM9TCdLPYr5lTnPUypOOp+i 9af1Iav17+tXA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB4F8CEACD8; Tue, 1 Oct 2024 14:39:28 +0000 (UTC) From: =?utf-8?q?Duje_Mihanovi=C4=87_via_B4_Relay?= Date: Tue, 01 Oct 2024 16:37:41 +0200 Subject: [PATCH v13 11/12] arm64: dts: Add DTS for Marvell PXA1908 and samsung,coreprimevelte Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241001-pxa1908-lkml-v13-11-6b9a7f64f9ae@skole.hr> References: <20241001-pxa1908-lkml-v13-0-6b9a7f64f9ae@skole.hr> In-Reply-To: <20241001-pxa1908-lkml-v13-0-6b9a7f64f9ae@skole.hr> To: Michael Turquette , Stephen Boyd , Linus Walleij , Rob Herring , Conor Dooley , Tony Lindgren , Haojian Zhuang , =?utf-8?q?Duje_Mihanovi=C4=87?= , Lubomir Rintel , Catalin Marinas , Will Deacon , Rob Herring , Krzysztof Kozlowski Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Karel Balej , David Wronek , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=17136; i=duje.mihanovic@skole.hr; s=20240706; h=from:subject:message-id; bh=ccRB1eAYdLvAWzlusYd1y9DoNR12xbtpU1oRcqkq0Cg=; b=owGbwMvMwCW21nBykGv/WmbG02pJDGl/OCc73fH7I+a5b/mzfS/3OVx63X3Z7s0O3WtSeW+f2 IrtYvvb21HKwiDGxSArpsiS+9/xGu9nka3bs5cZwMxhZQIZwsDFKQATeV3E8D+l5ZPwkxUv48rj 6r1OzRcR6JkQIHSvwLpkg0BARtKvP24Mv5ir5mw0dPDpl2peOf9Wi72FlfeHXUdKDui+zWnTfWv qwAIA X-Developer-Key: i=duje.mihanovic@skole.hr; a=openpgp; fpr=6DFF41D60DF314B5B76BA630AD319352458FAD03 X-Endpoint-Received: by B4 Relay for duje.mihanovic@skole.hr/20240706 with auth_id=191 X-Original-From: =?utf-8?q?Duje_Mihanovi=C4=87?= Reply-To: duje.mihanovic@skole.hr From: Duje Mihanovi=C4=87 Add DTS for Marvell PXA1908 SoC and Samsung Galaxy Core Prime Value Edition LTE, a smartphone based on said SoC. Signed-off-by: Duje Mihanovi=C4=87 --- arch/arm64/boot/dts/marvell/Makefile | 3 + .../dts/marvell/pxa1908-samsung-coreprimevelte.dts | 336 +++++++++++++++++= ++++ arch/arm64/boot/dts/marvell/pxa1908.dtsi | 300 ++++++++++++++++++ 3 files changed, 639 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/mar= vell/Makefile index ce751b5028e2628834340b5c50f8992092226eba..39c5749e631db33aa8fb0386a95= 1c0a70215bc02 100644 --- a/arch/arm64/boot/dts/marvell/Makefile +++ b/arch/arm64/boot/dts/marvell/Makefile @@ -32,3 +32,6 @@ dtb-$(CONFIG_ARCH_MVEBU) +=3D cn9130-cf-base.dtb dtb-$(CONFIG_ARCH_MVEBU) +=3D cn9130-cf-pro.dtb dtb-$(CONFIG_ARCH_MVEBU) +=3D cn9131-cf-solidwan.dtb dtb-$(CONFIG_ARCH_MVEBU) +=3D cn9132-clearfog.dtb + +# MMP SoC Family +dtb-$(CONFIG_ARCH_MMP) +=3D pxa1908-samsung-coreprimevelte.dtb diff --git a/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts= b/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts new file mode 100644 index 0000000000000000000000000000000000000000..83b789a837d3876bf15ed0d7e10= e190eacdfd56f --- /dev/null +++ b/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts @@ -0,0 +1,336 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include "pxa1908.dtsi" +#include +#include + +/ { + model =3D "Samsung Galaxy Core Prime VE LTE"; + compatible =3D "samsung,coreprimevelte", "marvell,pxa1908"; + + aliases { + mmc0 =3D &sdh2; /* eMMC */ + mmc1 =3D &sdh0; /* SD card */ + serial0 =3D &uart0; + }; + + chosen { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + stdout-path =3D "serial0:115200n8"; + + /* S-Boot places the initramfs here */ + linux,initrd-start =3D <0x4d70000>; + linux,initrd-end =3D <0x5000000>; + + fb0: framebuffer@17177000 { + compatible =3D "simple-framebuffer"; + reg =3D <0 0x17177000 0 (480 * 800 * 4)>; + width =3D <480>; + height =3D <800>; + stride =3D <(480 * 4)>; + format =3D "a8r8g8b8"; + }; + }; + + /* Bootloader fills this in */ + memory { + device_type =3D "memory"; + reg =3D <0 0 0 0>; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + framebuffer@17000000 { + reg =3D <0 0x17000000 0 0x1800000>; + no-map; + }; + + gpu@9000000 { + reg =3D <0 0x9000000 0 0x1000000>; + }; + + /* Communications processor, aka modem */ + cp@5000000 { + reg =3D <0 0x5000000 0 0x3000000>; + }; + + cm3@a000000 { + reg =3D <0 0xa000000 0 0x80000>; + }; + + seclog@8000000 { + reg =3D <0 0x8000000 0 0x100000>; + }; + + ramoops@8100000 { + compatible =3D "ramoops"; + reg =3D <0 0x8100000 0 0x40000>; + record-size =3D <0x8000>; + console-size =3D <0x20000>; + max-reason =3D <5>; + }; + }; + + + i2c-muic { + compatible =3D "i2c-gpio"; + sda-gpios =3D <&gpio 30 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios =3D <&gpio 29 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us =3D <3>; + i2c-gpio,timeout-ms =3D <100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c_muic_pins>; + + muic: extcon@14 { + compatible =3D "siliconmitus,sm5504-muic"; + reg =3D <0x14>; + interrupt-parent =3D <&gpio>; + interrupts =3D <0 IRQ_TYPE_EDGE_FALLING>; + }; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gpio_keys_pins>; + autorepeat; + + key-home { + label =3D "Home"; + linux,code =3D ; + gpios =3D <&gpio 50 GPIO_ACTIVE_LOW>; + }; + + key-volup { + label =3D "Volume Up"; + linux,code =3D ; + gpios =3D <&gpio 16 GPIO_ACTIVE_LOW>; + }; + + key-voldown { + label =3D "Volume Down"; + linux,code =3D ; + gpios =3D <&gpio 17 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&smmu { + status =3D "okay"; +}; + +&pmx { + pinctrl-single,gpio-range =3D <&range 55 55 0>, + <&range 110 32 0>, + <&range 52 1 0>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&board_pins_0 &board_pins_1 &board_pins_2>; + + board_pins_0: board-pins-0 { + pinctrl-single,pins =3D < + 0x160 0 + 0x164 0 + 0x168 0 + 0x16c 0 + >; + pinctrl-single,drive-strength =3D <0x1000 0x1800>; + pinctrl-single,bias-pullup =3D <0x8000 0x8000 0 0xc000>; + pinctrl-single,bias-pulldown =3D <0x8000 0x8000 0 0xa000>; + pinctrl-single,input-schmitt =3D <0 0x30>; + pinctrl-single,input-schmitt-enable =3D <0x40 0 0x40 0x40>; + pinctrl-single,low-power-mode =3D <0x288 0x388>; + }; + + board_pins_1: board-pins-1 { + pinctrl-single,pins =3D < + 0x44 1 + 0x48 1 + 0x20 1 + 0x18 1 + 0x14 1 + 0x10 1 + 0xc 1 + 0x8 1 + 0x68 1 + 0x58 0 + 0x54 0 + 0x7c 0 + 0x6c 0 + 0x70 0 + 0x4c 1 + 0x50 1 + 0xac 0 + 0x90 0 + 0x8c 0 + 0x88 0 + 0x84 0 + 0xc8 0 + 0x128 0 + 0x190 0 + 0x194 0 + 0x1a0 0 + 0x114 0 + 0x118 0 + 0x1d8 0 + 0x1e4 0 + 0xe8 0 + 0x100 0 + 0x204 0 + 0x210 0 + 0x218 0 + >; + pinctrl-single,bias-pullup =3D <0xc000 0xc000 0 0xc000>; + pinctrl-single,bias-pulldown =3D <0x8000 0xa000 0x8000 0xc000>; + pinctrl-single,low-power-mode =3D <0x288 0x388>; + }; + + board_pins_2: board-pins-2 { + pinctrl-single,pins =3D < + 0x260 0 + 0x264 0 + 0x268 0 + 0x26c 0 + 0x270 0 + 0x274 0 + 0x78 0 + 0x74 0 + 0xb0 1 + >; + pinctrl-single,drive-strength =3D <0x1000 0x1800>; + pinctrl-single,bias-pullup =3D <0 0xc000 0 0xc000>; + pinctrl-single,bias-pulldown =3D <0 0xa000 0 0xa000>; + pinctrl-single,input-schmitt =3D <0 0x30>; + pinctrl-single,input-schmitt-enable =3D <0x40 0 0x40 0x40>; + pinctrl-single,low-power-mode =3D <0 0x388>; + }; + + uart0_pins: uart0-pins { + pinctrl-single,pins =3D < + 0x198 6 + 0x19c 6 + >; + pinctrl-single,drive-strength =3D <0x1000 0x1800>; + pinctrl-single,bias-pullup =3D <0 0xc000 0 0xc000>; + pinctrl-single,bias-pulldown =3D <0 0xa000 0 0xa000>; + pinctrl-single,input-schmitt =3D <0 0x30>; + pinctrl-single,input-schmitt-enable =3D <0x40 0 0x40 0x40>; + pinctrl-single,low-power-mode =3D <0 0x388>; + }; + + gpio_keys_pins: gpio-keys-pins { + pinctrl-single,pins =3D < + 0x11c 0 + 0x120 0 + 0x1a4 0 + >; + pinctrl-single,drive-strength =3D <0x1000 0x1800>; + pinctrl-single,bias-pullup =3D <0xc000 0xc000 0 0xc000>; + pinctrl-single,bias-pulldown =3D <0x8000 0xa0000 0x8000 0xa000>; + pinctrl-single,input-schmitt =3D <0 0x30>; + pinctrl-single,input-schmitt-enable =3D <0x40 0 0x40 0x40>; + pinctrl-single,low-power-mode =3D <0 0x388>; + }; + + i2c_muic_pins: i2c-muic-pins { + pinctrl-single,pins =3D < + 0x154 0 + 0x150 0 + >; + pinctrl-single,drive-strength =3D <0x1000 0x1800>; + pinctrl-single,bias-pullup =3D <0 0xc000 0 0xc000>; + pinctrl-single,bias-pulldown =3D <0 0xa000 0 0xa000>; + pinctrl-single,input-schmitt =3D <0 0x30>; + pinctrl-single,input-schmitt-enable =3D <0x40 0 0x40 0x40>; + pinctrl-single,low-power-mode =3D <0x288 0x388>; + }; + + sdh0_pins_0: sdh0-pins-0 { + pinctrl-single,pins =3D < + 0x108 0 + >; + pinctrl-single,drive-strength =3D <0x1000 0x1800>; + pinctrl-single,bias-pullup =3D <0xc000 0xc000 0 0xc000>; + pinctrl-single,bias-pulldown =3D <0x8000 0xa000 0x8000 0xa000>; + pinctrl-single,input-schmitt =3D <0 0x30>; + pinctrl-single,input-schmitt-enable =3D <0x40 0 0x40 0x40>; + pinctrl-single,low-power-mode =3D <0 0x388>; + }; + + sdh0_pins_1: sdh0-pins-1 { + pinctrl-single,pins =3D < + 0x94 0 + 0x98 0 + 0x9c 0 + 0xa0 0 + 0xa4 0 + >; + pinctrl-single,drive-strength =3D <0x800 0x1800>; + pinctrl-single,bias-pullup =3D <0xc000 0xc000 0 0xc000>; + pinctrl-single,bias-pulldown =3D <0x8000 0xa000 0x8000 0xa000>; + pinctrl-single,input-schmitt =3D <0 0x30>; + pinctrl-single,input-schmitt-enable =3D <0x40 0 0x40 0x40>; + pinctrl-single,low-power-mode =3D <0 0x388>; + }; + + sdh0_pins_2: sdh0-pins-2 { + pinctrl-single,pins =3D < + 0xa8 0 + >; + pinctrl-single,drive-strength =3D <0x1000 0x1800>; + pinctrl-single,bias-pullup =3D <0 0xc000 0 0xc000>; + pinctrl-single,bias-pulldown =3D <0 0xa000 0 0xa000>; + pinctrl-single,input-schmitt =3D <0 0x30>; + pinctrl-single,input-schmitt-enable =3D <0x40 0 0x40 0x40>; + pinctrl-single,low-power-mode =3D <0x208 0x388>; + }; +}; + +&uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_pins>; +}; + +&twsi0 { + status =3D "okay"; +}; + +&twsi1 { + status =3D "okay"; +}; + +&twsi2 { + status =3D "okay"; +}; + +&twsi3 { + status =3D "okay"; +}; + +&usb { + extcon =3D <&muic>, <&muic>; +}; + +&sdh2 { + /* Disabled for now because initialization fails with -ETIMEDOUT. */ + status =3D "disabled"; + bus-width =3D <8>; + non-removable; + mmc-ddr-1_8v; +}; + +&sdh0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdh0_pins_0 &sdh0_pins_1 &sdh0_pins_2>; + cd-gpios =3D <&gpio 11 0>; + cd-inverted; + bus-width =3D <4>; + wp-inverted; +}; diff --git a/arch/arm64/boot/dts/marvell/pxa1908.dtsi b/arch/arm64/boot/dts= /marvell/pxa1908.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..cf2b9109688ce560eec8a139725= 1ead68d78a239 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/pxa1908.dtsi @@ -0,0 +1,300 @@ +// SPDX-License-Identifier: GPL-2.0-only +/dts-v1/; + +#include +#include + +/ { + model =3D "Marvell Armada PXA1908"; + compatible =3D "marvell,pxa1908"; + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&gic>; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0 0>; + enable-method =3D "psci"; + }; + + cpu1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0 1>; + enable-method =3D "psci"; + }; + + cpu2: cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0 2>; + enable-method =3D "psci"; + }; + + cpu3: cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0 3>; + enable-method =3D "psci"; + }; + }; + + pmu { + compatible =3D "arm,cortex-a53-pmu"; + interrupts =3D , + , + , + ; + interrupt-affinity =3D <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible =3D "arm,psci-0.2"; + method =3D "smc"; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; + + soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + smmu: iommu@c0010000 { + compatible =3D "arm,mmu-400"; + reg =3D <0 0xc0010000 0 0x10000>; + #global-interrupts =3D <1>; + #iommu-cells =3D <1>; + interrupts =3D , + ; + status =3D "disabled"; + }; + + gic: interrupt-controller@d1df9000 { + compatible =3D "arm,gic-400"; + reg =3D <0 0xd1df9000 0 0x1000>, + <0 0xd1dfa000 0 0x2000>, + /* The subsequent registers are guesses. */ + <0 0xd1dfc000 0 0x2000>, + <0 0xd1dfe000 0 0x2000>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <3>; + }; + + apb@d4000000 { + compatible =3D "simple-bus"; + reg =3D <0 0xd4000000 0 0x200000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0 0xd4000000 0x200000>; + + pdma: dma-controller@0 { + compatible =3D "marvell,pdma-1.0"; + reg =3D <0 0x10000>; + interrupts =3D ; + dma-channels =3D <30>; + #dma-cells =3D <2>; + }; + + twsi1: i2c@10800 { + compatible =3D "mrvl,mmp-twsi"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x10800 0x64>; + interrupts =3D ; + clocks =3D <&apbc PXA1908_CLK_TWSI1>; + mrvl,i2c-fast-mode; + status =3D "disabled"; + }; + + twsi0: i2c@11000 { + compatible =3D "mrvl,mmp-twsi"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x11000 0x64>; + interrupts =3D ; + clocks =3D <&apbc PXA1908_CLK_TWSI0>; + mrvl,i2c-fast-mode; + status =3D "disabled"; + }; + + twsi3: i2c@13800 { + compatible =3D "mrvl,mmp-twsi"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x13800 0x64>; + interrupts =3D ; + clocks =3D <&apbc PXA1908_CLK_TWSI3>; + mrvl,i2c-fast-mode; + status =3D "disabled"; + }; + + apbc: clock-controller@15000 { + compatible =3D "marvell,pxa1908-apbc"; + reg =3D <0x15000 0x1000>; + #clock-cells =3D <1>; + }; + + uart0: serial@17000 { + compatible =3D "mrvl,mmp-uart", "intel,xscale-uart"; + reg =3D <0x17000 0x1000>; + interrupts =3D ; + clocks =3D <&apbc PXA1908_CLK_UART0>; + reg-shift =3D <2>; + }; + + uart1: serial@18000 { + compatible =3D "mrvl,mmp-uart", "intel,xscale-uart"; + reg =3D <0x18000 0x1000>; + interrupts =3D ; + clocks =3D <&apbc PXA1908_CLK_UART1>; + reg-shift =3D <2>; + }; + + gpio: gpio@19000 { + compatible =3D "marvell,mmp-gpio"; + reg =3D <0x19000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + gpio-controller; + #gpio-cells =3D <2>; + clocks =3D <&apbc PXA1908_CLK_GPIO>; + interrupts =3D ; + interrupt-names =3D "gpio_mux"; + interrupt-controller; + #interrupt-cells =3D <2>; + ranges =3D <0 0x19000 0x800>; + + gpio@0 { + reg =3D <0x0 0x4>; + }; + + gpio@4 { + reg =3D <0x4 0x4>; + }; + + gpio@8 { + reg =3D <0x8 0x4>; + }; + + gpio@100 { + reg =3D <0x100 0x4>; + }; + }; + + pmx: pinmux@1e000 { + compatible =3D "marvell,pxa1908-padconf", "pinconf-single"; + reg =3D <0x1e000 0x330>; + + #pinctrl-cells =3D <1>; + pinctrl-single,register-width =3D <32>; + pinctrl-single,function-mask =3D <7>; + + range: gpio-range { + #pinctrl-single,gpio-range-cells =3D <3>; + }; + }; + + uart2: serial@36000 { + compatible =3D "mrvl,mmp-uart", "intel,xscale-uart"; + reg =3D <0x36000 0x1000>; + interrupts =3D ; + clocks =3D <&apbcp PXA1908_CLK_UART2>; + reg-shift =3D <2>; + }; + + twsi2: i2c@37000 { + compatible =3D "mrvl,mmp-twsi"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x37000 0x64>; + interrupts =3D ; + clocks =3D <&apbcp PXA1908_CLK_TWSI2>; + mrvl,i2c-fast-mode; + status =3D "disabled"; + }; + + apbcp: clock-controller@3b000 { + compatible =3D "marvell,pxa1908-apbcp"; + reg =3D <0x3b000 0x1000>; + #clock-cells =3D <1>; + }; + + mpmu: clock-controller@50000 { + compatible =3D "marvell,pxa1908-mpmu"; + reg =3D <0x50000 0x1000>; + #clock-cells =3D <1>; + }; + }; + + axi@d4200000 { + compatible =3D "simple-bus"; + reg =3D <0 0xd4200000 0 0x200000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0 0xd4200000 0x200000>; + + usbphy: phy@7000 { + compatible =3D "marvell,pxa1928-usb-phy"; + reg =3D <0x7000 0x200>; + clocks =3D <&apmu PXA1908_CLK_USB>; + #phy-cells =3D <0>; + }; + + usb: usb@8000 { + compatible =3D "chipidea,usb2"; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241001-pxa1908-lkml-v13-12-6b9a7f64f9ae@skole.hr> References: <20241001-pxa1908-lkml-v13-0-6b9a7f64f9ae@skole.hr> In-Reply-To: <20241001-pxa1908-lkml-v13-0-6b9a7f64f9ae@skole.hr> To: Michael Turquette , Stephen Boyd , Linus Walleij , Rob Herring , Conor Dooley , Tony Lindgren , Haojian Zhuang , =?utf-8?q?Duje_Mihanovi=C4=87?= , Lubomir Rintel , Catalin Marinas , Will Deacon , Rob Herring , Krzysztof Kozlowski Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Karel Balej , David Wronek , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=962; i=duje.mihanovic@skole.hr; s=20240706; h=from:subject:message-id; bh=l+xZKLnv6u5DO/ZJ2tEjb9sysdQzHXNYhZXbgNuCkVo=; b=owGbwMvMwCW21nBykGv/WmbG02pJDGl/OCdn5WVtsnfIcDh19SmvJ0fQIhO7lb5zHTLmLEmo/ 37PqGJuRykLgxgXg6yYIkvuf8drvJ9Ftm7PXmYAM4eVCWQIAxenAExk521Ghu545c6GVSyPEufV PWHQUlKWl95rdX+f8T7L0MnyVUcKuBkZPi1b0XJ+0507F29M48+eK/7QpXWp3nntN7pnn27c2zO xhBEA X-Developer-Key: i=duje.mihanovic@skole.hr; a=openpgp; fpr=6DFF41D60DF314B5B76BA630AD319352458FAD03 X-Endpoint-Received: by B4 Relay for duje.mihanovic@skole.hr/20240706 with auth_id=191 X-Original-From: =?utf-8?q?Duje_Mihanovi=C4=87?= Reply-To: duje.mihanovic@skole.hr From: Duje Mihanovi=C4=87 Add myself as the maintainer for Marvell PXA1908 SoC support. Signed-off-by: Duje Mihanovi=C4=87 --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index c27f3190737f8b85779bde5489639c8b899f4fd8..8d50cb7457924e3290810eaf7d3= c4b145d988ede 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2593,6 +2593,15 @@ F: drivers/irqchip/irq-mvebu-* F: drivers/pinctrl/mvebu/ F: drivers/rtc/rtc-armada38x.c =20 +ARM/Marvell PXA1908 SOC support +M: Duje Mihanovi=C4=87 +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +T: git https://gitlab.com/LegoLivesMatter/linux +F: arch/arm64/boot/dts/marvell/pxa1908* +F: drivers/clk/mmp/clk-pxa1908*.c +F: include/dt-bindings/clock/marvell,pxa1908.h + ARM/Mediatek RTC DRIVER M: Eddie Huang M: Sean Wang --=20 2.46.2