From nobody Thu Nov 28 16:37:34 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68D1E1BCA07; Tue, 1 Oct 2024 06:42:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727764925; cv=none; b=UNXgVB557WC47Sf9ZtrEkJwrOB15LqlwKoIyIIZ324Q8oSdrx2R7bsUXZUbIOSKRNJI91aFA1Elc0OIZhYeGcasHqcLGLA1Ljr7uJ24S/XoZyIXL8WjUxQgNgA5oBhdAZ/I293uM3VSaXUcQPpJHUAXWk6byhJMXRYbqZdaUqNM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727764925; c=relaxed/simple; bh=eHhi3IE5QYIljEIZfCEN/SVnk/FjMdvW+31klwdSPOA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=n58AvE0NHa6vqMCwGQI/TTVFZbOione1LpDNOmBv22mMYdKRLbMbI0EPGQzLJPruGsvNcYG0zV6VNDWjJ3qwCuaKPaimOgNOrYk6856GU44lYhB+QOLr2DEwr4Fs4ttpqq+EE3f/jOgjUJ03RRlMVhAjtl/jxqgqiKVV+Huo0L4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=J3hqxMrC; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="J3hqxMrC" Received: by smtp.kernel.org (Postfix) with ESMTPS id DBEA6C4CEDB; Tue, 1 Oct 2024 06:42:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1727764924; bh=eHhi3IE5QYIljEIZfCEN/SVnk/FjMdvW+31klwdSPOA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=J3hqxMrCvJxWVepJQlPHo2PHHZQ4EeFWui20tkpxEkrd5IA45R8yRYZLJMDGN738R GUzmf+EjcsZEUuoEmKGi1MDoiBzIHhbxoUKnyi2qnRL8eEi0ald8K90CSD2Mv8YXs8 VE2wCS9otmwQs9WlG2octRcE2MUrk4ILURn7wHlHpwW8aPpQt/dHKRlYsWBmg39oOa OQ4EOHR5wy7LTAuJA1iR2FsfDKqnixBuPo63A/QyPb0VhxqHGZfLERpALSt18NwVSN aSGfSj1GXU9U+7hbeZ00vf7uGNl0/Dgt/gdtHFIPZSxA6095gnzDG6WvByTfIZYJiA kneJlJ1uVSIng== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3868CEB2E8; Tue, 1 Oct 2024 06:42:04 +0000 (UTC) From: Mahadevan via B4 Relay Date: Tue, 01 Oct 2024 12:11:40 +0530 Subject: [PATCH v3 5/5] arm64: dts: qcom: sa8775p: add display dt nodes for MDSS0 and DPU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241001-patchv3_1-v3-5-d23284f45977@quicinc.com> References: <20241001-patchv3_1-v3-0-d23284f45977@quicinc.com> In-Reply-To: <20241001-patchv3_1-v3-0-d23284f45977@quicinc.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mahadevan , Bjorn Andersson , Konrad Dybcio Cc: Kalyan Thota , Jayaprakash Madisetty , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727764922; l=3736; i=quic_mahap@quicinc.com; s=20241001; h=from:subject:message-id; bh=mwU+T+g7aZfnj3h6yUCl49ZVraCw0HZEXDEFdRAhnjw=; b=XcwdYY/DjaO3MExCm5Duwt4n6hGSj6aUbW5VG4zX8y7dIQpI+o6mNcrdOWmbCWFhrz/64xzR9 /qDLJy8aXk4DndR0Y+SM5Dyy1wchEKngN/LEnenQZ4LEPHsXx9oyYyV X-Developer-Key: i=quic_mahap@quicinc.com; a=ed25519; pk=Xc9CA438o9mZKp4uZ8vZMclALnJ8XtlKn/n3Y42mMBI= X-Endpoint-Received: by B4 Relay for quic_mahap@quicinc.com/20241001 with auth_id=236 X-Original-From: Mahadevan Reply-To: quic_mahap@quicinc.com From: Mahadevan Add devicetree changes to enable MDSS0 display-subsystem its display-controller(DPU) for Qualcomm SA8775P platform. Signed-off-by: Mahadevan Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 89 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 89 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qc= om/sa8775p.dtsi index 8fd68a8aa916e6595134b470f87b18b509178a51..66bd5e1c82a426f93097dee63a6= 9c03527f04b3e 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -2937,6 +2938,94 @@ camcc: clock-controller@ade0000 { #power-domain-cells =3D <1>; }; =20 + mdss0: display-subsystem@ae00000 { + compatible =3D "qcom,sa8775p-mdss"; + reg =3D <0x0 0x0ae00000 0x0 0x1000>; + reg-names =3D "mdss"; + + /* same path used twice */ + interconnects =3D <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "mdp0-mem", + "mdp1-mem", + "cpu-cfg"; + + resets =3D <&dispcc0 MDSS_DISP_CC_MDSS_CORE_BCR>; + + power-domains =3D <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>; + + clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + + iommus =3D <&apps_smmu 0x1000 0x402>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + mdss0_mdp: display-controller@ae01000 { + compatible =3D "qcom,sa8775p-dpu"; + reg =3D <0x0 0x0ae01000 0x0 0x8f000>, + <0x0 0x0aeb0000 0x0 0x2008>; + reg-names =3D "mdp", "vbif"; + + clocks =3D <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdss0_mdp_opp_table>; + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + interrupt-parent =3D <&mdss0>; + interrupts =3D <0>; + + mdss0_mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-375000000 { + opp-hz =3D /bits/ 64 <375000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + + opp-575000000 { + opp-hz =3D /bits/ 64 <575000000>; + required-opps =3D <&rpmhpd_opp_turbo>; + }; + + opp-650000000 { + opp-hz =3D /bits/ 64 <650000000>; + required-opps =3D <&rpmhpd_opp_turbo_l1>; + }; + }; + }; + }; + dispcc0: clock-controller@af00000 { compatible =3D "qcom,sa8775p-dispcc0"; reg =3D <0x0 0x0af00000 0x0 0x20000>; --=20 2.34.1