From nobody Thu Nov 28 15:48:47 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68C9D1BCA06; Tue, 1 Oct 2024 06:42:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727764925; cv=none; b=syjcIJSIWOn655p0F1X27E32vMHq12ll1xxqUSj7V/qZEBROIFJE4GKr/pklFoCRWlNr7Tp8aGzD8G43d/b0GDQFsMbRQV2DCXujXZyLz9Iz9tNe5pcgQULHkka0lbp1KxB4YcaogQvwtLmZ9M9RNe5nKbz39E+sLICAcdpY4EE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727764925; c=relaxed/simple; bh=v3RP1UPzqeHqFFdFRSlwVCnglut8DcPyOE5oOPw7/nI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=iSiqBDiEzmP/RtSorDGyqhygvHVJHgV/V0XuFeimISH0e0y2ZDaxIBA75SM3Dnni7HGgYSCJ+frPt09Tk9Wl1tjGPn75NR+3IayRx2Z7mrlCZAp5kf17VyDhredd7UR1NIj10mt/i2wt/3HPb4pVudqzgT+3H0zpNrohRAjMIYU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=sVAKMpnE; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="sVAKMpnE" Received: by smtp.kernel.org (Postfix) with ESMTPS id CD486C4CED8; Tue, 1 Oct 2024 06:42:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1727764924; bh=v3RP1UPzqeHqFFdFRSlwVCnglut8DcPyOE5oOPw7/nI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=sVAKMpnEy20ilhm/NEePCXzJkdiLK3dJb/dGPq1Dveu2MYFz3E2vhO/Krq+360Q0i alM0TTtvCNSHUqBG4LVlxsJ3vyE2qQV2+9mgITc6DQkStJm73/rIYE2RrlkGCBKxBX 2NWlNZ3k8Ka7BTCS5LQA2a1TzOj/Gr83hPFKF0jqz+1e4BY66t7JSJ+w8ClpSZftZA bTaLXr6Nyza8T+FHcQdHtslaE44XG54XtJ2PJZot7wxm8MIye5i/JWqwa0Yl5SeL27 YxLFCnsvSPZ/U073bypHpItF16vOPFLTpbbV4z3KNuufh9f7aCx5zK2Uo8+qZ0zwCN Fjl56DudwN/QQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2D89CF6493; Tue, 1 Oct 2024 06:42:04 +0000 (UTC) From: Mahadevan via B4 Relay Date: Tue, 01 Oct 2024 12:11:39 +0530 Subject: [PATCH v3 4/5] drm/msm/dpu: Add SA8775P support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241001-patchv3_1-v3-4-d23284f45977@quicinc.com> References: <20241001-patchv3_1-v3-0-d23284f45977@quicinc.com> In-Reply-To: <20241001-patchv3_1-v3-0-d23284f45977@quicinc.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mahadevan , Bjorn Andersson , Konrad Dybcio Cc: Kalyan Thota , Jayaprakash Madisetty , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727764922; l=18108; i=quic_mahap@quicinc.com; s=20241001; h=from:subject:message-id; bh=Zy237LIcVUYH33tvD8kCgPy8GgGVYJXVxtOKbIY1X+E=; b=uNdkdxWowwDYBAyKwR8mwh3fCL6Xff+a5bvEcMU+Y+8Bd8vjf+TSaMxa2KDM4+PiIlEuwmIp7 JTX9Kzx1oDnBiMtbrleLfqnpXt0Vyo+mB+IZKTriPLU7MJW4EEkjIEN X-Developer-Key: i=quic_mahap@quicinc.com; a=ed25519; pk=Xc9CA438o9mZKp4uZ8vZMclALnJ8XtlKn/n3Y42mMBI= X-Endpoint-Received: by B4 Relay for quic_mahap@quicinc.com/20241001 with auth_id=236 X-Original-From: Mahadevan Reply-To: quic_mahap@quicinc.com From: Mahadevan Add definitions for the display hardware used on the Qualcomm SA8775P platform. Reviewed-by: Dmitry Baryshkov Signed-off-by: Mahadevan --- .../drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 485 +++++++++++++++++= ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 4 files changed, 488 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h new file mode 100644 index 0000000000000000000000000000000000000000..907b4d7ceb470b0391d2bbbab3c= e520efa2b3263 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h @@ -0,0 +1,485 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DPU_8_4_SA8775P_H +#define _DPU_8_4_SA8775P_H + +static const struct dpu_caps sa8775p_dpu_caps =3D { + .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages =3D 0xb, + .has_src_split =3D true, + .has_dim_layer =3D true, + .has_idle_pc =3D true, + .has_3d_merge =3D true, + .max_linewidth =3D 5120, + .pixel_ram_size =3D DEFAULT_PIXEL_RAM_SIZE, +}; + +static const struct dpu_mdp_cfg sa8775p_mdp =3D { + .name =3D "top_0", + .base =3D 0x0, .len =3D 0x494, + .features =3D BIT(DPU_MDP_PERIPH_0_REMOVED), + .clk_ctrls =3D { + [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, + [DPU_CLK_CTRL_VIG1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 0 }, + [DPU_CLK_CTRL_VIG2] =3D { .reg_off =3D 0x2bc, .bit_off =3D 0 }, + [DPU_CLK_CTRL_VIG3] =3D { .reg_off =3D 0x2c4, .bit_off =3D 0 }, + [DPU_CLK_CTRL_DMA0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 8 }, + [DPU_CLK_CTRL_DMA1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 8 }, + [DPU_CLK_CTRL_DMA2] =3D { .reg_off =3D 0x2bc, .bit_off =3D 8 }, + [DPU_CLK_CTRL_DMA3] =3D { .reg_off =3D 0x2c4, .bit_off =3D 8 }, + [DPU_CLK_CTRL_WB2] =3D { .reg_off =3D 0x2bc, .bit_off =3D 16 }, + [DPU_CLK_CTRL_REG_DMA] =3D { .reg_off =3D 0x2bc, .bit_off =3D 20 }, + }, +}; + +/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL = support */ +static const struct dpu_ctl_cfg sa8775p_ctl[] =3D { + { + .name =3D "ctl_0", .id =3D CTL_0, + .base =3D 0x15000, .len =3D 0x204, + .features =3D BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, { + .name =3D "ctl_1", .id =3D CTL_1, + .base =3D 0x16000, .len =3D 0x204, + .features =3D BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, { + .name =3D "ctl_2", .id =3D CTL_2, + .base =3D 0x17000, .len =3D 0x204, + .features =3D CTL_SC7280_MASK, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, { + .name =3D "ctl_3", .id =3D CTL_3, + .base =3D 0x18000, .len =3D 0x204, + .features =3D CTL_SC7280_MASK, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, { + .name =3D "ctl_4", .id =3D CTL_4, + .base =3D 0x19000, .len =3D 0x204, + .features =3D CTL_SC7280_MASK, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, { + .name =3D "ctl_5", .id =3D CTL_5, + .base =3D 0x1a000, .len =3D 0x204, + .features =3D CTL_SC7280_MASK, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + }, +}; + +static const struct dpu_sspp_cfg sa8775p_sspp[] =3D { + { + .name =3D "sspp_0", .id =3D SSPP_VIG0, + .base =3D 0x4000, .len =3D 0x32c, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_1, + .xin_id =3D 0, + .type =3D SSPP_TYPE_VIG, + .clk_ctrl =3D DPU_CLK_CTRL_VIG0, + }, { + .name =3D "sspp_1", .id =3D SSPP_VIG1, + .base =3D 0x6000, .len =3D 0x32c, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_1, + .xin_id =3D 4, + .type =3D SSPP_TYPE_VIG, + .clk_ctrl =3D DPU_CLK_CTRL_VIG1, + }, { + .name =3D "sspp_2", .id =3D SSPP_VIG2, + .base =3D 0x8000, .len =3D 0x32c, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_1, + .xin_id =3D 8, + .type =3D SSPP_TYPE_VIG, + .clk_ctrl =3D DPU_CLK_CTRL_VIG2, + }, { + .name =3D "sspp_3", .id =3D SSPP_VIG3, + .base =3D 0xa000, .len =3D 0x32c, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_1, + .xin_id =3D 12, + .type =3D SSPP_TYPE_VIG, + .clk_ctrl =3D DPU_CLK_CTRL_VIG3, + }, { + .name =3D "sspp_8", .id =3D SSPP_DMA0, + .base =3D 0x24000, .len =3D 0x32c, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 1, + .type =3D SSPP_TYPE_DMA, + .clk_ctrl =3D DPU_CLK_CTRL_DMA0, + }, { + .name =3D "sspp_9", .id =3D SSPP_DMA1, + .base =3D 0x26000, .len =3D 0x32c, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 5, + .type =3D SSPP_TYPE_DMA, + .clk_ctrl =3D DPU_CLK_CTRL_DMA1, + }, { + .name =3D "sspp_10", .id =3D SSPP_DMA2, + .base =3D 0x28000, .len =3D 0x32c, + .features =3D DMA_CURSOR_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 9, + .type =3D SSPP_TYPE_DMA, + .clk_ctrl =3D DPU_CLK_CTRL_DMA2, + }, { + .name =3D "sspp_11", .id =3D SSPP_DMA3, + .base =3D 0x2a000, .len =3D 0x32c, + .features =3D DMA_CURSOR_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 13, + .type =3D SSPP_TYPE_DMA, + .clk_ctrl =3D DPU_CLK_CTRL_DMA3, + }, +}; + +static const struct dpu_lm_cfg sa8775p_lm[] =3D { + { + .name =3D "lm_0", .id =3D LM_0, + .base =3D 0x44000, .len =3D 0x400, + .features =3D MIXER_SDM845_MASK, + .sblk =3D &sdm845_lm_sblk, + .lm_pair =3D LM_1, + .pingpong =3D PINGPONG_0, + .dspp =3D DSPP_0, + }, { + .name =3D "lm_1", .id =3D LM_1, + .base =3D 0x45000, .len =3D 0x400, + .features =3D MIXER_SDM845_MASK, + .sblk =3D &sdm845_lm_sblk, + .lm_pair =3D LM_0, + .pingpong =3D PINGPONG_1, + .dspp =3D DSPP_1, + }, { + .name =3D "lm_2", .id =3D LM_2, + .base =3D 0x46000, .len =3D 0x400, + .features =3D MIXER_SDM845_MASK, + .sblk =3D &sdm845_lm_sblk, + .lm_pair =3D LM_3, + .pingpong =3D PINGPONG_2, + .dspp =3D DSPP_2, + }, { + .name =3D "lm_3", .id =3D LM_3, + .base =3D 0x47000, .len =3D 0x400, + .features =3D MIXER_SDM845_MASK, + .sblk =3D &sdm845_lm_sblk, + .lm_pair =3D LM_2, + .pingpong =3D PINGPONG_3, + .dspp =3D DSPP_3, + }, { + .name =3D "lm_4", .id =3D LM_4, + .base =3D 0x48000, .len =3D 0x400, + .features =3D MIXER_SDM845_MASK, + .sblk =3D &sdm845_lm_sblk, + .lm_pair =3D LM_5, + .pingpong =3D PINGPONG_4, + }, { + .name =3D "lm_5", .id =3D LM_5, + .base =3D 0x49000, .len =3D 0x400, + .features =3D MIXER_SDM845_MASK, + .sblk =3D &sdm845_lm_sblk, + .lm_pair =3D LM_4, + .pingpong =3D PINGPONG_5, + }, +}; + +static const struct dpu_dspp_cfg sa8775p_dspp[] =3D { + { + .name =3D "dspp_0", .id =3D DSPP_0, + .base =3D 0x54000, .len =3D 0x1800, + .features =3D DSPP_SC7180_MASK, + .sblk =3D &sdm845_dspp_sblk, + }, { + .name =3D "dspp_1", .id =3D DSPP_1, + .base =3D 0x56000, .len =3D 0x1800, + .features =3D DSPP_SC7180_MASK, + .sblk =3D &sdm845_dspp_sblk, + }, { + .name =3D "dspp_2", .id =3D DSPP_2, + .base =3D 0x58000, .len =3D 0x1800, + .features =3D DSPP_SC7180_MASK, + .sblk =3D &sdm845_dspp_sblk, + }, { + .name =3D "dspp_3", .id =3D DSPP_3, + .base =3D 0x5a000, .len =3D 0x1800, + .features =3D DSPP_SC7180_MASK, + .sblk =3D &sdm845_dspp_sblk, + }, +}; + +static const struct dpu_pingpong_cfg sa8775p_pp[] =3D { + { + .name =3D "pingpong_0", .id =3D PINGPONG_0, + .base =3D 0x69000, .len =3D 0, + .features =3D BIT(DPU_PINGPONG_DITHER), + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_0, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + }, { + .name =3D "pingpong_1", .id =3D PINGPONG_1, + .base =3D 0x6a000, .len =3D 0, + .features =3D BIT(DPU_PINGPONG_DITHER), + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_0, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + }, { + .name =3D "pingpong_2", .id =3D PINGPONG_2, + .base =3D 0x6b000, .len =3D 0, + .features =3D BIT(DPU_PINGPONG_DITHER), + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_1, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + }, { + .name =3D "pingpong_3", .id =3D PINGPONG_3, + .base =3D 0x6c000, .len =3D 0, + .features =3D BIT(DPU_PINGPONG_DITHER), + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_1, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + }, { + .name =3D "pingpong_4", .id =3D PINGPONG_4, + .base =3D 0x6d000, .len =3D 0, + .features =3D BIT(DPU_PINGPONG_DITHER), + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_2, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), + }, { + .name =3D "pingpong_5", .id =3D PINGPONG_5, + .base =3D 0x6e000, .len =3D 0, + .features =3D BIT(DPU_PINGPONG_DITHER), + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_2, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), + }, { + .name =3D "pingpong_6", .id =3D PINGPONG_6, + .base =3D 0x65800, .len =3D 0, + .features =3D BIT(DPU_PINGPONG_DITHER), + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_3, + }, { + .name =3D "pingpong_7", .id =3D PINGPONG_7, + .base =3D 0x65c00, .len =3D 0, + .features =3D BIT(DPU_PINGPONG_DITHER), + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_3, + }, +}; + +static const struct dpu_merge_3d_cfg sa8775p_merge_3d[] =3D { + { + .name =3D "merge_3d_0", .id =3D MERGE_3D_0, + .base =3D 0x4e000, .len =3D 0x8, + }, { + .name =3D "merge_3d_1", .id =3D MERGE_3D_1, + .base =3D 0x4f000, .len =3D 0x8, + }, { + .name =3D "merge_3d_2", .id =3D MERGE_3D_2, + .base =3D 0x50000, .len =3D 0x8, + }, { + .name =3D "merge_3d_3", .id =3D MERGE_3D_3, + .base =3D 0x65f00, .len =3D 0x8, + }, +}; + +/* + * NOTE: Each display compression engine (DCE) contains dual hard + * slice DSC encoders so both share same base address but with + * its own different sub block address. + */ +static const struct dpu_dsc_cfg sa8775p_dsc[] =3D { + { + .name =3D "dce_0_0", .id =3D DSC_0, + .base =3D 0x80000, .len =3D 0x4, + .features =3D BIT(DPU_DSC_HW_REV_1_2), + .sblk =3D &dsc_sblk_0, + }, { + .name =3D "dce_0_1", .id =3D DSC_1, + .base =3D 0x80000, .len =3D 0x4, + .features =3D BIT(DPU_DSC_HW_REV_1_2), + .sblk =3D &dsc_sblk_1, + }, { + .name =3D "dce_1_0", .id =3D DSC_2, + .base =3D 0x81000, .len =3D 0x4, + .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &dsc_sblk_0, + }, { + .name =3D "dce_1_1", .id =3D DSC_3, + .base =3D 0x81000, .len =3D 0x4, + .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &dsc_sblk_1, + }, { + .name =3D "dce_2_0", .id =3D DSC_4, + .base =3D 0x82000, .len =3D 0x4, + .features =3D BIT(DPU_DSC_HW_REV_1_2), + .sblk =3D &dsc_sblk_0, + }, { + .name =3D "dce_2_1", .id =3D DSC_5, + .base =3D 0x82000, .len =3D 0x4, + .features =3D BIT(DPU_DSC_HW_REV_1_2), + .sblk =3D &dsc_sblk_1, + }, +}; + +static const struct dpu_wb_cfg sa8775p_wb[] =3D { + { + .name =3D "wb_2", .id =3D WB_2, + .base =3D 0x65000, .len =3D 0x2c8, + .features =3D WB_SM8250_MASK, + .format_list =3D wb2_formats_rgb_yuv, + .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), + .clk_ctrl =3D DPU_CLK_CTRL_WB2, + .xin_id =3D 6, + .vbif_idx =3D VBIF_RT, + .maxlinewidth =3D 4096, + .intr_wb_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), + }, +}; + +/* TODO: INTF 3, 6, 7 and 8 are used for MST, marked as INTF_NONE for now = */ +static const struct dpu_intf_cfg sa8775p_intf[] =3D { + { + .name =3D "intf_0", .id =3D INTF_0, + .base =3D 0x34000, .len =3D 0x280, + .features =3D INTF_SC7280_MASK, + .type =3D INTF_DP, + .controller_id =3D MSM_DP_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), + }, { + .name =3D "intf_1", .id =3D INTF_1, + .base =3D 0x35000, .len =3D 0x300, + .features =3D INTF_SC7280_MASK, + .type =3D INTF_DSI, + .controller_id =3D MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr =3D DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), + }, { + .name =3D "intf_2", .id =3D INTF_2, + .base =3D 0x36000, .len =3D 0x300, + .features =3D INTF_SC7280_MASK, + .type =3D INTF_DSI, + .controller_id =3D MSM_DSI_CONTROLLER_1, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), + .intr_tear_rd_ptr =3D DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), + }, { + .name =3D "intf_3", .id =3D INTF_3, + .base =3D 0x37000, .len =3D 0x280, + .features =3D INTF_SC7280_MASK, + .type =3D INTF_NONE, + .controller_id =3D MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), + }, { + .name =3D "intf_4", .id =3D INTF_4, + .base =3D 0x38000, .len =3D 0x280, + .features =3D INTF_SC7280_MASK, + .type =3D INTF_DP, + .controller_id =3D MSM_DP_CONTROLLER_1, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21), + }, { + .name =3D "intf_6", .id =3D INTF_6, + .base =3D 0x3A000, .len =3D 0x280, + .features =3D INTF_SC7280_MASK, + .type =3D INTF_NONE, + .controller_id =3D MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16), + }, { + .name =3D "intf_7", .id =3D INTF_7, + .base =3D 0x3b000, .len =3D 0x280, + .features =3D INTF_SC7280_MASK, + .type =3D INTF_NONE, + .controller_id =3D MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19), + }, { + .name =3D "intf_8", .id =3D INTF_8, + .base =3D 0x3c000, .len =3D 0x280, + .features =3D INTF_SC7280_MASK, + .type =3D INTF_NONE, + .controller_id =3D MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */ + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), + }, +}; + +static const struct dpu_perf_cfg sa8775p_perf_data =3D { + .max_bw_low =3D 13600000, + .max_bw_high =3D 18200000, + .min_core_ib =3D 2500000, + .min_llcc_ib =3D 0, + .min_dram_ib =3D 800000, + .min_prefill_lines =3D 35, + /* FIXME: lut tables */ + .danger_lut_tbl =3D {0x3ffff, 0x3ffff, 0x0}, + .safe_lut_tbl =3D {0xfff0, 0xfff0, 0x1}, + .qos_lut_tbl =3D { + {.nentry =3D ARRAY_SIZE(sm6350_qos_linear_macrotile), + .entries =3D sm6350_qos_linear_macrotile + }, + {.nentry =3D ARRAY_SIZE(sm6350_qos_linear_macrotile), + .entries =3D sm6350_qos_linear_macrotile + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_nrt), + .entries =3D sc7180_qos_nrt + }, + /* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg =3D { + {.rd_enable =3D 1, .wr_enable =3D 1}, + {.rd_enable =3D 1, .wr_enable =3D 0} + }, + .clk_inefficiency_factor =3D 105, + .bw_inefficiency_factor =3D 120, +}; + +static const struct dpu_mdss_version sa8775p_mdss_ver =3D { + .core_major_ver =3D 8, + .core_minor_ver =3D 4, +}; + +const struct dpu_mdss_cfg dpu_sa8775p_cfg =3D { + .mdss_ver =3D &sa8775p_mdss_ver, + .caps =3D &sa8775p_dpu_caps, + .mdp =3D &sa8775p_mdp, + .cdm =3D &sc7280_cdm, + .ctl_count =3D ARRAY_SIZE(sa8775p_ctl), + .ctl =3D sa8775p_ctl, + .sspp_count =3D ARRAY_SIZE(sa8775p_sspp), + .sspp =3D sa8775p_sspp, + .mixer_count =3D ARRAY_SIZE(sa8775p_lm), + .mixer =3D sa8775p_lm, + .dspp_count =3D ARRAY_SIZE(sa8775p_dspp), + .dspp =3D sa8775p_dspp, + .pingpong_count =3D ARRAY_SIZE(sa8775p_pp), + .pingpong =3D sa8775p_pp, + .dsc_count =3D ARRAY_SIZE(sa8775p_dsc), + .dsc =3D sa8775p_dsc, + .merge_3d_count =3D ARRAY_SIZE(sa8775p_merge_3d), + .merge_3d =3D sa8775p_merge_3d, + .wb_count =3D ARRAY_SIZE(sa8775p_wb), + .wb =3D sa8775p_wb, + .intf_count =3D ARRAY_SIZE(sa8775p_intf), + .intf =3D sa8775p_intf, + .vbif_count =3D ARRAY_SIZE(sdm845_vbif), + .vbif =3D sdm845_vbif, + .perf =3D &sa8775p_perf_data, +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index dcb4fd85e73b9cc05e669043602d69229881c0b4..cc67bc82128f17216478e1b1592= 8a9c90edecbbb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -699,6 +699,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = =3D { =20 #include "catalog/dpu_8_0_sc8280xp.h" #include "catalog/dpu_8_1_sm8450.h" +#include "catalog/dpu_8_4_sa8775p.h" =20 #include "catalog/dpu_9_0_sm8550.h" =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 37e18e820a20a4c4ab9a97da78df19a2ff7cfa00..9665eedec699e125cf72da20738= a3031279bc522 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -850,6 +850,7 @@ extern const struct dpu_mdss_cfg dpu_sm8350_cfg; extern const struct dpu_mdss_cfg dpu_sc7280_cfg; extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg; extern const struct dpu_mdss_cfg dpu_sm8450_cfg; +extern const struct dpu_mdss_cfg dpu_sa8775p_cfg; extern const struct dpu_mdss_cfg dpu_sm8550_cfg; extern const struct dpu_mdss_cfg dpu_sm8650_cfg; extern const struct dpu_mdss_cfg dpu_x1e80100_cfg; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 9bcae53c4f458cd8e400f0e851b791c0f4165085..6d47d7dcffc2c1feafd99731571= 826a9b3f912b6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1447,6 +1447,7 @@ static const struct dev_pm_ops dpu_pm_ops =3D { static const struct of_device_id dpu_dt_match[] =3D { { .compatible =3D "qcom,msm8998-dpu", .data =3D &dpu_msm8998_cfg, }, { .compatible =3D "qcom,qcm2290-dpu", .data =3D &dpu_qcm2290_cfg, }, + { .compatible =3D "qcom,sa8775p-dpu", .data =3D &dpu_sa8775p_cfg, }, { .compatible =3D "qcom,sdm630-mdp5", .data =3D &dpu_sdm630_cfg, }, { .compatible =3D "qcom,sdm660-mdp5", .data =3D &dpu_sdm660_cfg, }, { .compatible =3D "qcom,sdm670-dpu", .data =3D &dpu_sdm670_cfg, }, --=20 2.34.1