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[83.233.6.197]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5389fd53a02sm1549026e87.31.2024.10.01.03.42.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Oct 2024 03:42:58 -0700 (PDT) From: Marcus Folkesson Date: Tue, 01 Oct 2024 12:42:26 +0200 Subject: [PATCH 1/2] mtd: nand: davinci: add support for on-die ECC engine type Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241001-ondie-v1-1-a3daae15c89d@gmail.com> References: <20241001-ondie-v1-0-a3daae15c89d@gmail.com> In-Reply-To: <20241001-ondie-v1-0-a3daae15c89d@gmail.com> To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Marcus Folkesson X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1761; i=marcus.folkesson@gmail.com; h=from:subject:message-id; bh=PDm1f5NEBuhwxeXGvwzqxiOMHTZXe7TWbR431qOgkS4=; b=owEBbQKS/ZANAwAIAYiATm9ZXVIyAcsmYgBm+9Ih92PxVphriOcHjQalCKMkkaHpNrUhRbjz4 cPS9+Z8r12JAjMEAAEIAB0WIQQFUaLotmy1TWTBLGWIgE5vWV1SMgUCZvvSIQAKCRCIgE5vWV1S MpvtD/96jhTVsSN+ptMU+Evlwhv4dTAoF+mcghcW50wrwJYXrKw6dk7YYGRIJJ2FuoSfzJh+umA bpomSUCLh9GjLDlFKY2iC77wbW04fuuib3Gwcx8Tvyz+zqDxDRwjbEBZ9XM6NJUPprT61m0yJYX geuuwzG9yAL0GCMKW3IQD8f/HXEWkV96V60dFrf/hqYVuhsmh7v3juoy0m2oRjE67ButuD3eB5G U8gV19UImOA6G0WubUc3uLHC4ormjbYV7GPP6uUJ/3OEtqynTODYZiy/rPxHU7/gLStdMfG0el7 zQME1WtkXJMcGlcdEw1gGpGYG22vIBYiJeW4jkejWPm2KnBCRQuoZrtq1y77xyDfj0S4bx5DWsF U23nq6A6oE+v9lQNCxeUX+XKfkd1y/zkkrdBbLfvkgfpu5mwtZ5SRqgayZocYv/sz3iUd1TWsts IWPGTqhpr9bbjiAIIytn9hI6qU4bbaATOs1TVuMSwlPDbfYxSv2IueSfuNOohuDmqCWVaYLYDD5 FAAxuwdrS14E5dBDD+PNHsJnXv5ZszHKmpnJZO4UIPVnSpoH2G2f/whmMNkITwGwNxOoIMmHLP3 nenkxKdIrntuUldfB3QRADQvvXenEHN7FUD+3jo5rWgSdv7AKwXxQu58N2TNEQIUd4kUY/iKKX0 M3stbVMlRmcfc1w== X-Developer-Key: i=marcus.folkesson@gmail.com; a=openpgp; fpr=AB91D46C7E0F6E6FB2AB640EC0FE25D598F6C127 Some chips, e.g. Micron MT29F1G08ABBFAH4, has a mandatory on-die ECC. Add "on-die" as ECC engine type in order to be compatible with those. Signed-off-by: Marcus Folkesson --- drivers/mtd/nand/raw/davinci_nand.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/dav= inci_nand.c index 392678143a36b20b42c1827eee8203dc2e41889a..79e768d337ae12f6e8d7f21f1ac= d4e259f4f3020 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -66,6 +66,7 @@ struct davinci_nand_pdata { =20 /* none =3D=3D NAND_ECC_ENGINE_TYPE_NONE (strongly *not* advised!!) * soft =3D=3D NAND_ECC_ENGINE_TYPE_SOFT + * on-die =3D=3D NAND_ECC_ENGINE_TYPE_ON_DIE * else =3D=3D NAND_ECC_ENGINE_TYPE_ON_HOST, according to ecc_bits * * All DaVinci-family chips support 1-bit hardware ECC. @@ -524,6 +525,8 @@ static struct davinci_nand_pdata pdata->engine_type =3D NAND_ECC_ENGINE_TYPE_SOFT; if (!strncmp("hw", mode, 2)) pdata->engine_type =3D NAND_ECC_ENGINE_TYPE_ON_HOST; + if (!strncmp("on-die", mode, 6)) + pdata->engine_type =3D NAND_ECC_ENGINE_TYPE_ON_DIE; } if (!of_property_read_u32(pdev->dev.of_node, "ti,davinci-ecc-bits", &prop)) @@ -580,6 +583,7 @@ static int davinci_nand_attach_chip(struct nand_chip *c= hip) =20 switch (chip->ecc.engine_type) { case NAND_ECC_ENGINE_TYPE_NONE: + case NAND_ECC_ENGINE_TYPE_ON_DIE: pdata->ecc_bits =3D 0; break; case NAND_ECC_ENGINE_TYPE_SOFT: @@ -914,4 +918,3 @@ module_platform_driver(nand_davinci_driver); MODULE_LICENSE("GPL"); MODULE_AUTHOR("Texas Instruments"); MODULE_DESCRIPTION("Davinci NAND flash driver"); - --=20 2.46.0 From nobody Thu Nov 28 13:46:56 2024 Received: from mail-lj1-f180.google.com (mail-lj1-f180.google.com [209.85.208.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C24E61BC9F0; Tue, 1 Oct 2024 10:43:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Add "on-die" as ECC engine type in order to be compatible with those. Signed-off-by: Marcus Folkesson --- Documentation/devicetree/bindings/mtd/davinci-nand.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mtd/davinci-nand.txt b/Docum= entation/devicetree/bindings/mtd/davinci-nand.txt index eb8e2ff4dbd2901b3c396f2e66c1f590a32dcf67..9afda5cd956494c6b3171bdbaec= aeb289acd64ea 100644 --- a/Documentation/devicetree/bindings/mtd/davinci-nand.txt +++ b/Documentation/devicetree/bindings/mtd/davinci-nand.txt @@ -44,6 +44,7 @@ Recommended properties : - "none" - "soft" - "hw" + - "on-die" =20 - ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4. =20 --=20 2.46.0