From nobody Thu Nov 28 15:38:47 2024 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id ACCCA1922E5; Mon, 30 Sep 2024 14:58:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727708302; cv=none; b=f4MjMyB9FVlvvFsJ1ealA9hwFcdwu99S6blk/0hLMKPbGdQEp+ECJ7M7K5BWLWFsfDQD4g5DFjn7U4FzMax5dSJYo8gcGI1YusTdYOKrxlrye6C6CjRrmVI5EuimkxYBrvK/AVDqW0pWHbjTML5sc84yu+fIr+25kTcmGEzwmkg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727708302; c=relaxed/simple; bh=aSv48EF/xq4kmxfXe/OmnMinPAbSZsyx0W4kFM7uZNI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=qO5ARagiVQKX6SbrKnTauO9HJbosEo87ilbKzpKWfsRcpsbsqlkjy308w3IVOnkCliN6kqxjzzNJ22bFQ5RYyzorUHdGa9VQq78dkbXGN0wnPZuddegOfktUAMC1tl9Vpy06iLB2esQ3zPg15Lu/jPcHnkuf9zWJNJvS1z0cEuc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-IronPort-AV: E=Sophos;i="6.11,165,1725289200"; d="scan'208";a="224342602" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 30 Sep 2024 23:53:12 +0900 Received: from mulinux.home (unknown [10.226.92.226]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 3584D4204B8F; Mon, 30 Sep 2024 23:53:02 +0900 (JST) From: Fabrizio Castro To: Linus Walleij , Geert Uytterhoeven Cc: Fabrizio Castro , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Paterson , Biju Das , Lad Prabhakar Subject: [PATCH v2 1/5] pinctrl: renesas: rzg2l: Remove RZG2L_TINT_IRQ_START_INDEX Date: Mon, 30 Sep 2024 15:52:40 +0100 Message-Id: <20240930145244.356565-2-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240930145244.356565-1-fabrizio.castro.jz@renesas.com> References: <20240930145244.356565-1-fabrizio.castro.jz@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RZ/V2H(P) has 16 IRQ interrupts, while every other platforms has 8, and this affects the start index of TINT interrupts (1 + 16 =3D 17, rather than 1 + 8 =3D 9). Macro RZG2L_TINT_IRQ_START_INDEX cannot work anymore, replace it with a new member within struct rzg2l_hwcfg. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Tested-by: Claudiu Beznea --- v1->v2: * No change drivers/pinctrl/renesas/pinctrl-rzg2l.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 5a403915fed2..0aba75dce229 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -168,7 +168,6 @@ #define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT) =20 #define RZG2L_TINT_MAX_INTERRUPT 32 -#define RZG2L_TINT_IRQ_START_INDEX 9 #define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i)) =20 /* Custom pinconf parameters */ @@ -251,6 +250,7 @@ enum rzg2l_iolh_index { * @func_base: base number for port function (see register PFC) * @oen_max_pin: the maximum pin number supporting output enable * @oen_max_port: the maximum port number supporting output enable + * @tint_start_index: the start index for the TINT interrupts */ struct rzg2l_hwcfg { const struct rzg2l_register_offsets regs; @@ -262,6 +262,7 @@ struct rzg2l_hwcfg { u8 func_base; u8 oen_max_pin; u8 oen_max_port; + unsigned int tint_start_index; }; =20 struct rzg2l_dedicated_configs { @@ -2379,7 +2380,7 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct gp= io_chip *gc, =20 rzg2l_gpio_irq_endisable(pctrl, child, true); pctrl->hwirq[irq] =3D child; - irq +=3D RZG2L_TINT_IRQ_START_INDEX; + irq +=3D pctrl->data->hwcfg->tint_start_index; =20 /* All these interrupts are level high in the CPU */ *parent_type =3D IRQ_TYPE_LEVEL_HIGH; @@ -3035,6 +3036,7 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg =3D { }, .iolh_groupb_oi =3D { 100, 66, 50, 33, }, .oen_max_pin =3D 0, + .tint_start_index =3D 9, }; =20 static const struct rzg2l_hwcfg rzg3s_hwcfg =3D { @@ -3067,12 +3069,14 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg =3D { .func_base =3D 1, .oen_max_pin =3D 1, /* Pin 1 of P0 and P7 is the maximum OEN pin. */ .oen_max_port =3D 7, /* P7_1 is the maximum OEN port. */ + .tint_start_index =3D 9, }; =20 static const struct rzg2l_hwcfg rzv2h_hwcfg =3D { .regs =3D { .pwpr =3D 0x3c04, }, + .tint_start_index =3D 17, }; =20 static struct rzg2l_pinctrl_data r9a07g043_data =3D { --=20 2.34.1 From nobody Thu Nov 28 15:38:47 2024 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 19EC6192D67; Mon, 30 Sep 2024 14:58:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727708306; cv=none; b=nFZkn8Lk17ot1azAgcFSrEo2TIbUR/0EFgOq9viyk9YbbE5AwG+o+zVWa8OuiwpkAhUEqxybsaC8eZF1OR3vF/jcNLTZ9kG99ocGb0a/XMBEjQJPUrhSNE1VxhzMoPM/WsycyI8d3mr98Kp+x8E4BfA3707A72hissBEmA8oNF4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727708306; c=relaxed/simple; bh=rhcjgmdWEtFtAnSszBoKBMpu9S2+ha1ezwKmgqgSxqQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Ud3EoT7o/luy9EHePeOZ3Zc3eE2JarFe1X/ToehA3shJpea+bwqTsn6+KLVKqQxImj/v95sWfHomZq5Xi1y5mgWGE+myV+pnQhV356PKtPF4W5pye/g0zUzkoIUEtGA4eV27A7S+ZGJN10rzsD3OOtzpuS3oabW/jj0rNhPbljk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-IronPort-AV: E=Sophos;i="6.11,165,1725289200"; d="scan'208";a="220366615" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 30 Sep 2024 23:53:21 +0900 Received: from mulinux.home (unknown [10.226.92.226]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id E0BF84204B95; Mon, 30 Sep 2024 23:53:07 +0900 (JST) From: Fabrizio Castro To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven Cc: Fabrizio Castro , Magnus Damm , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Chris Paterson , Biju Das , Lad Prabhakar Subject: [PATCH v2 2/5] dt-bindings: interrupt-controller: Add Renesas RZ/V2H(P) Interrupt Controller Date: Mon, 30 Sep 2024 15:52:41 +0100 Message-Id: <20240930145244.356565-3-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240930145244.356565-1-fabrizio.castro.jz@renesas.com> References: <20240930145244.356565-1-fabrizio.castro.jz@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add DT bindings for the Renesas RZ/V2H(P) Interrupt Controller. Also add macros for the NMI and IRQ0-15 interrupts which map the SPI0-16 interrupts on the RZ/V2H(P) SoC so that they can be used in the first cell of the interrupt specifiers. For the second cell of the interrupt specifier, since NMI, IRQn and TINTn support different types of interrupts between themselves, add helper macros to make it easier for the user to work out what's available. Signed-off-by: Fabrizio Castro Reviewed-by: Rob Herring (Arm) --- v1->v2: * Removed '|' from main description * Reworked main description * Fixed indentation of #interrupt-cells * Reworked description of #interrupt-cells * Dropped file include/dt-bindings/interrupt-controller/icu-rzv2h.h .../renesas,rzv2h-icu.yaml | 276 ++++++++++++++++++ 1 file changed, 276 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= renesas,rzv2h-icu.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas= ,rzv2h-icu.yaml b/Documentation/devicetree/bindings/interrupt-controller/re= nesas,rzv2h-icu.yaml new file mode 100644 index 000000000000..3c48e9c2a954 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-= icu.yaml @@ -0,0 +1,276 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/renesas,rzv2h-icu.= yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/V2H(P) Interrupt Control Unit + +maintainers: + - Fabrizio Castro + - Geert Uytterhoeven + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +description: + The Interrupt Control Unit (ICU) handles external interrupts (NMI, IRQ, = and + TINT), error interrupts, DMAC requests, GPT interrupts, and internal + interrupts. + +properties: + compatible: + const: renesas,r9a09g057-icu # RZ/V2H(P) + + '#interrupt-cells': + description: The first cell is the SPI number of the NMI or the + PORT_IRQ[0-15] interrupt, as per user manual. The second cell is use= d to + specify the flag. + const: 2 + + '#address-cells': + const: 0 + + interrupt-controller: true + + reg: + maxItems: 1 + + interrupts: + minItems: 58 + items: + - description: NMI interrupt + - description: IRQ0 interrupt + - description: IRQ1 interrupt + - description: IRQ2 interrupt + - description: IRQ3 interrupt + - description: IRQ4 interrupt + - description: IRQ5 interrupt + - description: IRQ6 interrupt + - description: IRQ7 interrupt + - description: IRQ8 interrupt + - description: IRQ9 interrupt + - description: IRQ10 interrupt + - description: IRQ11 interrupt + - description: IRQ12 interrupt + - description: IRQ13 interrupt + - description: IRQ14 interrupt + - description: IRQ15 interrupt + - description: GPIO interrupt, TINT0 + - description: GPIO interrupt, TINT1 + - description: GPIO interrupt, TINT2 + - description: GPIO interrupt, TINT3 + - description: GPIO interrupt, TINT4 + - description: GPIO interrupt, TINT5 + - description: GPIO interrupt, TINT6 + - description: GPIO interrupt, TINT7 + - description: GPIO interrupt, TINT8 + - description: GPIO interrupt, TINT9 + - description: GPIO interrupt, TINT10 + - description: GPIO interrupt, TINT11 + - description: GPIO interrupt, TINT12 + - description: GPIO interrupt, TINT13 + - description: GPIO interrupt, TINT14 + - description: GPIO interrupt, TINT15 + - description: GPIO interrupt, TINT16 + - description: GPIO interrupt, TINT17 + - description: GPIO interrupt, TINT18 + - description: GPIO interrupt, TINT19 + - description: GPIO interrupt, TINT20 + - description: GPIO interrupt, TINT21 + - description: GPIO interrupt, TINT22 + - description: GPIO interrupt, TINT23 + - description: GPIO interrupt, TINT24 + - description: GPIO interrupt, TINT25 + - description: GPIO interrupt, TINT26 + - description: GPIO interrupt, TINT27 + - description: GPIO interrupt, TINT28 + - description: GPIO interrupt, TINT29 + - description: GPIO interrupt, TINT30 + - description: GPIO interrupt, TINT31 + - description: Software interrupt, INTA55_0 + - description: Software interrupt, INTA55_1 + - description: Software interrupt, INTA55_2 + - description: Software interrupt, INTA55_3 + - description: Error interrupt to CA55 + - description: GTCCRA compare match/input capture (U0) + - description: GTCCRB compare match/input capture (U0) + - description: GTCCRA compare match/input capture (U1) + - description: GTCCRB compare match/input capture (U1) + + interrupt-names: + minItems: 58 + items: + - const: nmi + - const: irq0 + - const: irq1 + - const: irq2 + - const: irq3 + - const: irq4 + - const: irq5 + - const: irq6 + - const: irq7 + - const: irq8 + - const: irq9 + - const: irq10 + - const: irq11 + - const: irq12 + - const: irq13 + - const: irq14 + - const: irq15 + - const: tint0 + - const: tint1 + - const: tint2 + - const: tint3 + - const: tint4 + - const: tint5 + - const: tint6 + - const: tint7 + - const: tint8 + - const: tint9 + - const: tint10 + - const: tint11 + - const: tint12 + - const: tint13 + - const: tint14 + - const: tint15 + - const: tint16 + - const: tint17 + - const: tint18 + - const: tint19 + - const: tint20 + - const: tint21 + - const: tint22 + - const: tint23 + - const: tint24 + - const: tint25 + - const: tint26 + - const: tint27 + - const: tint28 + - const: tint29 + - const: tint30 + - const: tint31 + - const: int-ca55-0 + - const: int-ca55-1 + - const: int-ca55-2 + - const: int-ca55-3 + - const: icu-error-ca55 + - const: gpt-u0-gtciada + - const: gpt-u0-gtciadb + - const: gpt-u1-gtciada + - const: gpt-u1-gtciadb + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - '#interrupt-cells' + - '#address-cells' + - interrupt-controller + - interrupts + - interrupt-names + - clocks + - power-domains + - resets + +unevaluatedProperties: false + +examples: + - | + #include + #include + + icu: interrupt-controller@10400000 { + compatible =3D "renesas,r9a09g057-icu"; + reg =3D <0x10400000 0x10000>; + #interrupt-cells =3D <2>; + #address-cells =3D <0>; + interrupt-controller; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "nmi", + "irq0", "irq1", "irq2", "irq3", + "irq4", "irq5", "irq6", "irq7", + "irq8", "irq9", "irq10", "irq11", + "irq12", "irq13", "irq14", "irq15", + "tint0", "tint1", "tint2", "tint3", + "tint4", "tint5", "tint6", "tint7", + "tint8", "tint9", "tint10", "tint11", + "tint12", "tint13", "tint14", "tint15", + "tint16", "tint17", "tint18", "tint19", + "tint20", "tint21", "tint22", "tint23", + "tint24", "tint25", "tint26", "tint27", + "tint28", "tint29", "tint30", "tint31", + "int-ca55-0", "int-ca55-1", + "int-ca55-2", "int-ca55-3", + "icu-error-ca55", + "gpt-u0-gtciada", "gpt-u0-gtciadb", + "gpt-u1-gtciada", "gpt-u1-gtciadb"; + clocks =3D <&cpg CPG_MOD 0x5>; + power-domains =3D <&cpg>; + resets =3D <&cpg 0x36>; + }; --=20 2.34.1 From nobody Thu Nov 28 15:38:47 2024 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DC547192599; Mon, 30 Sep 2024 14:53:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727708008; cv=none; b=LDK+YD6hKoHvrki+B7NEYJLsGmrDE726EA+IZBj5Vsw0g0Lwq8wN7gpmccrOoTfnFqSNoMHhU5fGDF85BTcwVWdhVAwsN79sBAL0zQpjCoXhA0/ocJFN7H2lQMoeMJBV9qerUZ1FAAUMTtjzI6tFaG1IDeLP1/5t3wuNdseFoe8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727708008; c=relaxed/simple; bh=skhX5iggBsH2GvmQkeGyNH4KLXmlyqwdCB2pLRX3xUg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=LkWqUIzQpawDb4F4e3ML5BbHq510cU0P3HqwNPI/vTB+vlVPxHLIMAInqfaFSxKGyuMmRTDJuoYpvMnZsBJYjW7OF292ePndM45SYHDq2jGU+OYXdzVhv20IDv6W6f/WwScjvcDmIxKU6aQcKv2+4TplrlUERqF8aOi0YMBLZlo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-IronPort-AV: E=Sophos;i="6.11,165,1725289200"; d="scan'208";a="224342622" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 30 Sep 2024 23:53:25 +0900 Received: from mulinux.home (unknown [10.226.92.226]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 1E6C24204B8B; Mon, 30 Sep 2024 23:53:14 +0900 (JST) From: Fabrizio Castro To: Michael Turquette , Stephen Boyd , Geert Uytterhoeven Cc: Fabrizio Castro , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Paterson , Biju Das , Lad Prabhakar Subject: [PATCH v2 3/5] clk: renesas: r9a09g057: Add clock and reset entries for ICU Date: Mon, 30 Sep 2024 15:52:42 +0100 Message-Id: <20240930145244.356565-4-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240930145244.356565-1-fabrizio.castro.jz@renesas.com> References: <20240930145244.356565-1-fabrizio.castro.jz@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add clock and reset entries for the Renesas RZ/V2H(P) ICU IP block. Signed-off-by: Lad Prabhakar Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven --- v1->v2: * No change drivers/clk/renesas/r9a09g057-cpg.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a0= 9g057-cpg.c index 3ee32db5c0af..b82fee006d65 100644 --- a/drivers/clk/renesas/r9a09g057-cpg.c +++ b/drivers/clk/renesas/r9a09g057-cpg.c @@ -78,6 +78,7 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __= initconst =3D { }; =20 static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst =3D { + DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5), DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3), DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4), DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5), @@ -119,6 +120,7 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] = __initconst =3D { }; =20 static const struct rzv2h_reset r9a09g057_resets[] __initconst =3D { + DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */ DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */ DEF_RST(6, 14, 2, 31), /* GTM_1_PRESETZ */ DEF_RST(6, 15, 3, 0), /* GTM_2_PRESETZ */ --=20 2.34.1 From nobody Thu Nov 28 15:38:47 2024 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1B7C3192D60; Mon, 30 Sep 2024 14:53:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727708011; cv=none; b=CRe2A2YqzMKcQjRznu1kKlP5sjqx1hTPcdnRS5Hy4MJzJrRTGqkdmzHAzCZf63n16yJmJnKdOrhuIrTyBcTRaD7KNU/d9smksKerEhydBrB6eYr3Uybn/dWTyr5m2jIOvHf2dxKqX2JgyP5foNkbhTz3R51iRZYgCBcCKEO5JrM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727708011; c=relaxed/simple; bh=aaLQb8+rfC7QTikzp9RUyNNtGLgPiYl0v3UKmd4LsYE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=IX1281VVbjFYE+SjBuIsxZCJsM1LFhJubeIcSYCew6kw9+YooYV75pdq2qW6DkMGWNMv0dzcuSEPXplRIeozUynE54S/Lb+I65+6S0BzGD7QswEgHtEjg6vi+iHIjCkOoXJywWM2ZsSU3Vwe0UYoUsMy2vuL9iWvhqnu5npAORw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-IronPort-AV: E=Sophos;i="6.11,165,1725289200"; d="scan'208";a="224342625" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 30 Sep 2024 23:53:25 +0900 Received: from mulinux.home (unknown [10.226.92.226]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 090E04204B94; Mon, 30 Sep 2024 23:53:19 +0900 (JST) From: Fabrizio Castro To: Thomas Gleixner , Philipp Zabel , Geert Uytterhoeven Cc: Fabrizio Castro , Magnus Damm , linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Chris Paterson , Biju Das , Lad Prabhakar Subject: [PATCH v2 4/5] irqchip: Add RZ/V2H(P) Interrupt Control Unit (ICU) driver Date: Mon, 30 Sep 2024 15:52:43 +0100 Message-Id: <20240930145244.356565-5-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240930145244.356565-1-fabrizio.castro.jz@renesas.com> References: <20240930145244.356565-1-fabrizio.castro.jz@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add driver for the Renesas RZ/V2H(P) Interrupt Control Unit (ICU). This driver supports the external interrupts NMI, IRQn, and TINTn. Signed-off-by: Fabrizio Castro --- v1->v2: * Fixed missing put_device in rzv2h_icu_init drivers/irqchip/Kconfig | 7 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-renesas-rzv2h.c | 527 ++++++++++++++++++++++++++++ drivers/soc/renesas/Kconfig | 1 + 4 files changed, 536 insertions(+) create mode 100644 drivers/irqchip/irq-renesas-rzv2h.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 341cd9ca5a05..006a47a86ed5 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -265,6 +265,13 @@ config RENESAS_RZG2L_IRQC Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Control= ler for external devices. =20 +config RENESAS_RZV2H_ICU + bool "Renesas RZ/V2H(P) ICU support" if COMPILE_TEST + select GENERIC_IRQ_CHIP + select IRQ_DOMAIN_HIERARCHY + help + Enable support for the Renesas RZ/V2H(P) Interrupt Control Unit (ICU) + config SL28CPLD_INTC bool "Kontron sl28cpld IRQ controller" depends on MFD_SL28CPLD=3Dy || COMPILE_TEST diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index e3679ec2b9f7..94ecaebff37f 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -51,6 +51,7 @@ obj-$(CONFIG_RENESAS_INTC_IRQPIN) +=3D irq-renesas-intc-i= rqpin.o obj-$(CONFIG_RENESAS_IRQC) +=3D irq-renesas-irqc.o obj-$(CONFIG_RENESAS_RZA1_IRQC) +=3D irq-renesas-rza1.o obj-$(CONFIG_RENESAS_RZG2L_IRQC) +=3D irq-renesas-rzg2l.o +obj-$(CONFIG_RENESAS_RZV2H_ICU) +=3D irq-renesas-rzv2h.o obj-$(CONFIG_VERSATILE_FPGA_IRQ) +=3D irq-versatile-fpga.o obj-$(CONFIG_ARCH_NSPIRE) +=3D irq-zevio.o obj-$(CONFIG_ARCH_VT8500) +=3D irq-vt8500.o diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-rene= sas-rzv2h.c new file mode 100644 index 000000000000..9cdd4e345850 --- /dev/null +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -0,0 +1,527 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RZ/V2H(P) ICU Driver + * + * Based on irq-renesas-rzg2l.c + * + * Copyright (C) 2024 Renesas Electronics Corporation. + * + * Author: Fabrizio Castro + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* DT "interrupts" indexes */ +#define ICU_IRQ_START 1 +#define ICU_IRQ_COUNT 16 +#define ICU_TINT_START (ICU_IRQ_START + ICU_IRQ_COUNT) +#define ICU_TINT_COUNT 32 +#define ICU_NUM_IRQ (ICU_TINT_START + ICU_TINT_COUNT) + +/* Registers */ +#define ICU_NSCNT 0x00 +#define ICU_NSCLR 0x04 +#define ICU_NITSR 0x08 +#define ICU_ISCTR 0x10 +#define ICU_ISCLR 0x14 +#define ICU_IITSR 0x18 +#define ICU_TSCTR 0x20 +#define ICU_TSCLR 0x24 +#define ICU_TITSR(k) (0x28 + (k) * 4) +#define ICU_TSSR(k) (0x30 + (k) * 4) + +/* NMI */ +#define ICU_NMI_EDGE_FALLING 0 +#define ICU_NMI_EDGE_RISING 1 + +#define ICU_NSCNT_NSTAT BIT(0) +#define ICU_NSCNT_NSTAT_DETECTED 1 + +#define ICU_NSCLR_NCLR BIT(0) + +/* IRQ */ +#define ICU_IRQ_LEVEL_LOW 0 +#define ICU_IRQ_EDGE_FALLING 1 +#define ICU_IRQ_EDGE_RISING 2 +#define ICU_IRQ_EDGE_BOTH 3 + +#define ICU_IITSR_IITSEL_PREP(iitsel, n) ((iitsel) << ((n) * 2)) +#define ICU_IITSR_IITSEL_GET(iitsr, n) (((iitsr) >> ((n) * 2)) & 0x03) +#define ICU_IITSR_IITSEL_MASK(n) ICU_IITSR_IITSEL_PREP(0x03, n) + +/* TINT */ +#define ICU_TINT_EDGE_RISING 0 +#define ICU_TINT_EDGE_FALLING 1 +#define ICU_TINT_LEVEL_HIGH 2 +#define ICU_TINT_LEVEL_LOW 3 + +#define ICU_TSSR_K(tint_nr) ((tint_nr) / 4) +#define ICU_TSSR_TSSEL_N(tint_nr) ((tint_nr) % 4) +#define ICU_TSSR_TSSEL_PREP(tssel, n) ((tssel) << ((n) * 8)) +#define ICU_TSSR_TSSEL_MASK(n) ICU_TSSR_TSSEL_PREP(0x7F, n) +#define ICU_TSSR_TIEN(n) (BIT(7) << ((n) * 8)) + +#define ICU_TITSR_K(tint_nr) ((tint_nr) / 16) +#define ICU_TITSR_TITSEL_N(tint_nr) ((tint_nr) % 16) +#define ICU_TITSR_TITSEL_PREP(titsel, n) ICU_IITSR_IITSEL_PREP(titsel, n) +#define ICU_TITSR_TITSEL_MASK(n) ICU_IITSR_IITSEL_MASK(n) +#define ICU_TITSR_TITSEL_GET(titsr, n) ICU_IITSR_IITSEL_GET(titsr, n) + +#define ICU_TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x)) +#define ICU_TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x)) +#define ICU_PB5_TINT 0x55 + +/** + * struct rzv2h_icu_priv - Interrupt Control Unit controller private data + * structure. + * @base: Controller's base address + * @irqchip: Pointer to struct irq_chip + * @fwspec: IRQ firmware specific data + * @lock: Lock to serialize access to hardware registers + */ +struct rzv2h_icu_priv { + void __iomem *base; + const struct irq_chip *irqchip; + struct irq_fwspec fwspec[ICU_NUM_IRQ]; + raw_spinlock_t lock; +}; + +static inline struct rzv2h_icu_priv *irq_data_to_priv(struct irq_data *dat= a) +{ + return data->domain->host_data; +} + +static void rzv2h_clear_nmi_int(struct rzv2h_icu_priv *priv) +{ + u32 nscnt =3D readl_relaxed(priv->base + ICU_NSCNT); + + if ((nscnt & ICU_NSCNT_NSTAT) =3D=3D ICU_NSCNT_NSTAT_DETECTED) + writel_relaxed(ICU_NSCLR_NCLR, priv->base + ICU_NSCLR); +} + +static void rzv2h_clear_irq_int(struct rzv2h_icu_priv *priv, unsigned int = hwirq) +{ + unsigned int irq_nr =3D hwirq - ICU_IRQ_START; + u32 isctr, iitsr, iitsel; + u32 bit =3D BIT(irq_nr); + + isctr =3D readl_relaxed(priv->base + ICU_ISCTR); + iitsr =3D readl_relaxed(priv->base + ICU_IITSR); + iitsel =3D ICU_IITSR_IITSEL_GET(iitsr, irq_nr); + + /* + * When level sensing is used, the interrupt flag gets automatically + * cleared when the interrupt signal is de-asserted by the source of + * the interrupt request, therefore clear the interrupt only for edge + * triggered interrupts. + */ + if ((isctr & bit) && (iitsel !=3D ICU_IRQ_LEVEL_LOW)) + writel_relaxed(bit, priv->base + ICU_ISCLR); +} + +static void rzv2h_clear_tint_int(struct rzv2h_icu_priv *priv, + unsigned int hwirq) +{ + unsigned int tint_nr =3D hwirq - ICU_TINT_START; + int titsel_n =3D ICU_TITSR_TITSEL_N(tint_nr); + u32 tsctr, titsr, titsel; + u32 bit =3D BIT(tint_nr); + int k =3D tint_nr / 16; + + tsctr =3D readl_relaxed(priv->base + ICU_TSCTR); + titsr =3D readl_relaxed(priv->base + ICU_TITSR(k)); + titsel =3D ICU_TITSR_TITSEL_GET(titsr, titsel_n); + + /* + * Writing 1 to the corresponding flag from register ICU_TSCTR only + * has effect if TSTATn =3D 1b and if it's a rising edge or a falling + * edge interrupt. + */ + if ((tsctr & bit) && ((titsel =3D=3D ICU_TINT_EDGE_RISING) || + (titsel =3D=3D ICU_TINT_EDGE_FALLING))) + writel_relaxed(bit, priv->base + ICU_TSCLR); +} + +static void rzv2h_icu_eoi(struct irq_data *d) +{ + struct rzv2h_icu_priv *priv =3D irq_data_to_priv(d); + unsigned int hw_irq =3D irqd_to_hwirq(d); + + raw_spin_lock(&priv->lock); + if (hw_irq >=3D ICU_TINT_START) + rzv2h_clear_tint_int(priv, hw_irq); + else if (hw_irq >=3D ICU_IRQ_START) + rzv2h_clear_irq_int(priv, hw_irq); + else + rzv2h_clear_nmi_int(priv); + raw_spin_unlock(&priv->lock); + + irq_chip_eoi_parent(d); +} + +static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable) +{ + struct rzv2h_icu_priv *priv =3D irq_data_to_priv(d); + unsigned int hw_irq =3D irqd_to_hwirq(d); + u32 tint_nr, tssel_n, k, tssr; + + if (hw_irq < ICU_TINT_START) + return; + + tint_nr =3D hw_irq - ICU_TINT_START; + k =3D ICU_TSSR_K(tint_nr); + tssel_n =3D ICU_TSSR_TSSEL_N(tint_nr); + + raw_spin_lock(&priv->lock); + tssr =3D readl_relaxed(priv->base + ICU_TSSR(k)); + if (enable) + tssr |=3D ICU_TSSR_TIEN(tssel_n); + else + tssr &=3D ~ICU_TSSR_TIEN(tssel_n); + writel_relaxed(tssr, priv->base + ICU_TSSR(k)); + raw_spin_unlock(&priv->lock); +} + +static void rzv2h_icu_irq_disable(struct irq_data *d) +{ + irq_chip_disable_parent(d); + rzv2h_tint_irq_endisable(d, false); +} + +static void rzv2h_icu_irq_enable(struct irq_data *d) +{ + rzv2h_tint_irq_endisable(d, true); + irq_chip_enable_parent(d); +} + +static int rzv2h_nmi_set_type(struct irq_data *d, unsigned int type) +{ + struct rzv2h_icu_priv *priv =3D irq_data_to_priv(d); + u32 sense; + + switch (type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_EDGE_FALLING: + sense =3D ICU_NMI_EDGE_FALLING; + break; + + case IRQ_TYPE_EDGE_RISING: + sense =3D ICU_NMI_EDGE_RISING; + break; + + default: + return -EINVAL; + } + + writel_relaxed(sense, priv->base + ICU_NITSR); + + return 0; +} + +static int rzv2h_irq_set_type(struct irq_data *d, unsigned int type) +{ + struct rzv2h_icu_priv *priv =3D irq_data_to_priv(d); + unsigned int hwirq =3D irqd_to_hwirq(d); + u32 irq_nr =3D hwirq - ICU_IRQ_START; + u32 iitsr, sense; + + switch (type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_LEVEL_LOW: + sense =3D ICU_IRQ_LEVEL_LOW; + break; + + case IRQ_TYPE_EDGE_FALLING: + sense =3D ICU_IRQ_EDGE_FALLING; + break; + + case IRQ_TYPE_EDGE_RISING: + sense =3D ICU_IRQ_EDGE_RISING; + break; + + case IRQ_TYPE_EDGE_BOTH: + sense =3D ICU_IRQ_EDGE_BOTH; + break; + + default: + return -EINVAL; + } + + raw_spin_lock(&priv->lock); + iitsr =3D readl_relaxed(priv->base + ICU_IITSR); + iitsr &=3D ~ICU_IITSR_IITSEL_MASK(irq_nr); + iitsr |=3D ICU_IITSR_IITSEL_PREP(sense, irq_nr); + rzv2h_clear_irq_int(priv, hwirq); + writel_relaxed(iitsr, priv->base + ICU_IITSR); + raw_spin_unlock(&priv->lock); + + return 0; +} + +static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) +{ + u32 titsr, titsr_k, titsel_n, tien; + struct rzv2h_icu_priv *priv; + u32 tssr, tssr_k, tssel_n; + unsigned int hwirq; + u32 tint, sense; + int tint_nr; + + switch (type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_LEVEL_LOW: + sense =3D ICU_TINT_LEVEL_LOW; + break; + + case IRQ_TYPE_LEVEL_HIGH: + sense =3D ICU_TINT_LEVEL_HIGH; + break; + + case IRQ_TYPE_EDGE_RISING: + sense =3D ICU_TINT_EDGE_RISING; + break; + + case IRQ_TYPE_EDGE_FALLING: + sense =3D ICU_TINT_EDGE_FALLING; + break; + + default: + return -EINVAL; + } + + tint =3D (u32)(uintptr_t)irq_data_get_irq_chip_data(d); + if (tint > ICU_PB5_TINT) + return -EINVAL; + + priv =3D irq_data_to_priv(d); + hwirq =3D irqd_to_hwirq(d); + + tint_nr =3D hwirq - ICU_TINT_START; + + tssr_k =3D ICU_TSSR_K(tint_nr); + tssel_n =3D ICU_TSSR_TSSEL_N(tint_nr); + + titsr_k =3D ICU_TITSR_K(tint_nr); + titsel_n =3D ICU_TITSR_TITSEL_N(tint_nr); + tien =3D ICU_TSSR_TIEN(titsel_n); + + raw_spin_lock(&priv->lock); + + tssr =3D readl_relaxed(priv->base + ICU_TSSR(tssr_k)); + tssr &=3D ~(ICU_TSSR_TSSEL_MASK(tssel_n) | tien); + tssr |=3D ICU_TSSR_TSSEL_PREP(tint, tssel_n); + + writel_relaxed(tssr, priv->base + ICU_TSSR(tssr_k)); + + titsr =3D readl_relaxed(priv->base + ICU_TITSR(titsr_k)); + titsr &=3D ~ICU_TITSR_TITSEL_MASK(titsel_n); + titsr |=3D ICU_TITSR_TITSEL_PREP(sense, titsel_n); + + writel_relaxed(titsr, priv->base + ICU_TITSR(titsr_k)); + + rzv2h_clear_tint_int(priv, hwirq); + + writel_relaxed(tssr | tien, priv->base + ICU_TSSR(tssr_k)); + + raw_spin_unlock(&priv->lock); + + return 0; +} + +static int rzv2h_icu_set_type(struct irq_data *d, unsigned int type) +{ + unsigned int hw_irq =3D irqd_to_hwirq(d); + int ret; + + if (hw_irq >=3D ICU_TINT_START) + ret =3D rzv2h_tint_set_type(d, type); + else if (hw_irq >=3D ICU_IRQ_START) + ret =3D rzv2h_irq_set_type(d, type); + else + ret =3D rzv2h_nmi_set_type(d, type); + + if (ret) + return ret; + + return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); +} + +static const struct irq_chip rzv2h_icu_chip =3D { + .name =3D "rzv2h-icu", + .irq_eoi =3D rzv2h_icu_eoi, + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, + .irq_disable =3D rzv2h_icu_irq_disable, + .irq_enable =3D rzv2h_icu_irq_enable, + .irq_get_irqchip_state =3D irq_chip_get_parent_state, + .irq_set_irqchip_state =3D irq_chip_set_parent_state, + .irq_retrigger =3D irq_chip_retrigger_hierarchy, + .irq_set_type =3D rzv2h_icu_set_type, + .irq_set_affinity =3D irq_chip_set_affinity_parent, + .flags =3D IRQCHIP_SET_TYPE_MASKED, +}; + +static int rzv2h_icu_alloc(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs, void *arg) +{ + struct rzv2h_icu_priv *priv =3D domain->host_data; + unsigned long tint =3D 0; + irq_hw_number_t hwirq; + unsigned int type; + int ret; + + ret =3D irq_domain_translate_twocell(domain, arg, &hwirq, &type); + if (ret) + return ret; + + /* + * For TINT interrupts the hwirq and TINT are encoded in + * fwspec->param[0]. + * hwirq is embedded in bits 0-15. + * TINT is embedded in bits 16-31. + */ + if (hwirq >=3D ICU_TINT_START) { + tint =3D ICU_TINT_EXTRACT_GPIOINT(hwirq); + hwirq =3D ICU_TINT_EXTRACT_HWIRQ(hwirq); + + if (hwirq < ICU_TINT_START) + return -EINVAL; + } + + if (hwirq > (ICU_NUM_IRQ - 1)) + return -EINVAL; + + ret =3D irq_domain_set_hwirq_and_chip(domain, virq, hwirq, priv->irqchip, + (void *)(uintptr_t)tint); + if (ret) + return ret; + + return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, + &priv->fwspec[hwirq]); +} + +static const struct irq_domain_ops rzv2h_icu_domain_ops =3D { + .alloc =3D rzv2h_icu_alloc, + .free =3D irq_domain_free_irqs_common, + .translate =3D irq_domain_translate_twocell, +}; + +static int rzv2h_icu_parse_interrupts(struct rzv2h_icu_priv *priv, + struct device_node *np) +{ + struct of_phandle_args map; + unsigned int i; + int ret; + + for (i =3D 0; i < ICU_NUM_IRQ; i++) { + ret =3D of_irq_parse_one(np, i, &map); + if (ret) + return ret; + + of_phandle_args_to_fwspec(np, map.args, map.args_count, + &priv->fwspec[i]); + } + + return 0; +} + +static int rzv2h_icu_init(struct device_node *node, + struct device_node *parent) +{ + struct irq_domain *irq_domain, *parent_domain; + struct rzv2h_icu_priv *rzv2h_icu_data; + struct platform_device *pdev; + struct reset_control *resetn; + int ret; + + pdev =3D of_find_device_by_node(node); + if (!pdev) + return -ENODEV; + + parent_domain =3D irq_find_host(parent); + if (!parent_domain) { + dev_err(&pdev->dev, "cannot find parent domain\n"); + ret =3D -ENODEV; + goto put_dev; + } + + rzv2h_icu_data =3D devm_kzalloc(&pdev->dev, sizeof(*rzv2h_icu_data), + GFP_KERNEL); + if (!rzv2h_icu_data) { + ret =3D -ENOMEM; + goto put_dev; + } + + rzv2h_icu_data->irqchip =3D &rzv2h_icu_chip; + + rzv2h_icu_data->base =3D devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, + NULL); + if (IS_ERR(rzv2h_icu_data->base)) { + ret =3D PTR_ERR(rzv2h_icu_data->base); + goto put_dev; + } + + ret =3D rzv2h_icu_parse_interrupts(rzv2h_icu_data, node); + if (ret) { + dev_err(&pdev->dev, "cannot parse interrupts: %d\n", ret); + goto put_dev; + } + + resetn =3D devm_reset_control_get_exclusive(&pdev->dev, NULL); + if (IS_ERR(resetn)) { + ret =3D PTR_ERR(resetn); + goto put_dev; + } + + ret =3D reset_control_deassert(resetn); + if (ret) { + dev_err(&pdev->dev, "failed to deassert resetn pin, %d\n", ret); + goto put_dev; + } + + pm_runtime_enable(&pdev->dev); + ret =3D pm_runtime_resume_and_get(&pdev->dev); + if (ret < 0) { + dev_err(&pdev->dev, "pm_runtime_resume_and_get failed: %d\n", + ret); + goto pm_disable; + } + + raw_spin_lock_init(&rzv2h_icu_data->lock); + + irq_domain =3D irq_domain_add_hierarchy(parent_domain, 0, ICU_NUM_IRQ, + node, &rzv2h_icu_domain_ops, + rzv2h_icu_data); + if (!irq_domain) { + dev_err(&pdev->dev, "failed to add irq domain\n"); + ret =3D -ENOMEM; + goto pm_put; + } + + put_device(&pdev->dev); + return 0; + +pm_put: + pm_runtime_put(&pdev->dev); +pm_disable: + pm_runtime_disable(&pdev->dev); + reset_control_assert(resetn); +put_dev: + put_device(&pdev->dev); + + return ret; +} + +IRQCHIP_PLATFORM_DRIVER_BEGIN(rzv2h_icu) +IRQCHIP_MATCH("renesas,r9a09g057-icu", rzv2h_icu_init) +IRQCHIP_PLATFORM_DRIVER_END(rzv2h_icu) +MODULE_AUTHOR("Fabrizio Castro "); +MODULE_DESCRIPTION("Renesas RZ/V2H(P) ICU Driver"); diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 5d94c3f31494..9f7fe02310b9 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -347,6 +347,7 @@ config ARCH_R9A09G011 =20 config ARCH_R9A09G057 bool "ARM64 Platform support for RZ/V2H(P)" + select RENESAS_RZV2H_ICU help This enables support for the Renesas RZ/V2H(P) SoC variants. =20 --=20 2.34.1 From nobody Thu Nov 28 15:38:47 2024 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BF1DB195805; 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dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-IronPort-AV: E=Sophos;i="6.11,165,1725289200"; d="scan'208";a="224342632" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 30 Sep 2024 23:53:37 +0900 Received: from mulinux.home (unknown [10.226.92.226]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id DEBB74204B97; Mon, 30 Sep 2024 23:53:24 +0900 (JST) From: Fabrizio Castro To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven Cc: Fabrizio Castro , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Paterson , Biju Das , Lad Prabhakar Subject: [PATCH v2 5/5] arm64: dts: renesas: r9a09g057: Add ICU node Date: Mon, 30 Sep 2024 15:52:44 +0100 Message-Id: <20240930145244.356565-6-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240930145244.356565-1-fabrizio.castro.jz@renesas.com> References: <20240930145244.356565-1-fabrizio.castro.jz@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add node for the Interrupt Control Unit IP found on the Renesas RZ/V2H(P) SoC, and modify the pinctrl node as its interrupt parent is the ICU node. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven --- v1->v2: * No change arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 88 ++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g057.dtsi index 1ad5a1b6917f..72d54aa68e37 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -90,6 +90,93 @@ soc: soc { #size-cells =3D <2>; ranges; =20 + icu: interrupt-controller@10400000 { + compatible =3D "renesas,r9a09g057-icu"; + reg =3D <0 0x10400000 0 0x10000>; + #interrupt-cells =3D <2>; + #address-cells =3D <0>; + interrupt-controller; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "nmi", + "irq0", "irq1", "irq2", "irq3", + "irq4", "irq5", "irq6", "irq7", + "irq8", "irq9", "irq10", "irq11", + "irq12", "irq13", "irq14", "irq15", + "tint0", "tint1", "tint2", "tint3", + "tint4", "tint5", "tint6", "tint7", + "tint8", "tint9", "tint10", "tint11", + "tint12", "tint13", "tint14", "tint15", + "tint16", "tint17", "tint18", "tint19", + "tint20", "tint21", "tint22", "tint23", + "tint24", "tint25", "tint26", "tint27", + "tint28", "tint29", "tint30", "tint31", + "int-ca55-0", "int-ca55-1", + "int-ca55-2", "int-ca55-3", + "icu-error-ca55", + "gpt-u0-gtciada", "gpt-u0-gtciadb", + "gpt-u1-gtciada", "gpt-u1-gtciadb"; + clocks =3D <&cpg CPG_MOD 0x5>; + power-domains =3D <&cpg>; + resets =3D <&cpg 0x36>; + }; + pinctrl: pinctrl@10410000 { compatible =3D "renesas,r9a09g057-pinctrl"; reg =3D <0 0x10410000 0 0x10000>; @@ -99,6 +186,7 @@ pinctrl: pinctrl@10410000 { gpio-ranges =3D <&pinctrl 0 0 96>; #interrupt-cells =3D <2>; interrupt-controller; + interrupt-parent =3D <&icu>; power-domains =3D <&cpg>; resets =3D <&cpg 0xa5>, <&cpg 0xa6>; }; --=20 2.34.1