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charset="utf-8" Added definitions for some pins which were missing from the S32G2 SIUL2 pinctrl driver. These pins are used by the JTAG, PFE and LLCE hardware modules. Signed-off-by: Andrei Stefanescu Reviewed-by: Matthias Brugger --- drivers/pinctrl/nxp/pinctrl-s32g2.c | 52 +++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/drivers/pinctrl/nxp/pinctrl-s32g2.c b/drivers/pinctrl/nxp/pinc= trl-s32g2.c index 440ff1879424..c49d28793b69 100644 --- a/drivers/pinctrl/nxp/pinctrl-s32g2.c +++ b/drivers/pinctrl/nxp/pinctrl-s32g2.c @@ -216,6 +216,12 @@ enum s32_pins { S32G_IMCR_CAN1_RXD =3D 631, S32G_IMCR_CAN2_RXD =3D 632, S32G_IMCR_CAN3_RXD =3D 633, + + /* JTAG IMCRs */ + S32G_IMCR_JTAG_TMS =3D 562, + S32G_IMCR_JTAG_TCK =3D 572, + S32G_IMCR_JTAG_TDI =3D 573, + /* GMAC0 */ S32G_IMCR_Ethernet_MDIO =3D 527, S32G_IMCR_Ethernet_CRS =3D 526, @@ -229,7 +235,21 @@ enum s32_pins { S32G_IMCR_Ethernet_RX_DV =3D 530, S32G_IMCR_Ethernet_TX_CLK =3D 538, S32G_IMCR_Ethernet_REF_CLK =3D 535, + /* PFE EMAC 0 MII */ + S32G_IMCR_PFE_EMAC_0_MDIO =3D 837, + S32G_IMCR_PFE_EMAC_0_CRS =3D 836, + S32G_IMCR_PFE_EMAC_0_COL =3D 835, + S32G_IMCR_PFE_EMAC_0_RX_D0 =3D 841, + S32G_IMCR_PFE_EMAC_0_RX_D1 =3D 842, + S32G_IMCR_PFE_EMAC_0_RX_D2 =3D 843, + S32G_IMCR_PFE_EMAC_0_RX_D3 =3D 844, + S32G_IMCR_PFE_EMAC_0_RX_ER =3D 840, + S32G_IMCR_PFE_EMAC_0_RX_CLK =3D 839, + S32G_IMCR_PFE_EMAC_0_RX_DV =3D 845, + S32G_IMCR_PFE_EMAC_0_TX_CLK =3D 846, + S32G_IMCR_PFE_EMAC_0_REF_CLK =3D 838, + /* PFE EMAC 1 MII */ S32G_IMCR_PFE_EMAC_1_MDIO =3D 857, S32G_IMCR_PFE_EMAC_1_CRS =3D 856, @@ -317,6 +337,13 @@ enum s32_pins { S32G_IMCR_LLCE_CAN13_RXD =3D 758, S32G_IMCR_LLCE_CAN14_RXD =3D 759, S32G_IMCR_LLCE_CAN15_RXD =3D 760, + S32G_IMCR_LLCE_UART0_RXD =3D 790, + S32G_IMCR_LLCE_UART1_RXD =3D 791, + S32G_IMCR_LLCE_UART2_RXD =3D 792, + S32G_IMCR_LLCE_UART3_RXD =3D 793, + S32G_IMCR_LLCE_LPSPI2_PCS0 =3D 811, + S32G_IMCR_LLCE_LPSPI2_SCK =3D 816, + S32G_IMCR_LLCE_LPSPI2_SIN =3D 817, S32G_IMCR_USB_CLK =3D 895, S32G_IMCR_USB_DATA0 =3D 896, S32G_IMCR_USB_DATA1 =3D 897, @@ -503,6 +530,12 @@ static const struct pinctrl_pin_desc s32_pinctrl_pads_= siul2[] =3D { S32_PINCTRL_PIN(S32G_IMCR_USDHC_DAT7), S32_PINCTRL_PIN(S32G_IMCR_USDHC_DQS), S32_PINCTRL_PIN(S32G_IMCR_CAN0_RXD), + + /* JTAG IMCRs */ + S32_PINCTRL_PIN(S32G_IMCR_JTAG_TMS), + S32_PINCTRL_PIN(S32G_IMCR_JTAG_TCK), + S32_PINCTRL_PIN(S32G_IMCR_JTAG_TDI), + /* GMAC0 */ S32_PINCTRL_PIN(S32G_IMCR_Ethernet_MDIO), S32_PINCTRL_PIN(S32G_IMCR_Ethernet_CRS), @@ -638,6 +671,13 @@ static const struct pinctrl_pin_desc s32_pinctrl_pads_= siul2[] =3D { S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN13_RXD), S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN14_RXD), S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN15_RXD), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_UART0_RXD), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_UART1_RXD), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_UART2_RXD), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_UART3_RXD), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_LPSPI2_PCS0), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_LPSPI2_SCK), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_LPSPI2_SIN), S32_PINCTRL_PIN(S32G_IMCR_CAN1_RXD), S32_PINCTRL_PIN(S32G_IMCR_CAN2_RXD), S32_PINCTRL_PIN(S32G_IMCR_CAN3_RXD), @@ -652,6 +692,18 @@ static const struct pinctrl_pin_desc s32_pinctrl_pads_= siul2[] =3D { S32_PINCTRL_PIN(S32G_IMCR_USB_DATA7), S32_PINCTRL_PIN(S32G_IMCR_USB_DIR), S32_PINCTRL_PIN(S32G_IMCR_USB_NXT), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_MDIO), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_CRS), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_COL), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_RX_D0), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_RX_D1), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_RX_D2), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_RX_D3), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_RX_ER), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_RX_CLK), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_RX_DV), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_TX_CLK), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_REF_CLK), S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_MDIO), S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_CRS), S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_COL), --=20 2.45.2 From nobody Thu Nov 28 15:34:28 2024 Received: from EUR05-AM6-obe.outbound.protection.outlook.com (mail-am6eur05on2047.outbound.protection.outlook.com [40.107.22.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54E071917E3; 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charset="utf-8" The SIUL2 hardware module is also integrated into the S32G3 SoC. Add another compatible for it. Signed-off-by: Andrei Stefanescu --- .../bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctr= l.yaml index a24286e4def6..454773e7aa07 100644 --- a/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml @@ -25,8 +25,14 @@ description: | =20 properties: compatible: - enum: - - nxp,s32g2-siul2-pinctrl + oneOf: + - description: for S32G2 SoCs + items: + - const: nxp,s32g2-siul2-pinctrl + - description: for S32G3 SoCs + items: + - const: nxp,s32g3-siul2-pinctrl + - const: nxp,s32g2-siul2-pinctrl =20 reg: description: | --=20 2.45.2 From nobody Thu Nov 28 15:34:28 2024 Received: from EUR05-AM6-obe.outbound.protection.outlook.com (mail-am6eur05on2047.outbound.protection.outlook.com [40.107.22.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38324191F8D; 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charset="utf-8" Add the newly introduced S32G3 compatible for the pinctrl node. Currently, it will fall back to the S32G2 compatible. Signed-off-by: Andrei Stefanescu Reviewed-by: Matthias Brugger --- arch/arm64/boot/dts/freescale/s32g3.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts= /freescale/s32g3.dtsi index b4226a9143c8..f6aafe44c9d7 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -172,7 +172,8 @@ soc@0 { ranges =3D <0 0 0 0x80000000>; =20 pinctrl: pinctrl@4009c240 { - compatible =3D "nxp,s32g2-siul2-pinctrl"; + compatible =3D "nxp,s32g3-siul2-pinctrl", + "nxp,s32g2-siul2-pinctrl"; /* MSCR0-MSCR101 registers on siul2_0 */ reg =3D <0x4009c240 0x198>, /* MSCR112-MSCR122 registers on siul2_1 */ --=20 2.45.2