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charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20240930112131epcas5p1babeb8b867f8e4e0ec82a496c3d41aa9 References: <20240930111859.22264-1-v.pavani@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Use samsung CCF function which registers multiple clock providers using single function call samsung_cmu_register_clocks(). Signed-off-by: Varada Pavani --- drivers/clk/samsung/clk-exynos4.c | 78 +++++++++++++++++-------------- 1 file changed, 44 insertions(+), 34 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-ex= ynos4.c index 28945b6b0ee1..31cb85330549 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -1269,6 +1269,45 @@ static const struct samsung_cpu_clock exynos4412_cpu= _clks[] __initconst =3D { CPUCLK_LAYOUT_E4210, e4412_armclk_d), }; =20 +static const struct samsung_cmu_info cmu_info_exynos4 __initconst =3D { + .mux_clks =3D exynos4_mux_clks, + .nr_mux_clks =3D ARRAY_SIZE(exynos4_mux_clks), + .div_clks =3D exynos4_div_clks, + .nr_div_clks =3D ARRAY_SIZE(exynos4_div_clks), + .gate_clks =3D exynos4_gate_clks, + .nr_gate_clks =3D ARRAY_SIZE(exynos4_gate_clks), + .fixed_factor_clks =3D exynos4_fixed_factor_clks, + .nr_fixed_factor_clks =3D ARRAY_SIZE(exynos4_fixed_factor_clks), + .fixed_clks =3D exynos4_fixed_rate_clks, + .nr_fixed_clks =3D ARRAY_SIZE(exynos4_fixed_rate_clks), +}; + +static const struct samsung_cmu_info cmu_info_exynos4210 __initconst =3D { + .mux_clks =3D exynos4210_mux_clks, + .nr_mux_clks =3D ARRAY_SIZE(exynos4210_mux_clks), + .div_clks =3D exynos4210_div_clks, + .nr_div_clks =3D ARRAY_SIZE(exynos4210_div_clks), + .gate_clks =3D exynos4210_gate_clks, + .nr_gate_clks =3D ARRAY_SIZE(exynos4210_gate_clks), + .fixed_factor_clks =3D exynos4210_fixed_factor_clks, + .nr_fixed_factor_clks =3D ARRAY_SIZE(exynos4210_fixed_factor_clks), + .fixed_clks =3D exynos4210_fixed_rate_clks, + .nr_fixed_clks =3D ARRAY_SIZE(exynos4210_fixed_rate_clks), + .cpu_clks =3D exynos4210_cpu_clks, + .nr_cpu_clks =3D ARRAY_SIZE(exynos4210_cpu_clks), +}; + +static const struct samsung_cmu_info cmu_info_exynos4x12 __initconst =3D { + .mux_clks =3D exynos4x12_mux_clks, + .nr_mux_clks =3D ARRAY_SIZE(exynos4x12_mux_clks), + .div_clks =3D exynos4x12_div_clks, + .nr_div_clks =3D ARRAY_SIZE(exynos4x12_div_clks), + .gate_clks =3D exynos4x12_gate_clks, + .nr_gate_clks =3D ARRAY_SIZE(exynos4x12_gate_clks), + .fixed_factor_clks =3D exynos4x12_fixed_factor_clks, + .nr_fixed_factor_clks =3D ARRAY_SIZE(exynos4x12_fixed_factor_clks), +}; + /* register exynos4 clocks */ static void __init exynos4_clk_init(struct device_node *np, enum exynos4_soc soc) @@ -1322,41 +1361,12 @@ static void __init exynos4_clk_init(struct device_n= ode *np, ARRAY_SIZE(exynos4x12_plls)); } =20 - samsung_clk_register_fixed_rate(ctx, exynos4_fixed_rate_clks, - ARRAY_SIZE(exynos4_fixed_rate_clks)); - samsung_clk_register_mux(ctx, exynos4_mux_clks, - ARRAY_SIZE(exynos4_mux_clks)); - samsung_clk_register_div(ctx, exynos4_div_clks, - ARRAY_SIZE(exynos4_div_clks)); - samsung_clk_register_gate(ctx, exynos4_gate_clks, - ARRAY_SIZE(exynos4_gate_clks)); - samsung_clk_register_fixed_factor(ctx, exynos4_fixed_factor_clks, - ARRAY_SIZE(exynos4_fixed_factor_clks)); + samsung_cmu_register_clocks(ctx, &cmu_info_exynos4); =20 - if (exynos4_soc =3D=3D EXYNOS4210) { - samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks, - ARRAY_SIZE(exynos4210_fixed_rate_clks)); - samsung_clk_register_mux(ctx, exynos4210_mux_clks, - ARRAY_SIZE(exynos4210_mux_clks)); - samsung_clk_register_div(ctx, exynos4210_div_clks, - ARRAY_SIZE(exynos4210_div_clks)); - samsung_clk_register_gate(ctx, exynos4210_gate_clks, - ARRAY_SIZE(exynos4210_gate_clks)); - samsung_clk_register_fixed_factor(ctx, - exynos4210_fixed_factor_clks, - ARRAY_SIZE(exynos4210_fixed_factor_clks)); - samsung_clk_register_cpu(ctx, exynos4210_cpu_clks, - ARRAY_SIZE(exynos4210_cpu_clks)); - } else { - samsung_clk_register_mux(ctx, exynos4x12_mux_clks, - ARRAY_SIZE(exynos4x12_mux_clks)); - samsung_clk_register_div(ctx, exynos4x12_div_clks, - ARRAY_SIZE(exynos4x12_div_clks)); - samsung_clk_register_gate(ctx, exynos4x12_gate_clks, - ARRAY_SIZE(exynos4x12_gate_clks)); - samsung_clk_register_fixed_factor(ctx, - exynos4x12_fixed_factor_clks, - ARRAY_SIZE(exynos4x12_fixed_factor_clks)); + if (exynos4_soc =3D=3D EXYNOS4210) + samsung_cmu_register_clocks(ctx, &cmu_info_exynos4210); + else { + samsung_cmu_register_clocks(ctx, &cmu_info_exynos4x12); if (soc =3D=3D EXYNOS4412) samsung_clk_register_cpu(ctx, exynos4412_cpu_clks, ARRAY_SIZE(exynos4412_cpu_clks)); --=20 2.17.1 From nobody Thu Nov 28 15:46:15 2024 Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D9371917C9 for ; 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Mon, 30 Sep 2024 20:21:35 +0900 (KST) Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20240930112133epsmtip2aabb8e0f2086f34c47bdb457a284a90e~6AbcoJIpt3034630346epsmtip2V; Mon, 30 Sep 2024 11:21:33 +0000 (GMT) From: Varada Pavani To: krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, mturquette@baylibre.com, sboyd@kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: aswani.reddy@samsung.com, pankaj.dubey@samsung.com, gost.dev@samsung.com, Varada Pavani , stable@vger.kernel.org Subject: [PATCH 2/2] clk: samsung: Fixes PLL locktime for PLL142XX used on FSD platfom Date: Mon, 30 Sep 2024 16:48:59 +0530 Message-Id: <20240930111859.22264-3-v.pavani@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240930111859.22264-1-v.pavani@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupkk+LIzCtJLcpLzFFi42LZdlhTQ9dg+q80g+V9ahYP5m1jszi0eSu7 xfUvz1ktbh7YyWRx/vwGdotNj6+xWnzsucdqcXnXHDaLGef3MVlcPOVqsWjrF3aLw2/aWS3+ XdvIYrFg4yNGiw29r9gd+D3e32hl99i0qpPNY/OSeo++LasYPT5vkgtgjcq2yUhNTEktUkjN S85PycxLt1XyDo53jjc1MzDUNbS0MFdSyEvMTbVVcvEJ0HXLzAE6VkmhLDGnFCgUkFhcrKRv Z1OUX1qSqpCRX1xiq5RakJJTYFKgV5yYW1yal66Xl1piZWhgYGQKVJiQnfHl8SK2gs2cFc8v 9rM1MD5i72Lk5JAQMJG4ePIPWxcjF4eQwB5GidP/rrBAOJ8YJVauW8kI4XxjlOjY9ZQVpmXl hEusEIm9jBKvn02HamllkpjXsh2sik1AS2L11OVgVSICfUwSd09MYAJxmAX6GCVa2p6DrRcW iJDo6n4BZrMIqErcWXWADcTmFbCUuHnjNdSJ8hKrNxxgBrE5BawkLs35ww4ySEKgkUNi/vZX UEe5SOw8fJkRwhaWeHV8C1SzlMTL/jYgmwPITpZo/8QNEc6RuLR7FROEbS9x4MocFpASZgFN ifW79CHCshJTT60DK2EW4JPo/f0EqpxXYsc8GFtJYueOCVC2hMTT1WvYIGwPiXmT9kCDqJdR YuGP1UwTGOVmIaxYwMi4ilEqtaA4Nz012bTAUDcvtRweccn5uZsYwWlSK2AH4+oNf/UOMTJx MB5ilOBgVhLhvXfoZ5oQb0piZVVqUX58UWlOavEhRlNgAE5klhJNzgcm6rySeEMTSwMTMzMz E0tjM0Mlcd7XrXNThATSE0tSs1NTC1KLYPqYODilGpgqn71W/OJoHKh6prdgXdsdPUHrZcnM M49wse0orBYJyautMjpXq2bxtOSIq0/ytk1ybSz+OXK/xAqnlKtUrLrxKMcl/tvxo5tyLjiL f533K3TuEnXLO/WfXJanaUef+bAysnPb4tc5F6b21VitvXFLoOq5wdnbb1Suv5i84tMPy7SX qmkGTkECvvOfGTzZde/N88kVP5xPlR2f/eNlite8huz7XX+WtKkvmGE6Vfuw0+uD168zr+uK X7t1DXPJhznFmj8rDnzcs0NCf9mMbQfeH5v9sT5+vQPf0gUXpmk2KK8+nxy3ryiFSeSoyFe/ O0e6LuWeFtyrYe0m1pf1pndjcmp50Ow9DwJK77rn+LHFKLEUZyQaajEXFScCAI7CFkccBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrLLMWRmVeSWpSXmKPExsWy7bCSvO7+zl9pBg9nCFg8mLeNzeLQ5q3s Fte/PGe1uHlgJ5PF+fMb2C02Pb7GavGx5x6rxeVdc9gsZpzfx2Rx8ZSrxaKtX9gtDr9pZ7X4 d20ji8WCjY8YLTb0vmJ34Pd4f6OV3WPTqk42j81L6j36tqxi9Pi8SS6ANYrLJiU1J7MstUjf LoEr48vjRWwFmzkrnl/sZ2tgfMTexcjJISFgIrFywiXWLkYuDiGB3YwS3y98YYVISEjs/NbK DGELS6z895wdoqiZSeLi9xVg3WwCWhKrpy4H6xYRmMUkMXfJBxYQh1lgEqPEuj/ngao4OIQF wiRWv+cCaWARUJW4s+oAG4jNK2ApcfPGa6gz5CVWbzgAto1TwEri0pw/YK1CIDUvsyYw8i1g ZFjFKJlaUJybnltsWGCUl1quV5yYW1yal66XnJ+7iREcwlpaOxj3rPqgd4iRiYPxEKMEB7OS CO+9Qz/ThHhTEiurUovy44tKc1KLDzFKc7AoifN+e92bIiSQnliSmp2aWpBaBJNl4uCUamBS CC6Yv2LqRpX8CfOMj/xPnmEw+3/K383BnQYelh8+3ur5u2DOnc9xlRLLZia73e/xMerSO3A1 zXfK9pmTfwSmTe279iT+BWPWbS99XeE7hfGLfpw1S+3WniedrTbtzrmOCq0vezdzS3FKCKre 2mLd+r9Qc7mZ1wTT+sVfrl+t4dGZutlmb4rVkbdvl99LTPlqq8Kw5rl95cyKYyKvuc8sXPuq fF1CBedU8X9b3S96d04Sbnu5TubdgctbVr7R7oze7fak54fli9cBLydf14/4o7y5ztbXMv58 4iSPyyFvdcpWc5wxmLWqdgdbaJTSBPsjq5V1CqMLnHJuTp+x2qpVqfEyY83yW/KBPdN7Vq9p VWIpzkg01GIuKk4EAKHIgknQAgAA X-CMS-MailID: 20240930112135epcas5p2175ec81bb609da5b166d47341ece2f67 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20240930112135epcas5p2175ec81bb609da5b166d47341ece2f67 References: <20240930111859.22264-1-v.pavani@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Add PLL locktime for PLL142XX controller. Fixes: 4f346005aaed ("clk: samsung: fsd: Add initial clock support") Cc: stable@vger.kernel.org Signed-off-by: Varada Pavani --- drivers/clk/samsung/clk-pll.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 4be879ab917e..d4c5ae20de4f 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -206,6 +206,7 @@ static const struct clk_ops samsung_pll3000_clk_ops =3D= { */ /* Maximum lock time can be 270 * PDIV cycles */ #define PLL35XX_LOCK_FACTOR (270) +#define PLL142XX_LOCK_FACTOR (150) =20 #define PLL35XX_MDIV_MASK (0x3FF) #define PLL35XX_PDIV_MASK (0x3F) @@ -272,7 +273,11 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw,= unsigned long drate, } =20 /* Set PLL lock time. */ - writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR, + if (pll->type =3D=3D pll_142xx) + writel_relaxed(rate->pdiv * PLL142XX_LOCK_FACTOR, + pll->lock_reg); + else + writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR, pll->lock_reg); =20 /* Change PLL PMS values */ --=20 2.17.1