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charset="utf-8" Add a panel-timing node to panel-lvds node to override any fixed display modes written in a panel driver. This way, 74.25MHz clock frequency specified in panel-timing node may accommodate 7-fold 519.75MHz "media_ldb" clock which is derived from 1.0395GHz "video_pll1" clock. This should suppress this LDB driver warning: [ 17.923709] fsl-ldb 32ec0000.blk-ctrl:bridge@5c: Configured LDB clock (7= 2400000 Hz) does not match requested LVDS clock: 506800000 Hz This also makes the display mode used by the panel pass mode validation against pixel clock rate and "media_ldb" clock rate in a certain display driver. Fixes: 326d86e197fc ("arm64: dts: imx8mp-phyboard-pollux-rdk: add etml pane= l support") Signed-off-by: Liu Ying --- .../dts/freescale/imx8mp-phyboard-pollux-rdk.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b= /arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts index 50debe821c42..20cb5363cccb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts @@ -37,6 +37,21 @@ panel1_lvds: panel-lvds { backlight =3D <&backlight_lvds>; power-supply =3D <®_vcc_3v3_sw>; =20 + panel-timing { + clock-frequency =3D <74250000>; + hactive =3D <1280>; + vactive =3D <800>; + hfront-porch =3D <72>; + hback-porch =3D <86>; + hsync-len =3D <2>; + vfront-porch =3D <15>; + vback-porch =3D <21>; + vsync-len =3D <2>; + hsync-active =3D <0>; + vsync-active =3D <0>; + de-active =3D <1>; + }; + port { panel1_in: endpoint { remote-endpoint =3D <&ldb_lvds_ch1>; --=20 2.34.1