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[71.34.69.82]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71b26529d4bsm6630213b3a.158.2024.09.30.12.51.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Sep 2024 12:51:10 -0700 (PDT) From: Drew Fustini Date: Mon, 30 Sep 2024 12:50:53 -0700 Subject: [PATCH v3 3/8] riscv: dts: thead: Add TH1520 pin control nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240930-th1520-pinctrl-v3-3-32cea2bdbecb@tenstorrent.com> References: <20240930-th1520-pinctrl-v3-0-32cea2bdbecb@tenstorrent.com> In-Reply-To: <20240930-th1520-pinctrl-v3-0-32cea2bdbecb@tenstorrent.com> To: Drew Fustini , Guo Ren , Fu Wei , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Emil Renner Berthing , Thomas Bonnefille Cc: linux-riscv@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Drew Fustini X-Mailer: b4 0.14.1 From: Emil Renner Berthing Add nodes for pin controllers on the T-Head TH1520 RISC-V SoC. Tested-by: Thomas Bonnefille Signed-off-by: Emil Renner Berthing Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 4 ++++ .../boot/dts/thead/th1520-lichee-module-4a.dtsi | 4 ++++ arch/riscv/boot/dts/thead/th1520.dtsi | 27 ++++++++++++++++++= ++++ 3 files changed, 35 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/risc= v/boot/dts/thead/th1520-beaglev-ahead.dts index 497d961456f3..e88b4fce755e 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -45,6 +45,10 @@ &osc_32k { clock-frequency =3D <32768>; }; =20 +&aonsys_clk { + clock-frequency =3D <73728000>; +}; + &dmac0 { status =3D "okay"; }; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/= riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi index 78977bdbbe3d..bf1c639072b8 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -25,6 +25,10 @@ &osc_32k { clock-frequency =3D <32768>; }; =20 +&aonsys_clk { + clock-frequency =3D <73728000>; +}; + &dmac0 { status =3D "okay"; }; diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index 6992060e6a54..e4eda2a76595 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -216,6 +216,12 @@ osc_32k: 32k-oscillator { #clock-cells =3D <0>; }; =20 + aonsys_clk: aonsys-clk { + compatible =3D "fixed-clock"; + clock-output-names =3D "aonsys_clk"; + #clock-cells =3D <0>; + }; + soc { compatible =3D "simple-bus"; interrupt-parent =3D <&plic>; @@ -354,6 +360,13 @@ portd: gpio-controller@0 { }; }; =20 + padctrl1_apsys: pinctrl@ffe7f3c000 { + compatible =3D "thead,th1520-pinctrl"; + reg =3D <0xff 0xe7f3c000 0x0 0x1000>; + clocks =3D <&clk CLK_PADCTRL1>; + thead,pad-group =3D <2>; + }; + gpio0: gpio@ffec005000 { compatible =3D "snps,dw-apb-gpio"; reg =3D <0xff 0xec005000 0x0 0x1000>; @@ -392,6 +405,13 @@ portb: gpio-controller@0 { }; }; =20 + padctrl0_apsys: pinctrl@ffec007000 { + compatible =3D "thead,th1520-pinctrl"; + reg =3D <0xff 0xec007000 0x0 0x1000>; + clocks =3D <&clk CLK_PADCTRL0>; + thead,pad-group =3D <3>; + }; + uart2: serial@ffec010000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0xff 0xec010000 0x0 0x4000>; @@ -538,6 +558,13 @@ porte: gpio-controller@0 { }; }; =20 + padctrl_aosys: pinctrl@fffff4a000 { + compatible =3D "thead,th1520-pinctrl"; + reg =3D <0xff 0xfff4a000 0x0 0x2000>; + thead,pad-group =3D <1>; + clocks =3D <&aonsys_clk>; + }; + ao_gpio1: gpio@fffff52000 { compatible =3D "snps,dw-apb-gpio"; reg =3D <0xff 0xfff52000 0x0 0x1000>; --=20 2.34.1