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[71.34.69.82]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71b26529d4bsm6630213b3a.158.2024.09.30.12.51.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Sep 2024 12:51:08 -0700 (PDT) From: Drew Fustini Date: Mon, 30 Sep 2024 12:50:51 -0700 Subject: [PATCH v3 1/8] dt-bindings: pinctrl: Add thead,th1520-pinctrl bindings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240930-th1520-pinctrl-v3-1-32cea2bdbecb@tenstorrent.com> References: <20240930-th1520-pinctrl-v3-0-32cea2bdbecb@tenstorrent.com> In-Reply-To: <20240930-th1520-pinctrl-v3-0-32cea2bdbecb@tenstorrent.com> To: Drew Fustini , Guo Ren , Fu Wei , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Emil Renner Berthing , Thomas Bonnefille Cc: linux-riscv@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Drew Fustini X-Mailer: b4 0.14.1 From: Emil Renner Berthing Add bindings for the pin controllers on the T-Head TH1520 RISC-V SoC. Reviewed-by: Rob Herring (Arm) Tested-by: Thomas Bonnefille Signed-off-by: Emil Renner Berthing [dfustini: add thead,pad-group to select the pin controller instance] Signed-off-by: Drew Fustini --- .../bindings/pinctrl/thead,th1520-pinctrl.yaml | 176 +++++++++++++++++= ++++ MAINTAINERS | 1 + 2 files changed, 177 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl= .yaml b/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml new file mode 100644 index 000000000000..21f86740a63d --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml @@ -0,0 +1,176 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/thead,th1520-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-Head TH1520 SoC pin controller + +maintainers: + - Emil Renner Berthing + +description: | + Pinmux and pinconf controller in the T-Head TH1520 RISC-V SoC. + + The TH1520 has 3 groups of pads each controlled from different memory ra= nges. + Confusingly the memory ranges are named + PADCTRL_AOSYS -> PAD Group 1 + PADCTRL1_APSYS -> PAD Group 2 + PADCTRL0_APSYS -> PAD Group 3 + + Each pad can be muxed individually to up to 6 different functions. For m= ost + pads only a few of those 6 configurations are valid though, and a few pa= ds in + group 1 does not support muxing at all. + + Pinconf is fairly regular except for a few pads in group 1 that either c= an't + be configured or has some special functions. The rest have configurable = drive + strength, input enable, schmitt trigger, slew rate, pull-up and pull-dow= n in + addition to a special strong pull up. + + Certain pads in group 1 can be muxed to AUDIO_PA0 - AUDIO_PA30 functions= and + are then meant to be used by the audio co-processor. Each such pad can t= hen + be further muxed to either audio GPIO or one of 4 functions such as UART= , I2C + and I2S. If the audio pad is muxed to one of the 4 functions then pincon= f is + also configured in different registers. All of this is done from a diffe= rent + AUDIO_IOCTRL memory range and is left to the audio co-processor for now. + +properties: + compatible: + enum: + - thead,th1520-pinctrl + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + thead,pad-group: + description: | + Select the pad group that is associated with the pin controller inst= ance. + + Base Address Name Group + 0xFF_FFF4_A000 PADCTRL_AOSYS 1 + 0xFF_E7F3_C000 PADCTRL1_APSYS 2 + 0xFF_EC00_7000 PADCTRL0_APSYS 3 + + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3] + +required: + - compatible + - reg + - clocks + +patternProperties: + '-[0-9]+$': + type: object + additionalProperties: false + + patternProperties: + '-pins$': + type: object + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml# + - $ref: /schemas/pinctrl/pinmux-node.yaml# + + additionalProperties: false + + description: + A pinctrl node should contain at least one subnode describing one + or more pads and their associated pinmux and pinconf settings. + + properties: + pins: + description: List of pads that properties in the node apply to. + + function: + enum: [ gpio, pwm, uart, ir, i2c, spi, qspi, sdio, audio, i2s, + gmac0, gmac1, dpu0, dpu1, isp, hdmi, bootsel, debug, + clock, jtag, iso7816, efuse, reset ] + description: The mux function to select for the given pins. + + bias-disable: true + + bias-pull-up: + oneOf: + - type: boolean + description: Enable the regular 48kOhm pull-up + - enum: [ 2100, 48000 ] + description: Enable the strong 2.1kOhm pull-up or regular = 48kOhm pull-up + + bias-pull-down: + oneOf: + - type: boolean + - const: 44000 + description: Enable the regular 44kOhm pull-down + + drive-strength: + enum: [ 1, 2, 3, 5, 7, 8, 10, 12, 13, 15, 16, 18, 20, 21, 23, = 25 ] + description: Drive strength in mA + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + slew-rate: + maximum: 1 + + required: + - pins + +additionalProperties: false + +examples: + - | + padctrl0_apsys: pinctrl@ec007000 { + compatible =3D "thead,th1520-pinctrl"; + reg =3D <0xec007000 0x1000>; + clocks =3D <&apb_clk>; + thead,pad-group =3D <3>; + + uart0_pins: uart0-0 { + tx-pins { + pins =3D "UART0_TXD"; + function =3D "uart"; + bias-disable; + drive-strength =3D <3>; + input-disable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + + rx-pins { + pins =3D "UART0_RXD"; + function =3D "uart"; + bias-disable; + drive-strength =3D <1>; + input-enable; + input-schmitt-enable; + slew-rate =3D <0>; + }; + }; + }; + + padctrl1_apsys: pinctrl@e7f3c000 { + compatible =3D "thead,th1520-pinctrl"; + reg =3D <0xe7f3c000 0x1000>; + clocks =3D <&apb_clk>; + thead,pad-group =3D <2>; + + i2c5_pins: i2c5-0 { + i2c-pins { + pins =3D "QSPI1_CSN0", /* I2C5_SCL */ + "QSPI1_D0_MOSI"; /* I2C5_SDA */ + function =3D "i2c"; + bias-pull-up =3D <2100>; + drive-strength =3D <7>; + input-enable; + input-schmitt-enable; + slew-rate =3D <0>; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index c27f3190737f..dd74c9aa2009 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19942,6 +19942,7 @@ L: linux-riscv@lists.infradead.org S: Maintained T: git https://github.com/pdp7/linux.git F: Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml +F: Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml F: arch/riscv/boot/dts/thead/ F: drivers/clk/thead/clk-th1520-ap.c F: include/dt-bindings/clock/thead,th1520-clk-ap.h --=20 2.34.1