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[71.34.69.82]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71b264ba68dsm7267804b3a.57.2024.09.30.23.23.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Sep 2024 23:23:46 -0700 (PDT) From: Drew Fustini Date: Mon, 30 Sep 2024 23:23:25 -0700 Subject: [PATCH v3 2/3] net: stmmac: Add glue layer for T-HEAD TH1520 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240930-th1520-dwmac-v3-2-ae3e03c225ab@tenstorrent.com> References: <20240930-th1520-dwmac-v3-0-ae3e03c225ab@tenstorrent.com> In-Reply-To: <20240930-th1520-dwmac-v3-0-ae3e03c225ab@tenstorrent.com> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Jisheng Zhang , Maxime Coquelin , Emil Renner Berthing , Drew Fustini , Guo Ren , Fu Wei , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Drew Fustini Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org X-Mailer: b4 0.14.1 From: Jisheng Zhang Add dwmac glue driver to support the DesignWare-based GMAC controllers on the T-HEAD TH1520 SoC. Signed-off-by: Jisheng Zhang [esmil: rename plat->interface -> plat->mac_interface, use devm_stmmac_probe_config_dt()] Signed-off-by: Emil Renner Berthing [drew: convert from stmmac_dvr_probe() to devm_stmmac_pltfr_probe()] Signed-off-by: Drew Fustini --- MAINTAINERS | 1 + drivers/net/ethernet/stmicro/stmmac/Kconfig | 11 + drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c | 291 ++++++++++++++++++= ++++ 4 files changed, 304 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 9e50107efb37..1d24863c01df 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19946,6 +19946,7 @@ F: Documentation/devicetree/bindings/net/thead,th15= 20-gmac.yaml F: Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml F: arch/riscv/boot/dts/thead/ F: drivers/clk/thead/clk-th1520-ap.c +F: drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c F: drivers/pinctrl/pinctrl-th1520.c F: include/dt-bindings/clock/thead,th1520-clk-ap.h =20 diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethe= rnet/stmicro/stmmac/Kconfig index 05cc07b8f48c..82030adaf16e 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -228,6 +228,17 @@ config DWMAC_SUN8I stmmac device driver. This driver is used for H3/A83T/A64 EMAC ethernet controller. =20 +config DWMAC_THEAD + tristate "T-HEAD dwmac support" + depends on OF && (ARCH_THEAD || COMPILE_TEST) + select MFD_SYSCON + help + Support for ethernet controllers on T-HEAD RISC-V SoCs + + This selects the T-HEAD platform specific glue layer support for + the stmmac device driver. This driver is used for T-HEAD TH1520 + ethernet controller. + config DWMAC_IMX8 tristate "NXP IMX8 DWMAC support" default ARCH_MXC diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/eth= ernet/stmicro/stmmac/Makefile index c2f0e91f6bf8..d065634c6223 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_DWMAC_STI) +=3D dwmac-sti.o obj-$(CONFIG_DWMAC_STM32) +=3D dwmac-stm32.o obj-$(CONFIG_DWMAC_SUNXI) +=3D dwmac-sunxi.o obj-$(CONFIG_DWMAC_SUN8I) +=3D dwmac-sun8i.o +obj-$(CONFIG_DWMAC_THEAD) +=3D dwmac-thead.o obj-$(CONFIG_DWMAC_DWC_QOS_ETH) +=3D dwmac-dwc-qos-eth.o obj-$(CONFIG_DWMAC_INTEL_PLAT) +=3D dwmac-intel-plat.o obj-$(CONFIG_DWMAC_LOONGSON1) +=3D dwmac-loongson1.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c b/drivers/ne= t/ethernet/stmicro/stmmac/dwmac-thead.c new file mode 100644 index 000000000000..f2f94539c0d2 --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c @@ -0,0 +1,291 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * T-HEAD DWMAC platform driver + * + * Copyright (C) 2021 Alibaba Group Holding Limited. + * Copyright (C) 2023 Jisheng Zhang + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "stmmac_platform.h" + +#define GMAC_CLK_EN 0x00 +#define GMAC_TX_CLK_EN BIT(1) +#define GMAC_TX_CLK_N_EN BIT(2) +#define GMAC_TX_CLK_OUT_EN BIT(3) +#define GMAC_RX_CLK_EN BIT(4) +#define GMAC_RX_CLK_N_EN BIT(5) +#define GMAC_EPHY_REF_CLK_EN BIT(6) +#define GMAC_RXCLK_DELAY_CTRL 0x04 +#define GMAC_RXCLK_BYPASS BIT(15) +#define GMAC_RXCLK_INVERT BIT(14) +#define GMAC_RXCLK_DELAY_MASK GENMASK(4, 0) +#define GMAC_RXCLK_DELAY_VAL(x) FIELD_PREP(GMAC_RXCLK_DELAY_MASK, (x)) +#define GMAC_TXCLK_DELAY_CTRL 0x08 +#define GMAC_TXCLK_BYPASS BIT(15) +#define GMAC_TXCLK_INVERT BIT(14) +#define GMAC_TXCLK_DELAY_MASK GENMASK(4, 0) +#define GMAC_TXCLK_DELAY_VAL(x) FIELD_PREP(GMAC_RXCLK_DELAY_MASK, (x)) +#define GMAC_PLLCLK_DIV 0x0c +#define GMAC_PLLCLK_DIV_EN BIT(31) +#define GMAC_PLLCLK_DIV_MASK GENMASK(7, 0) +#define GMAC_PLLCLK_DIV_NUM(x) FIELD_PREP(GMAC_PLLCLK_DIV_MASK, (x)) +#define GMAC_GTXCLK_SEL 0x18 +#define GMAC_GTXCLK_SEL_PLL BIT(0) +#define GMAC_INTF_CTRL 0x1c +#define PHY_INTF_MASK BIT(0) +#define PHY_INTF_RGMII FIELD_PREP(PHY_INTF_MASK, 1) +#define PHY_INTF_MII_GMII FIELD_PREP(PHY_INTF_MASK, 0) +#define GMAC_TXCLK_OEN 0x20 +#define TXCLK_DIR_MASK BIT(0) +#define TXCLK_DIR_OUTPUT FIELD_PREP(TXCLK_DIR_MASK, 0) +#define TXCLK_DIR_INPUT FIELD_PREP(TXCLK_DIR_MASK, 1) + +#define GMAC_GMII_RGMII_RATE 125000000 +#define GMAC_MII_RATE 25000000 + +static const struct regmap_config regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, +}; + +struct thead_dwmac { + struct plat_stmmacenet_data *plat; + struct regmap *apb_regmap; + struct device *dev; +}; + +static int thead_dwmac_set_phy_if(struct plat_stmmacenet_data *plat) +{ + struct thead_dwmac *dwmac =3D plat->bsp_priv; + u32 phyif; + + switch (plat->mac_interface) { + case PHY_INTERFACE_MODE_MII: + phyif =3D PHY_INTF_MII_GMII; + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + phyif =3D PHY_INTF_RGMII; + break; + default: + dev_err(dwmac->dev, "unsupported phy interface %d\n", + plat->mac_interface); + return -EINVAL; + }; + + return regmap_write(dwmac->apb_regmap, GMAC_INTF_CTRL, phyif); +} + +static int thead_dwmac_set_txclk_dir(struct plat_stmmacenet_data *plat) +{ + struct thead_dwmac *dwmac =3D plat->bsp_priv; + u32 txclk_dir; + + switch (plat->mac_interface) { + case PHY_INTERFACE_MODE_MII: + txclk_dir =3D TXCLK_DIR_INPUT; + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + txclk_dir =3D TXCLK_DIR_OUTPUT; + break; + default: + dev_err(dwmac->dev, "unsupported phy interface %d\n", + plat->mac_interface); + return -EINVAL; + }; + + return regmap_write(dwmac->apb_regmap, GMAC_TXCLK_OEN, txclk_dir); +} + +static void thead_dwmac_fix_speed(void *priv, unsigned int speed, unsigned= int mode) +{ + struct plat_stmmacenet_data *plat; + struct thead_dwmac *dwmac =3D priv; + unsigned long rate; + u32 div; + + plat =3D dwmac->plat; + + switch (plat->mac_interface) { + /* For MII, rxc/txc is provided by phy */ + case PHY_INTERFACE_MODE_MII: + return; + + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + rate =3D clk_get_rate(plat->stmmac_clk); + if (!rate || rate % GMAC_GMII_RGMII_RATE !=3D 0 || + rate % GMAC_MII_RATE !=3D 0) { + dev_err(dwmac->dev, "invalid gmac rate %ld\n", rate); + return; + } + + regmap_update_bits(dwmac->apb_regmap, GMAC_PLLCLK_DIV, GMAC_PLLCLK_DIV_E= N, 0); + + switch (speed) { + case SPEED_1000: + div =3D rate / GMAC_GMII_RGMII_RATE; + break; + case SPEED_100: + div =3D rate / GMAC_MII_RATE; + break; + case SPEED_10: + div =3D rate * 10 / GMAC_MII_RATE; + break; + default: + dev_err(dwmac->dev, "invalid speed %u\n", speed); + return; + } + regmap_update_bits(dwmac->apb_regmap, GMAC_PLLCLK_DIV, + GMAC_PLLCLK_DIV_MASK, GMAC_PLLCLK_DIV_NUM(div)); + + regmap_update_bits(dwmac->apb_regmap, GMAC_PLLCLK_DIV, + GMAC_PLLCLK_DIV_EN, GMAC_PLLCLK_DIV_EN); + break; + default: + dev_err(dwmac->dev, "unsupported phy interface %d\n", + plat->mac_interface); + return; + } +} + +static int thead_dwmac_enable_clk(struct plat_stmmacenet_data *plat) +{ + struct thead_dwmac *dwmac =3D plat->bsp_priv; + int err; + u32 reg; + + switch (plat->mac_interface) { + case PHY_INTERFACE_MODE_MII: + reg =3D GMAC_RX_CLK_EN | GMAC_TX_CLK_EN; + break; + + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + /* use pll */ + err =3D regmap_write(dwmac->apb_regmap, GMAC_GTXCLK_SEL, GMAC_GTXCLK_SEL= _PLL); + if (err) + return dev_err_probe(dwmac->dev, err, + "failed to set phy interface\n"); + + reg =3D GMAC_TX_CLK_EN | GMAC_TX_CLK_N_EN | GMAC_TX_CLK_OUT_EN | + GMAC_RX_CLK_EN | GMAC_RX_CLK_N_EN; + break; + + default: + dev_err(dwmac->dev, "unsupported phy interface %d\n", + plat->mac_interface); + return -EINVAL; + } + + return regmap_write(dwmac->apb_regmap, GMAC_CLK_EN, reg); +} + +static int thead_dwmac_init(struct platform_device *pdev, void *priv) +{ + struct thead_dwmac *dwmac =3D priv; + int ret; + + ret =3D thead_dwmac_set_phy_if(dwmac->plat); + if (ret) + return ret; + + ret =3D thead_dwmac_set_txclk_dir(dwmac->plat); + if (ret) + return ret; + + ret =3D regmap_write(dwmac->apb_regmap, GMAC_RXCLK_DELAY_CTRL, + GMAC_RXCLK_DELAY_VAL(0)); + if (ret) + return dev_err_probe(dwmac->dev, ret, + "failed to set GMAC RX clock delay\n"); + + ret =3D regmap_write(dwmac->apb_regmap, GMAC_TXCLK_DELAY_CTRL, + GMAC_TXCLK_DELAY_VAL(0)); + if (ret) + return dev_err_probe(dwmac->dev, ret, + "failed to set GMAC TX clock delay\n"); + + return thead_dwmac_enable_clk(dwmac->plat); +} + +static int thead_dwmac_probe(struct platform_device *pdev) +{ + struct stmmac_resources stmmac_res; + struct plat_stmmacenet_data *plat; + struct thead_dwmac *dwmac; + void __iomem *apb; + int ret; + + ret =3D stmmac_get_platform_resources(pdev, &stmmac_res); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "failed to get resources\n"); + + plat =3D devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); + if (IS_ERR(plat)) + return dev_err_probe(&pdev->dev, PTR_ERR(plat), + "dt configuration failed\n"); + + dwmac =3D devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); + if (!dwmac) + return -ENOMEM; + + apb =3D devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(apb)) + return dev_err_probe(&pdev->dev, PTR_ERR(apb), + "Failed to remap gmac apb registers\n"); + + dwmac->apb_regmap =3D devm_regmap_init_mmio(&pdev->dev, apb, ®map_conf= ig); + if (IS_ERR(dwmac->apb_regmap)) + return dev_err_probe(&pdev->dev, PTR_ERR(dwmac->apb_regmap), + "Failed to access gmac apb registers\n"); + + dwmac->dev =3D &pdev->dev; + dwmac->plat =3D plat; + plat->bsp_priv =3D dwmac; + plat->fix_mac_speed =3D thead_dwmac_fix_speed; + plat->init =3D thead_dwmac_init; + + return devm_stmmac_pltfr_probe(pdev, plat, &stmmac_res); +} + +static const struct of_device_id thead_dwmac_match[] =3D { + { .compatible =3D "thead,th1520-gmac" }, + { } +}; +MODULE_DEVICE_TABLE(of, thead_dwmac_match); + +static struct platform_driver thead_dwmac_driver =3D { + .probe =3D thead_dwmac_probe, + .driver =3D { + .name =3D "thead-dwmac", + .pm =3D &stmmac_pltfr_pm_ops, + .of_match_table =3D thead_dwmac_match, + }, +}; +module_platform_driver(thead_dwmac_driver); + +MODULE_AUTHOR("Jisheng Zhang "); +MODULE_AUTHOR("Drew Fustini "); +MODULE_DESCRIPTION("T-HEAD DWMAC platform driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1