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[95.250.55.22]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5c88245ea57sm4507540a12.55.2024.09.30.06.52.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Sep 2024 06:52:58 -0700 (PDT) From: Antonino Maniscalco Date: Mon, 30 Sep 2024 15:52:46 +0200 Subject: [PATCH v7 11/12] drm/msm/a6xx: Enable preemption for a750 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240930-preemption-a750-t-v7-11-47803c7a5a64@gmail.com> References: <20240930-preemption-a750-t-v7-0-47803c7a5a64@gmail.com> In-Reply-To: <20240930-preemption-a750-t-v7-0-47803c7a5a64@gmail.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Jonathan Corbet Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Antonino Maniscalco , Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727704357; l=6298; i=antomani103@gmail.com; s=20240815; h=from:subject:message-id; bh=v6B4qmUJBsuB41vVTIX8n9r0BxOexKUVJScDHt92rI8=; b=IU2tkVpM6i1rJVydvzIOhaHq4YWV4yREzGkTdNK9qBK2DBmHQq+nG/St5qwljs4dn9Z5c4kH/ OmAx7svbP+UBYcjtvG66FXDUB4tVBOascpk7p8lyKPSad7O7mvpclxn X-Developer-Key: i=antomani103@gmail.com; a=ed25519; pk=0zicFb38tVla+iHRo4kWpOMsmtUrpGBEa7LkFF81lyY= Initialize with 4 rings to enable preemption. For now only on a750 as other targets require testing. Add the "preemption_enabled" module parameter to override this for other a7xx targets. Tested-by: Rob Clark Tested-by: Neil Armstrong # on SM8650-QRD Tested-by: Neil Armstrong # on SM8550-QRD Tested-by: Neil Armstrong # on SM8450-HDK Signed-off-by: Antonino Maniscalco --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 12 ++++++++---- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +++++- drivers/gpu/drm/msm/adreno/adreno_device.c | 4 ++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + drivers/gpu/drm/msm/msm_submitqueue.c | 6 +++++- 5 files changed, 23 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/ms= m/adreno/a6xx_catalog.c index e4d271fa89cc66f188be04206e267fabd83cca83..1c8b31627eb68bff406e7099583= 8e418331449ef 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -1204,7 +1204,8 @@ static const struct adreno_info a7xx_gpus[] =3D { .gmem =3D SZ_2M, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, + ADRENO_QUIRK_HAS_HW_APRIV | + ADRENO_QUIRK_PREEMPTION, .init =3D a6xx_gpu_init, .zapfw =3D "a730_zap.mdt", .a6xx =3D &(const struct a6xx_info) { @@ -1224,7 +1225,8 @@ static const struct adreno_info a7xx_gpus[] =3D { .gmem =3D 3 * SZ_1M, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, + ADRENO_QUIRK_HAS_HW_APRIV | + ADRENO_QUIRK_PREEMPTION, .init =3D a6xx_gpu_init, .zapfw =3D "a740_zap.mdt", .a6xx =3D &(const struct a6xx_info) { @@ -1245,7 +1247,8 @@ static const struct adreno_info a7xx_gpus[] =3D { .gmem =3D 3 * SZ_1M, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, + ADRENO_QUIRK_HAS_HW_APRIV | + ADRENO_QUIRK_PREEMPTION, .init =3D a6xx_gpu_init, .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a740_hwcg, @@ -1265,7 +1268,8 @@ static const struct adreno_info a7xx_gpus[] =3D { .gmem =3D 3 * SZ_1M, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, + ADRENO_QUIRK_HAS_HW_APRIV | + ADRENO_QUIRK_PREEMPTION, .init =3D a6xx_gpu_init, .zapfw =3D "gen70900_zap.mbn", .a6xx =3D &(const struct a6xx_info) { diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 2f7c93e74e097a78510700d2c6607d052cbdda66..dca9d011f09e741784ac6dc31b6= 1841149acbae2 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2439,6 +2439,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) struct a6xx_gpu *a6xx_gpu; struct adreno_gpu *adreno_gpu; struct msm_gpu *gpu; + extern int enable_preemption; bool is_a7xx; int ret; =20 @@ -2477,7 +2478,10 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) return ERR_PTR(ret); } =20 - if (is_a7xx) + if ((enable_preemption =3D=3D 1) || (enable_preemption =3D=3D -1 && + (config->info->quirks & ADRENO_QUIRK_PREEMPTION))) + ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 4); + else if (is_a7xx) ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 1); else if (adreno_has_gmu_wrapper(adreno_gpu)) ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_gmuwrapper, 1); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/m= sm/adreno/adreno_device.c index cfc74a9e2646d3de76a06bd67457d69afa49e309..9ffe91920fbfb4841b28aabec9f= bde94539fdd83 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -20,6 +20,10 @@ bool allow_vram_carveout =3D false; MODULE_PARM_DESC(allow_vram_carveout, "Allow using VRAM Carveout, in place= of IOMMU"); module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600); =20 +int enable_preemption =3D -1; +MODULE_PARM_DESC(enable_preemption, "Enable preemption (A7xx only) (1=3Don= , 0=3Ddisable, -1=3Dauto (default))"); +module_param(enable_preemption, int, 0600); + extern const struct adreno_gpulist a2xx_gpulist; extern const struct adreno_gpulist a3xx_gpulist; extern const struct adreno_gpulist a4xx_gpulist; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index 2d8eef6c668b0da246edceba0c5d92041ea9a35b..30c6b949d0b197fea130c9b2b69= c9362c1527737 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -56,6 +56,7 @@ enum adreno_family { #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2) #define ADRENO_QUIRK_HAS_HW_APRIV BIT(3) #define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4) +#define ADRENO_QUIRK_PREEMPTION BIT(5) =20 /* Helper for formating the chip_id in the way that userspace tools like * crashdec expect. diff --git a/drivers/gpu/drm/msm/msm_submitqueue.c b/drivers/gpu/drm/msm/ms= m_submitqueue.c index 9b3ffca3f3b471f509918edd4a2fdb0f80dfeb06..2fc3eaf81f4461990d48065f67b= f5477787708e9 100644 --- a/drivers/gpu/drm/msm/msm_submitqueue.c +++ b/drivers/gpu/drm/msm/msm_submitqueue.c @@ -161,6 +161,8 @@ int msm_submitqueue_create(struct drm_device *drm, stru= ct msm_file_private *ctx, struct msm_drm_private *priv =3D drm->dev_private; struct msm_gpu_submitqueue *queue; enum drm_sched_priority sched_prio; + extern int enable_preemption; + bool preemption_supported; unsigned ring_nr; int ret; =20 @@ -170,7 +172,9 @@ int msm_submitqueue_create(struct drm_device *drm, stru= ct msm_file_private *ctx, if (!priv->gpu) return -ENODEV; =20 - if (flags & MSM_SUBMITQUEUE_ALLOW_PREEMPT && priv->gpu->nr_rings =3D=3D 1) + preemption_supported =3D priv->gpu->nr_rings =3D=3D 1 && enable_preemptio= n !=3D 0; + + if (flags & MSM_SUBMITQUEUE_ALLOW_PREEMPT && preemption_supported) return -EINVAL; =20 ret =3D msm_gpu_convert_priority(priv->gpu, prio, &ring_nr, &sched_prio); --=20 2.46.1