From nobody Thu Nov 28 18:36:44 2024 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35B6A198831; Mon, 30 Sep 2024 18:36:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727721371; cv=none; b=skKvpXvUfPBSNwyrdlTmaB542wlSiG51ZUKkciQHn+TOIIgom7jcEOdR0RIsv8OnC3jkRzZWAjWlxGf3E5mY1jV7SnndvErOOiYMEuhPUybzl/Bp6GdTtVRzbiRmuzVJFhM9K7L+S2fhLMnnbOxQzxfqhvMSU1lIFcND2fruqUQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727721371; c=relaxed/simple; bh=Z5SC+6UDFlEj9PHLJ3evpz3WzgUy6CqfrBnaVebiCTc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=p42knO7W59HPfIPoniGlvGPniDtQ7LzpmTtjg81VB8KIOMfNYnnPvi7v6LXAB86XIA/NpgER485nIV01+BMcL/hmiCrNpuz1aXS3z+3EYFqWx8tpE8GIsMECygBfVR9uk4Wf+BjbzJtaCar/KyBK2YgfOLiLJhYoOCf7Qdv8zrg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org; spf=pass smtp.mailfrom=mainlining.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=aHv9tg9M; arc=none smtp.client-ip=5.75.144.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mainlining.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="aHv9tg9M" Received: from [192.168.1.130] (51B6DC6E.dsl.pool.telekom.hu [81.182.220.110]) by mail.mainlining.org (Postfix) with ESMTPSA id 7627BE4524; Mon, 30 Sep 2024 18:36:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mainlining.org; s=psm; t=1727721361; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=QdjOmboCzzxr+wO0FSFKNI0m2TFQvcd1auTusDJIIMk=; b=aHv9tg9MPuMq6Uqm+qT451hTxZRzU3IiTbVvncGfLsK1RwrT/RTajy/ZrcYrh4mRKUDaeu Ik0ssrFURPImF5zPvHApkuKCP+5xjS0nL0Raj4pK2usDpNpi3WSEevpgx2zTil9aC8tkAV GVJZg0foP0L06So1lPvMbNPKfTdDgTZTZ42ZjHFaVFDP7rk9II0/qFM3ECkR1ALrOmrjeA TxegEJG1YBdMBN1EcnhxqhlHWkbnRuil/19TMeTwqEghEQ6aGzXFCBUkmlpdULM+egXo4L 6YRhXDxw+i/1zBOUibGKgzLj/oNsUSyhTgtaS58y0MKr7I8cRI6eb56uXKRGnw== From: =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= Date: Mon, 30 Sep 2024 20:35:58 +0200 Subject: [PATCH v2 3/4] drm/msm/dpu: Add support for MSM8937 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240930-dpu-msm8953-msm8996-v2-3-594c3e3190b4@mainlining.org> References: <20240930-dpu-msm8953-msm8996-v2-0-594c3e3190b4@mainlining.org> In-Reply-To: <20240930-dpu-msm8953-msm8996-v2-0-594c3e3190b4@mainlining.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Simona Vetter Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727721359; l=9486; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=okZgb4+yWJwwh7RgmIFm2ZMiFghdKsHJEbDfV6kHm8M=; b=eAs1TSgkJdWGvBW2bitoABQyu65WMFx3TbQLnV4PMSbm99aJRmz9YImeOqESq7I6fpZds32O5 yxhBiMTpPTTAYwdVbhTn/bzLFah5kahxFKocoDLjdBLm/TVSuBmnsVm X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= From: Dmitry Baryshkov Add support for MSM8937, which has MDP5 v1.14. It looks like trimmed down version of MSM8996. Less SSPP, LM and PP blocks. No DSC, etc. Signed-off-by: Dmitry Baryshkov [Remove intr_start from CTLs config, reword the commit] Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n Reviewed-by: Dmitry Baryshkov --- .../drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 210 +++++++++++++++++= ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + drivers/gpu/drm/msm/msm_drv.c | 1 + 5 files changed, 214 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h new file mode 100644 index 0000000000000000000000000000000000000000..ab3dfb0b374ead36c7f07b0a77c= 703fb2c09ff8a --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h @@ -0,0 +1,210 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DPU_1_14_MSM8937_H +#define _DPU_1_14_MSM8937_H + +static const struct dpu_caps msm8937_dpu_caps =3D { + .max_mixer_width =3D DEFAULT_DPU_LINE_WIDTH, + .max_mixer_blendstages =3D 0x4, + .max_linewidth =3D DEFAULT_DPU_LINE_WIDTH, + .pixel_ram_size =3D 40 * 1024, + .max_hdeci_exp =3D MAX_HORZ_DECIMATION, + .max_vdeci_exp =3D MAX_VERT_DECIMATION, +}; + +static const struct dpu_mdp_cfg msm8937_mdp[] =3D { + { + .name =3D "top_0", + .base =3D 0x0, .len =3D 0x454, + .features =3D BIT(DPU_MDP_VSYNC_SEL), + .clk_ctrls =3D { + [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, + [DPU_CLK_CTRL_RGB0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 4 }, + [DPU_CLK_CTRL_RGB1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 4 }, + [DPU_CLK_CTRL_DMA0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 8 }, + [DPU_CLK_CTRL_CURSOR0] =3D { .reg_off =3D 0x3a8, .bit_off =3D 16 }, + }, + }, +}; + +static const struct dpu_ctl_cfg msm8937_ctl[] =3D { + { + .name =3D "ctl_0", .id =3D CTL_0, + .base =3D 0x1000, .len =3D 0x64, + }, { + .name =3D "ctl_1", .id =3D CTL_1, + .base =3D 0x1200, .len =3D 0x64, + }, { + .name =3D "ctl_2", .id =3D CTL_2, + .base =3D 0x1400, .len =3D 0x64, + }, +}; + +static const struct dpu_sspp_cfg msm8937_sspp[] =3D { + { + .name =3D "sspp_0", .id =3D SSPP_VIG0, + .base =3D 0x4000, .len =3D 0x150, + .features =3D VIG_MSM8953_MASK, + .sblk =3D &dpu_vig_sblk_qseed2, + .xin_id =3D 0, + .type =3D SSPP_TYPE_VIG, + .clk_ctrl =3D DPU_CLK_CTRL_VIG0, + }, { + .name =3D "sspp_4", .id =3D SSPP_RGB0, + .base =3D 0x14000, .len =3D 0x150, + .features =3D RGB_MSM8953_MASK, + .sblk =3D &dpu_rgb_sblk, + .xin_id =3D 1, + .type =3D SSPP_TYPE_RGB, + .clk_ctrl =3D DPU_CLK_CTRL_RGB0, + }, { + .name =3D "sspp_5", .id =3D SSPP_RGB1, + .base =3D 0x16000, .len =3D 0x150, + .features =3D RGB_MSM8953_MASK, + .sblk =3D &dpu_rgb_sblk, + .xin_id =3D 5, + .type =3D SSPP_TYPE_RGB, + .clk_ctrl =3D DPU_CLK_CTRL_RGB1, + }, { + .name =3D "sspp_8", .id =3D SSPP_DMA0, + .base =3D 0x24000, .len =3D 0x150, + .features =3D DMA_MSM8953_MASK | BIT(DPU_SSPP_CURSOR), + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 2, + .type =3D SSPP_TYPE_DMA, + .clk_ctrl =3D DPU_CLK_CTRL_DMA0, + }, +}; + +static const struct dpu_lm_cfg msm8937_lm[] =3D { + { + .name =3D "lm_0", .id =3D LM_0, + .base =3D 0x44000, .len =3D 0x320, + .sblk =3D &msm8998_lm_sblk, + .lm_pair =3D LM_1, + .pingpong =3D PINGPONG_0, + .dspp =3D DSPP_0, + }, { + .name =3D "lm_1", .id =3D LM_1, + .base =3D 0x45000, .len =3D 0x320, + .sblk =3D &msm8998_lm_sblk, + .lm_pair =3D LM_0, + .pingpong =3D PINGPONG_1, + }, +}; + +static const struct dpu_pingpong_cfg msm8937_pp[] =3D { + { + .name =3D "pingpong_0", .id =3D PINGPONG_0, + .base =3D 0x70000, .len =3D 0xd4, + .features =3D PINGPONG_MSM8996_MASK, + .sblk =3D &msm8996_pp_sblk, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), + }, { + .name =3D "pingpong_1", .id =3D PINGPONG_1, + .base =3D 0x70800, .len =3D 0xd4, + .features =3D PINGPONG_MSM8996_MASK, + .sblk =3D &msm8996_pp_sblk, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), + }, +}; + +static const struct dpu_dspp_cfg msm8937_dspp[] =3D { + { + .name =3D "dspp_0", .id =3D DSPP_0, + .base =3D 0x54000, .len =3D 0x1800, + .features =3D DSPP_SC7180_MASK, + .sblk =3D &msm8998_dspp_sblk, + }, +}; + +static const struct dpu_intf_cfg msm8937_intf[] =3D { + { + .name =3D "intf_1", .id =3D INTF_1, + .base =3D 0x6a800, .len =3D 0x268, + .type =3D INTF_DSI, + .controller_id =3D MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 14, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr =3D -1, + }, { + .name =3D "intf_2", .id =3D INTF_2, + .base =3D 0x6b000, .len =3D 0x268, + .type =3D INTF_DSI, + .controller_id =3D MSM_DSI_CONTROLLER_1, + .prog_fetch_lines_worst_case =3D 14, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), + .intr_tear_rd_ptr =3D -1, + }, +}; + +static const struct dpu_perf_cfg msm8937_perf_data =3D { + .max_bw_low =3D 3100000, + .max_bw_high =3D 3100000, + .min_core_ib =3D 2400000, + .min_llcc_ib =3D 0, /* No LLCC on this SoC */ + .min_dram_ib =3D 800000, + .undersized_prefill_lines =3D 2, + .xtra_prefill_lines =3D 2, + .dest_scale_prefill_lines =3D 3, + .macrotile_prefill_lines =3D 4, + .yuv_nv12_prefill_lines =3D 8, + .linear_prefill_lines =3D 1, + .downscaling_prefill_lines =3D 1, + .amortizable_threshold =3D 25, + .min_prefill_lines =3D 14, + .danger_lut_tbl =3D {0xf, 0xffff, 0x0}, + .safe_lut_tbl =3D {0xfffc, 0xff00, 0xffff}, + .qos_lut_tbl =3D { + {.nentry =3D ARRAY_SIZE(msm8998_qos_linear), + .entries =3D msm8998_qos_linear + }, + {.nentry =3D ARRAY_SIZE(msm8998_qos_macrotile), + .entries =3D msm8998_qos_macrotile + }, + {.nentry =3D ARRAY_SIZE(msm8998_qos_nrt), + .entries =3D msm8998_qos_nrt + }, + }, + .cdp_cfg =3D { + {.rd_enable =3D 1, .wr_enable =3D 1}, + {.rd_enable =3D 1, .wr_enable =3D 0} + }, + .clk_inefficiency_factor =3D 105, + .bw_inefficiency_factor =3D 120, +}; + +static const struct dpu_mdss_version msm8937_mdss_ver =3D { + .core_major_ver =3D 1, + .core_minor_ver =3D 14, +}; + +const struct dpu_mdss_cfg dpu_msm8937_cfg =3D { + .mdss_ver =3D &msm8937_mdss_ver, + .caps =3D &msm8937_dpu_caps, + .mdp =3D msm8937_mdp, + .ctl_count =3D ARRAY_SIZE(msm8937_ctl), + .ctl =3D msm8937_ctl, + .sspp_count =3D ARRAY_SIZE(msm8937_sspp), + .sspp =3D msm8937_sspp, + .mixer_count =3D ARRAY_SIZE(msm8937_lm), + .mixer =3D msm8937_lm, + .dspp_count =3D ARRAY_SIZE(msm8937_dspp), + .dspp =3D msm8937_dspp, + .pingpong_count =3D ARRAY_SIZE(msm8937_pp), + .pingpong =3D msm8937_pp, + .intf_count =3D ARRAY_SIZE(msm8937_intf), + .intf =3D msm8937_intf, + .vbif_count =3D ARRAY_SIZE(msm8996_vbif), + .vbif =3D msm8996_vbif, + .perf =3D &msm8937_perf_data, +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 3049d7d15a34605455ad5f0db2cc118315c64bee..374d478faec4a08138f3e6cf2b3= 96996eb082baa 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -779,6 +779,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = =3D { *************************************************************/ =20 #include "catalog/dpu_1_7_msm8996.h" +#include "catalog/dpu_1_14_msm8937.h" #include "catalog/dpu_1_16_msm8953.h" =20 #include "catalog/dpu_3_0_msm8998.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 68c1364c3ffe10ddf784079006ece2d73e62a4bf..cd9cd27f816969cf95ecdc46d0f= 5821ba851294c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -831,6 +831,7 @@ struct dpu_mdss_cfg { const struct dpu_format_extended *vig_formats; }; =20 +extern const struct dpu_mdss_cfg dpu_msm8937_cfg; extern const struct dpu_mdss_cfg dpu_msm8953_cfg; extern const struct dpu_mdss_cfg dpu_msm8996_cfg; extern const struct dpu_mdss_cfg dpu_msm8998_cfg; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 33f6a854461eb63b4b14b6525e88799342a7df54..778d11d6cb63235456451bec83f= 0b1d9127861b8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1445,6 +1445,7 @@ static const struct dev_pm_ops dpu_pm_ops =3D { }; =20 static const struct of_device_id dpu_dt_match[] =3D { + { .compatible =3D "qcom,msm8937-mdp5", .data =3D &dpu_msm8937_cfg, }, { .compatible =3D "qcom,msm8953-mdp5", .data =3D &dpu_msm8953_cfg, }, { .compatible =3D "qcom,msm8996-mdp5", .data =3D &dpu_msm8996_cfg, }, { .compatible =3D "qcom,msm8998-dpu", .data =3D &dpu_msm8998_cfg, }, diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index ea2e39f002f2aa7871efcb0a3983069077a094b1..d7e51a7c25aad10629aee5166cd= 501693e8ec4fd 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -983,6 +983,7 @@ module_param(prefer_mdp5, bool, 0444); =20 /* list all platforms supported by both mdp5 and dpu drivers */ static const char *const msm_mdp5_dpu_migration[] =3D { + "qcom,msm8937-mdp5", "qcom,msm8953-mdp5", "qcom,msm8996-mdp5", "qcom,sdm630-mdp5", --=20 2.46.2