From nobody Thu Nov 28 16:48:18 2024 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 592CD192D82; Mon, 30 Sep 2024 18:36:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727721370; cv=none; b=gAGjLIQxHgA/35atGQPi/5/cgeTbUmZC530/engLC6HZpdLO1f+it+uLW2sC9IXiR8Ty4kSP0rU3ZTC4gfaFsTfWSMH88ZyNk4WrB/e4JjE8XmarA0EJwQag2d9UzBUVTIw0SNkPJ16fnkm+K25PkSmlw/MKXIRogkto7lh0WOs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727721370; c=relaxed/simple; bh=YRjmAerOOqTM6StnDRFOOAGeReltV65FWOr7+E1ycQM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DXhUFzT3VpPLIQghrWlUqz1IdWWlNbA29GtrkuIzc4Pzs66u3l/fmZKapORlL6ILsFTQxPh49hU/Cd+rh2VFM01O8IuRkM1xiPZxRuOO3G5825smVCqs8VW9mRFllVXFILqvwH8fLihVtJ5ikwysWbGq59ZZB17fKun1flOFvPA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org; spf=pass smtp.mailfrom=mainlining.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=LTT+1QeY; arc=none smtp.client-ip=5.75.144.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mainlining.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="LTT+1QeY" Received: from [192.168.1.130] (51B6DC6E.dsl.pool.telekom.hu [81.182.220.110]) by mail.mainlining.org (Postfix) with ESMTPSA id 32374E4521; Mon, 30 Sep 2024 18:36:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mainlining.org; s=psm; t=1727721360; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=oKb6G1ckxP05vV6eCYAwKE4qy5r7ox3As405/e0/Om0=; b=LTT+1QeYyUhzjfJCrBYvZAZJo2ShxNsd3zQFERS+32ZLp2hJaE/dyNfuB2ON967sDOuzlG I43TvjZCXP9EHU4mj2XAhLTvw3it7kG2W4viWZzCFz9NMkDluKDHTSS+nyk0NJQQ18KXQA XgMVPoaDvtxtjee6JdKVNgACBTet6oGMRQgFw3F0xAID3mVHOrlanFbDY2JKl95pho56xG EroVOY7t/fU0dBH/A6sChwOliFUv3NZRxH7wjr9c65tKX+sjUMCoFM7b43jAln0WdOJc8f XCBtivI1sGQlIRQMpAO7h2V8K59jsV37N80bRJ2k7uluoNWxrN0UGMRMlHQeIQ== From: =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= Date: Mon, 30 Sep 2024 20:35:56 +0200 Subject: [PATCH v2 1/4] drm/msm/dpu: Add support for MSM8996 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240930-dpu-msm8953-msm8996-v2-1-594c3e3190b4@mainlining.org> References: <20240930-dpu-msm8953-msm8996-v2-0-594c3e3190b4@mainlining.org> In-Reply-To: <20240930-dpu-msm8953-msm8996-v2-0-594c3e3190b4@mainlining.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Simona Vetter Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= , Konrad Dybcio , Konrad Dybcio , Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727721359; l=19117; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=gQrgAUsRvFgloiAHd5j64bXYZU5JcVEFVWnI5BGhiL0=; b=fHlYHoCdmJ/0Op3RigQPyE/m4ZPnslWyo29VlHLVXytVBNwaoHcymqD1cWZrtrHkIJXTUUfnI Kik9sEJqLaFDl30ZgJhM+pEmY7DdRQJGklQk1J5yU8sz5KVCtf7esbD X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= From: Konrad Dybcio Add support for MSM8996, which - fun fact - was the SoC that this driver (or rather SDE, its downstream origin) was meant for and first tested on. It has some hardware that differs from the modern SoCs, so not a lot of current structs could have been reused. It's also seemingly the only SoC supported by DPU that uses RGB pipes. Note, by default this platform is still handled by the MDP5 driver unless the `msm.prefer_mdp5=3Dfalse' parameter is provided. Signed-off-by: Konrad Dybcio Signed-off-by: Konrad Dybcio [DB: rebased on top of sblk changes, add dpu_rgb_sblk] Signed-off-by: Dmitry Baryshkov Acked-by: Konrad Dybcio [Removed intr_start from CTLs config, removed LM_3 and LM_4] Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n Reviewed-by: Dmitry Baryshkov --- .../drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h | 338 +++++++++++++++++= ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 94 ++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + drivers/gpu/drm/msm/msm_drv.c | 1 + 5 files changed, 435 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h new file mode 100644 index 0000000000000000000000000000000000000000..491f6f5827d151011dd3f74bef2= a4b8bf69591ab --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h @@ -0,0 +1,338 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023, Linaro Limited + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserve= d. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + */ + +#ifndef _DPU_1_7_MSM8996_H +#define _DPU_1_7_MSM8996_H + +static const struct dpu_caps msm8996_dpu_caps =3D { + .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages =3D 0x7, + .has_src_split =3D true, + .max_linewidth =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .pixel_ram_size =3D DEFAULT_PIXEL_RAM_SIZE, + .max_hdeci_exp =3D MAX_HORZ_DECIMATION, + .max_vdeci_exp =3D MAX_VERT_DECIMATION, +}; + +static const struct dpu_mdp_cfg msm8996_mdp[] =3D { + { + .name =3D "top_0", + .base =3D 0x0, .len =3D 0x454, + .features =3D BIT(DPU_MDP_VSYNC_SEL), + .clk_ctrls =3D { + [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, + [DPU_CLK_CTRL_VIG1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 0 }, + [DPU_CLK_CTRL_VIG2] =3D { .reg_off =3D 0x2bc, .bit_off =3D 0 }, + [DPU_CLK_CTRL_VIG3] =3D { .reg_off =3D 0x2c4, .bit_off =3D 0 }, + [DPU_CLK_CTRL_RGB0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 4 }, + [DPU_CLK_CTRL_RGB1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 4 }, + [DPU_CLK_CTRL_RGB2] =3D { .reg_off =3D 0x2bc, .bit_off =3D 4 }, + [DPU_CLK_CTRL_RGB3] =3D { .reg_off =3D 0x2c4, .bit_off =3D 4 }, + [DPU_CLK_CTRL_DMA0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 8 }, + [DPU_CLK_CTRL_DMA1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 8 }, + [DPU_CLK_CTRL_CURSOR0] =3D { .reg_off =3D 0x3a8, .bit_off =3D 16 }, + [DPU_CLK_CTRL_CURSOR1] =3D { .reg_off =3D 0x3b0, .bit_off =3D 16 }, + }, + }, +}; + +static const struct dpu_ctl_cfg msm8996_ctl[] =3D { + { + .name =3D "ctl_0", .id =3D CTL_0, + .base =3D 0x1000, .len =3D 0x64, + }, { + .name =3D "ctl_1", .id =3D CTL_1, + .base =3D 0x1200, .len =3D 0x64, + }, { + .name =3D "ctl_2", .id =3D CTL_2, + .base =3D 0x1400, .len =3D 0x64, + }, { + .name =3D "ctl_3", .id =3D CTL_3, + .base =3D 0x1600, .len =3D 0x64, + }, { + .name =3D "ctl_4", .id =3D CTL_4, + .base =3D 0x1800, .len =3D 0x64, + }, +}; + +static const struct dpu_sspp_cfg msm8996_sspp[] =3D { + { + .name =3D "sspp_0", .id =3D SSPP_VIG0, + .base =3D 0x4000, .len =3D 0x150, + .features =3D VIG_MSM8996_MASK, + .sblk =3D &dpu_vig_sblk_qseed2, + .xin_id =3D 0, + .type =3D SSPP_TYPE_VIG, + .clk_ctrl =3D DPU_CLK_CTRL_VIG0, + }, { + .name =3D "sspp_1", .id =3D SSPP_VIG1, + .base =3D 0x6000, .len =3D 0x150, + .features =3D VIG_MSM8996_MASK, + .sblk =3D &dpu_vig_sblk_qseed2, + .xin_id =3D 4, + .type =3D SSPP_TYPE_VIG, + .clk_ctrl =3D DPU_CLK_CTRL_VIG1, + }, { + .name =3D "sspp_2", .id =3D SSPP_VIG2, + .base =3D 0x8000, .len =3D 0x150, + .features =3D VIG_MSM8996_MASK, + .sblk =3D &dpu_vig_sblk_qseed2, + .xin_id =3D 8, + .type =3D SSPP_TYPE_VIG, + .clk_ctrl =3D DPU_CLK_CTRL_VIG2, + }, { + .name =3D "sspp_3", .id =3D SSPP_VIG3, + .base =3D 0xa000, .len =3D 0x150, + .features =3D VIG_MSM8996_MASK, + .sblk =3D &dpu_vig_sblk_qseed2, + .xin_id =3D 12, + .type =3D SSPP_TYPE_VIG, + .clk_ctrl =3D DPU_CLK_CTRL_VIG3, + }, { + .name =3D "sspp_4", .id =3D SSPP_RGB0, + .base =3D 0x14000, .len =3D 0x150, + .features =3D RGB_MSM8996_MASK, + .sblk =3D &dpu_rgb_sblk, + .xin_id =3D 1, + .type =3D SSPP_TYPE_RGB, + .clk_ctrl =3D DPU_CLK_CTRL_RGB0, + }, { + .name =3D "sspp_5", .id =3D SSPP_RGB1, + .base =3D 0x16000, .len =3D 0x150, + .features =3D RGB_MSM8996_MASK, + .sblk =3D &dpu_rgb_sblk, + .xin_id =3D 5, + .type =3D SSPP_TYPE_RGB, + .clk_ctrl =3D DPU_CLK_CTRL_RGB1, + }, { + .name =3D "sspp_6", .id =3D SSPP_RGB2, + .base =3D 0x18000, .len =3D 0x150, + .features =3D RGB_MSM8996_MASK, + .sblk =3D &dpu_rgb_sblk, + .xin_id =3D 9, + .type =3D SSPP_TYPE_RGB, + .clk_ctrl =3D DPU_CLK_CTRL_RGB2, + }, { + .name =3D "sspp_7", .id =3D SSPP_RGB3, + .base =3D 0x1a000, .len =3D 0x150, + .features =3D RGB_MSM8996_MASK, + .sblk =3D &dpu_rgb_sblk, + .xin_id =3D 13, + .type =3D SSPP_TYPE_RGB, + .clk_ctrl =3D DPU_CLK_CTRL_RGB3, + }, { + .name =3D "sspp_8", .id =3D SSPP_DMA0, + .base =3D 0x24000, .len =3D 0x150, + .features =3D DMA_MSM8996_MASK, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 2, + .type =3D SSPP_TYPE_DMA, + .clk_ctrl =3D DPU_CLK_CTRL_DMA0, + }, { + .name =3D "sspp_9", .id =3D SSPP_DMA1, + .base =3D 0x26000, .len =3D 0x150, + .features =3D DMA_MSM8996_MASK, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 10, + .type =3D SSPP_TYPE_DMA, + .clk_ctrl =3D DPU_CLK_CTRL_DMA1, + }, +}; + +static const struct dpu_lm_cfg msm8996_lm[] =3D { + { + .name =3D "lm_0", .id =3D LM_0, + .base =3D 0x44000, .len =3D 0x320, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &msm8998_lm_sblk, + .lm_pair =3D LM_1, + .pingpong =3D PINGPONG_0, + .dspp =3D DSPP_0, + }, { + .name =3D "lm_1", .id =3D LM_1, + .base =3D 0x45000, .len =3D 0x320, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &msm8998_lm_sblk, + .lm_pair =3D LM_0, + .pingpong =3D PINGPONG_1, + .dspp =3D DSPP_1, + }, { + .name =3D "lm_2", .id =3D LM_2, + .base =3D 0x46000, .len =3D 0x320, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &msm8998_lm_sblk, + .lm_pair =3D LM_5, + .pingpong =3D PINGPONG_2, + }, { + .name =3D "lm_5", .id =3D LM_5, + .base =3D 0x49000, .len =3D 0x320, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &msm8998_lm_sblk, + .lm_pair =3D LM_2, + .pingpong =3D PINGPONG_3, + }, +}; + +static const struct dpu_pingpong_cfg msm8996_pp[] =3D { + { + .name =3D "pingpong_0", .id =3D PINGPONG_0, + .base =3D 0x70000, .len =3D 0xd4, + .features =3D PINGPONG_MSM8996_TE2_MASK, + .sblk =3D &msm8996_pp_sblk_te, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), + }, { + .name =3D "pingpong_1", .id =3D PINGPONG_1, + .base =3D 0x70800, .len =3D 0xd4, + .features =3D PINGPONG_MSM8996_TE2_MASK, + .sblk =3D &msm8996_pp_sblk_te, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), + }, { + .name =3D "pingpong_2", .id =3D PINGPONG_2, + .base =3D 0x71000, .len =3D 0xd4, + .features =3D PINGPONG_MSM8996_MASK, + .sblk =3D &msm8996_pp_sblk, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14), + }, { + .name =3D "pingpong_3", .id =3D PINGPONG_3, + .base =3D 0x71800, .len =3D 0xd4, + .features =3D PINGPONG_MSM8996_MASK, + .sblk =3D &msm8996_pp_sblk, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15), + }, +}; + +static const struct dpu_dsc_cfg msm8996_dsc[] =3D { + { + .name =3D "dsc_0", .id =3D DSC_0, + .base =3D 0x80000, .len =3D 0x140, + }, { + .name =3D "dsc_1", .id =3D DSC_1, + .base =3D 0x80400, .len =3D 0x140, + }, +}; + +static const struct dpu_dspp_cfg msm8996_dspp[] =3D { + { + .name =3D "dspp_0", .id =3D DSPP_0, + .base =3D 0x54000, .len =3D 0x1800, + .features =3D DSPP_SC7180_MASK, + .sblk =3D &msm8998_dspp_sblk, + }, { + .name =3D "dspp_1", .id =3D DSPP_1, + .base =3D 0x56000, .len =3D 0x1800, + .features =3D DSPP_SC7180_MASK, + .sblk =3D &msm8998_dspp_sblk, + }, +}; + +static const struct dpu_intf_cfg msm8996_intf[] =3D { + { + .name =3D "intf_0", .id =3D INTF_0, + .base =3D 0x6a000, .len =3D 0x268, + .type =3D INTF_NONE, + .prog_fetch_lines_worst_case =3D 25, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), + .intr_tear_rd_ptr =3D -1, + }, { + .name =3D "intf_1", .id =3D INTF_1, + .base =3D 0x6a800, .len =3D 0x268, + .type =3D INTF_DSI, + .controller_id =3D MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 25, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr =3D -1, + }, { + .name =3D "intf_2", .id =3D INTF_2, + .base =3D 0x6b000, .len =3D 0x268, + .type =3D INTF_DSI, + .controller_id =3D MSM_DSI_CONTROLLER_1, + .prog_fetch_lines_worst_case =3D 25, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), + .intr_tear_rd_ptr =3D -1, + }, { + .name =3D "intf_3", .id =3D INTF_3, + .base =3D 0x6b800, .len =3D 0x268, + .type =3D INTF_HDMI, + .prog_fetch_lines_worst_case =3D 25, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), + .intr_tear_rd_ptr =3D -1, + }, +}; + +static const struct dpu_perf_cfg msm8996_perf_data =3D { + .max_bw_low =3D 9600000, + .max_bw_high =3D 9600000, + .min_core_ib =3D 2400000, + .min_llcc_ib =3D 0, /* No LLCC on this SoC */ + .min_dram_ib =3D 800000, + .undersized_prefill_lines =3D 2, + .xtra_prefill_lines =3D 2, + .dest_scale_prefill_lines =3D 3, + .macrotile_prefill_lines =3D 4, + .yuv_nv12_prefill_lines =3D 8, + .linear_prefill_lines =3D 1, + .downscaling_prefill_lines =3D 1, + .amortizable_threshold =3D 25, + .min_prefill_lines =3D 21, + .danger_lut_tbl =3D {0xf, 0xffff, 0x0}, + .safe_lut_tbl =3D {0xfffc, 0xff00, 0xffff}, + .qos_lut_tbl =3D { + {.nentry =3D ARRAY_SIZE(msm8998_qos_linear), + .entries =3D msm8998_qos_linear + }, + {.nentry =3D ARRAY_SIZE(msm8998_qos_macrotile), + .entries =3D msm8998_qos_macrotile + }, + {.nentry =3D ARRAY_SIZE(msm8998_qos_nrt), + .entries =3D msm8998_qos_nrt + }, + }, + .cdp_cfg =3D { + {.rd_enable =3D 1, .wr_enable =3D 1}, + {.rd_enable =3D 1, .wr_enable =3D 0} + }, + .clk_inefficiency_factor =3D 105, + .bw_inefficiency_factor =3D 120, +}; + +static const struct dpu_mdss_version msm8996_mdss_ver =3D { + .core_major_ver =3D 1, + .core_minor_ver =3D 7, +}; + +const struct dpu_mdss_cfg dpu_msm8996_cfg =3D { + .mdss_ver =3D &msm8996_mdss_ver, + .caps =3D &msm8996_dpu_caps, + .mdp =3D msm8996_mdp, + .ctl_count =3D ARRAY_SIZE(msm8996_ctl), + .ctl =3D msm8996_ctl, + .sspp_count =3D ARRAY_SIZE(msm8996_sspp), + .sspp =3D msm8996_sspp, + .mixer_count =3D ARRAY_SIZE(msm8996_lm), + .mixer =3D msm8996_lm, + .dspp_count =3D ARRAY_SIZE(msm8996_dspp), + .dspp =3D msm8996_dspp, + .pingpong_count =3D ARRAY_SIZE(msm8996_pp), + .pingpong =3D msm8996_pp, + .dsc_count =3D ARRAY_SIZE(msm8996_dsc), + .dsc =3D msm8996_dsc, + .intf_count =3D ARRAY_SIZE(msm8996_intf), + .intf =3D msm8996_intf, + .vbif_count =3D ARRAY_SIZE(msm8996_vbif), + .vbif =3D msm8996_vbif, + .perf =3D &msm8996_perf_data, +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index dcb4fd85e73b9cc05e669043602d69229881c0b4..03274c8fcd9fda3167bd2daad79= 6157a1a496b2c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -21,6 +21,11 @@ (VIG_BASE_MASK | \ BIT(DPU_SSPP_CSC_10BIT)) =20 +#define VIG_MSM8996_MASK \ + (BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_CDP) |\ + BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_SCALER_QSEED2) |\ + BIT(DPU_SSPP_CSC)) + #define VIG_MSM8998_MASK \ (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE)) =20 @@ -32,6 +37,9 @@ =20 #define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL)) =20 +#define DMA_MSM8996_MASK \ + (BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_CDP)) + #define DMA_MSM8998_MASK \ (BIT(DPU_SSPP_QOS) |\ BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ @@ -57,9 +65,16 @@ #define DMA_CURSOR_SDM845_MASK_SDMA \ (DMA_CURSOR_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) =20 +#define DMA_CURSOR_MSM8996_MASK \ + (DMA_MSM8996_MASK | BIT(DPU_SSPP_CURSOR)) + #define DMA_CURSOR_MSM8998_MASK \ (DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR)) =20 +#define RGB_MSM8996_MASK \ + (BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_CDP) |\ + BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_SCALER_RGB)) + #define MIXER_MSM8998_MASK \ (BIT(DPU_MIXER_SOURCESPLIT)) =20 @@ -69,6 +84,12 @@ #define MIXER_QCM2290_MASK \ (BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA)) =20 +#define PINGPONG_MSM8996_MASK \ + (BIT(DPU_PINGPONG_DSC)) + +#define PINGPONG_MSM8996_TE2_MASK \ + (PINGPONG_MSM8996_MASK | BIT(DPU_PINGPONG_TE2)) + #define PINGPONG_SDM845_MASK \ (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC)) =20 @@ -316,6 +337,35 @@ static const u32 wb2_formats_rgb_yuv[] =3D { .virt_num_formats =3D ARRAY_SIZE(plane_formats), \ } =20 +/* qseed2 is not supported, so disabled scaling */ +#define _VIG_SBLK_QSEED2() \ + { \ + .maxdwnscale =3D SSPP_UNITY_SCALE, \ + .maxupscale =3D SSPP_UNITY_SCALE, \ + .scaler_blk =3D {.name =3D "scaler", \ + /* no version for qseed2 */ \ + .base =3D 0x200, .len =3D 0xa0,}, \ + .csc_blk =3D {.name =3D "csc", \ + .base =3D 0x320, .len =3D 0x100,}, \ + .format_list =3D plane_formats_yuv, \ + .num_formats =3D ARRAY_SIZE(plane_formats_yuv), \ + .virt_format_list =3D plane_formats, \ + .virt_num_formats =3D ARRAY_SIZE(plane_formats), \ + .rotation_cfg =3D NULL, \ + } + +#define _RGB_SBLK() \ + { \ + .maxdwnscale =3D SSPP_UNITY_SCALE, \ + .maxupscale =3D SSPP_UNITY_SCALE, \ + .scaler_blk =3D {.name =3D "scaler", \ + .base =3D 0x200, .len =3D 0x28,}, \ + .format_list =3D plane_formats, \ + .num_formats =3D ARRAY_SIZE(plane_formats), \ + .virt_format_list =3D plane_formats, \ + .virt_num_formats =3D ARRAY_SIZE(plane_formats), \ + } + #define _DMA_SBLK() \ { \ .maxdwnscale =3D SSPP_UNITY_SCALE, \ @@ -332,6 +382,9 @@ static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg= _v2 =3D { .rot_format_list =3D rotation_v2_formats, }; =20 +static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed2 =3D + _VIG_SBLK_QSEED2(); + static const struct dpu_sspp_sub_blks dpu_vig_sblk_noscale =3D _VIG_SBLK_NOSCALE(); =20 @@ -363,6 +416,8 @@ static const struct dpu_sspp_sub_blks dpu_vig_sblk_qsee= d3_3_2 =3D static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_3 =3D _VIG_SBLK(SSPP_SCALER_VER(3, 3)); =20 +static const struct dpu_sspp_sub_blks dpu_rgb_sblk =3D _RGB_SBLK(); + static const struct dpu_sspp_sub_blks dpu_dma_sblk =3D _DMA_SBLK(); =20 /************************************************************* @@ -427,6 +482,15 @@ static const struct dpu_dspp_sub_blks sdm845_dspp_sblk= =3D { /************************************************************* * PINGPONG sub blocks config *************************************************************/ +static const struct dpu_pingpong_sub_blks msm8996_pp_sblk_te =3D { + .te2 =3D {.name =3D "te2", .base =3D 0x2000, .len =3D 0x0, + .version =3D 0x1}, +}; + +static const struct dpu_pingpong_sub_blks msm8996_pp_sblk =3D { + /* No dither block */ +}; + static const struct dpu_pingpong_sub_blks sdm845_pp_sblk_te =3D { .te2 =3D {.name =3D "te2", .base =3D 0x2000, .len =3D 0x0, .version =3D 0x1}, @@ -492,6 +556,34 @@ static const struct dpu_vbif_dynamic_ot_cfg msm8998_ot= _rdwr_cfg[] =3D { }, }; =20 +static const struct dpu_vbif_cfg msm8996_vbif[] =3D { + { + .name =3D "vbif_rt", .id =3D VBIF_RT, + .base =3D 0, .len =3D 0x1040, + .default_ot_rd_limit =3D 32, + .default_ot_wr_limit =3D 16, + .features =3D BIT(DPU_VBIF_QOS_REMAP) | BIT(DPU_VBIF_QOS_OTLIM), + .xin_halt_timeout =3D 0x4000, + .qos_rp_remap_size =3D 0x20, + .dynamic_ot_rd_tbl =3D { + .count =3D ARRAY_SIZE(msm8998_ot_rdwr_cfg), + .cfg =3D msm8998_ot_rdwr_cfg, + }, + .dynamic_ot_wr_tbl =3D { + .count =3D ARRAY_SIZE(msm8998_ot_rdwr_cfg), + .cfg =3D msm8998_ot_rdwr_cfg, + }, + .qos_rt_tbl =3D { + .npriority_lvl =3D ARRAY_SIZE(msm8998_rt_pri_lvl), + .priority_lvl =3D msm8998_rt_pri_lvl, + }, + .qos_nrt_tbl =3D { + .npriority_lvl =3D ARRAY_SIZE(msm8998_nrt_pri_lvl), + .priority_lvl =3D msm8998_nrt_pri_lvl, + }, + }, +}; + static const struct dpu_vbif_cfg msm8998_vbif[] =3D { { .name =3D "vbif_rt", .id =3D VBIF_RT, @@ -675,6 +767,8 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = =3D { * Hardware catalog *************************************************************/ =20 +#include "catalog/dpu_1_7_msm8996.h" + #include "catalog/dpu_3_0_msm8998.h" #include "catalog/dpu_3_2_sdm660.h" #include "catalog/dpu_3_3_sdm630.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 37e18e820a20a4c4ab9a97da78df19a2ff7cfa00..69f089431901b020e7766f6628c= 0fca35c3703ce 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -831,6 +831,7 @@ struct dpu_mdss_cfg { const struct dpu_format_extended *vig_formats; }; =20 +extern const struct dpu_mdss_cfg dpu_msm8996_cfg; extern const struct dpu_mdss_cfg dpu_msm8998_cfg; extern const struct dpu_mdss_cfg dpu_sdm630_cfg; extern const struct dpu_mdss_cfg dpu_sdm660_cfg; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 9bcae53c4f458cd8e400f0e851b791c0f4165085..b3e53de6a82acd191eb7c3524eb= 1e0e2216e8885 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1445,6 +1445,7 @@ static const struct dev_pm_ops dpu_pm_ops =3D { }; =20 static const struct of_device_id dpu_dt_match[] =3D { + { .compatible =3D "qcom,msm8996-mdp5", .data =3D &dpu_msm8996_cfg, }, { .compatible =3D "qcom,msm8998-dpu", .data =3D &dpu_msm8998_cfg, }, { .compatible =3D "qcom,qcm2290-dpu", .data =3D &dpu_qcm2290_cfg, }, { .compatible =3D "qcom,sdm630-mdp5", .data =3D &dpu_sdm630_cfg, }, diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 8c13b08708d228cf089dd83ad390fd4ad7ae818a..93944ebc08718ec1387ff9e2945= b332786d7acf8 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -983,6 +983,7 @@ module_param(prefer_mdp5, bool, 0444); =20 /* list all platforms supported by both mdp5 and dpu drivers */ static const char *const msm_mdp5_dpu_migration[] =3D { + "qcom,msm8996-mdp5", "qcom,sdm630-mdp5", "qcom,sdm660-mdp5", NULL, --=20 2.46.2 From nobody Thu Nov 28 16:48:18 2024 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59322193417; Mon, 30 Sep 2024 18:36:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727721370; cv=none; b=PsB75ykE0vSxgJpca+Jffq1nICaxY8bl31aZU4zzTUpKdYkCMDb2K65+rlb+TWsi9Ij4oDJwZQTHrVvFF1utJBcBRdXOirLKAgINkecJaVhbw9DEKITEF/ewOjWTnbSSHS6Q9NFCkHdDT4Scg/Jxb0iiKSdX6bxNfhdu+QuNEXY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727721370; c=relaxed/simple; bh=/ttA8M2f6iFpXEv3ZFi3BWHWe3m+RJ0QoH/1AJTGnUU=; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240930-dpu-msm8953-msm8996-v2-2-594c3e3190b4@mainlining.org> References: <20240930-dpu-msm8953-msm8996-v2-0-594c3e3190b4@mainlining.org> In-Reply-To: <20240930-dpu-msm8953-msm8996-v2-0-594c3e3190b4@mainlining.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Simona Vetter Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727721359; l=10627; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=Rg0i3zYCdEQcwk/fXALW5C+HsqOqnoY3QymVng8p/Ps=; b=HKNYOzQqDY8zls4Dx4cXzTERZWb9mfzQjlJOadIFLJlnshhlr4Fw9juFtPmmObmLohyL79HHP DyH5CRX51n6BJCe0PgCmAWpS8vq/l/A+Z+Ejk5Fcm+ifylneWu3BKgj X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= From: Dmitry Baryshkov Add support for MSM8953, which has MDP5 v1.16. It looks like trimmed down version of MSM8996. Less SSPP, LM and PP blocks. No DSC, etc. Signed-off-by: Dmitry Baryshkov [Remove intr_start from CTLs config, reword the commit] Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n Reviewed-by: Dmitry Baryshkov --- .../drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h | 218 +++++++++++++++++= ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 12 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + drivers/gpu/drm/msm/msm_drv.c | 1 + 5 files changed, 233 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h new file mode 100644 index 0000000000000000000000000000000000000000..14f36ea6ad0eb61e87f043437a8= cd78bb1bde49c --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h @@ -0,0 +1,218 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DPU_1_16_MSM8953_H +#define _DPU_1_16_MSM8953_H + +static const struct dpu_caps msm8953_dpu_caps =3D { + .max_mixer_width =3D DEFAULT_DPU_LINE_WIDTH, + .max_mixer_blendstages =3D 0x4, + .max_linewidth =3D DEFAULT_DPU_LINE_WIDTH, + .pixel_ram_size =3D 40 * 1024, + .max_hdeci_exp =3D MAX_HORZ_DECIMATION, + .max_vdeci_exp =3D MAX_VERT_DECIMATION, +}; + +static const struct dpu_mdp_cfg msm8953_mdp[] =3D { + { + .name =3D "top_0", + .base =3D 0x0, .len =3D 0x454, + .features =3D BIT(DPU_MDP_VSYNC_SEL), + .clk_ctrls =3D { + [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, + [DPU_CLK_CTRL_RGB0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 4 }, + [DPU_CLK_CTRL_RGB1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 4 }, + [DPU_CLK_CTRL_DMA0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 8 }, + [DPU_CLK_CTRL_CURSOR0] =3D { .reg_off =3D 0x3a8, .bit_off =3D 16 }, + }, + }, +}; + +static const struct dpu_ctl_cfg msm8953_ctl[] =3D { + { + .name =3D "ctl_0", .id =3D CTL_0, + .base =3D 0x1000, .len =3D 0x64, + }, { + .name =3D "ctl_1", .id =3D CTL_1, + .base =3D 0x1200, .len =3D 0x64, + }, { + .name =3D "ctl_2", .id =3D CTL_2, + .base =3D 0x1400, .len =3D 0x64, + }, +}; + +static const struct dpu_sspp_cfg msm8953_sspp[] =3D { + { + .name =3D "sspp_0", .id =3D SSPP_VIG0, + .base =3D 0x4000, .len =3D 0x150, + .features =3D VIG_MSM8953_MASK, + .sblk =3D &dpu_vig_sblk_qseed2, + .xin_id =3D 0, + .type =3D SSPP_TYPE_VIG, + .clk_ctrl =3D DPU_CLK_CTRL_VIG0, + }, { + .name =3D "sspp_4", .id =3D SSPP_RGB0, + .base =3D 0x14000, .len =3D 0x150, + .features =3D RGB_MSM8953_MASK, + .sblk =3D &dpu_rgb_sblk, + .xin_id =3D 1, + .type =3D SSPP_TYPE_RGB, + .clk_ctrl =3D DPU_CLK_CTRL_RGB0, + }, { + .name =3D "sspp_5", .id =3D SSPP_RGB1, + .base =3D 0x16000, .len =3D 0x150, + .features =3D RGB_MSM8953_MASK, + .sblk =3D &dpu_rgb_sblk, + .xin_id =3D 5, + .type =3D SSPP_TYPE_RGB, + .clk_ctrl =3D DPU_CLK_CTRL_RGB1, + }, { + .name =3D "sspp_8", .id =3D SSPP_DMA0, + .base =3D 0x24000, .len =3D 0x150, + .features =3D DMA_MSM8953_MASK | BIT(DPU_SSPP_CURSOR), + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 2, + .type =3D SSPP_TYPE_DMA, + .clk_ctrl =3D DPU_CLK_CTRL_DMA0, + }, +}; + +static const struct dpu_lm_cfg msm8953_lm[] =3D { + { + .name =3D "lm_0", .id =3D LM_0, + .base =3D 0x44000, .len =3D 0x320, + .sblk =3D &msm8998_lm_sblk, + .lm_pair =3D LM_1, + .pingpong =3D PINGPONG_0, + .dspp =3D DSPP_0, + }, { + .name =3D "lm_1", .id =3D LM_1, + .base =3D 0x45000, .len =3D 0x320, + .sblk =3D &msm8998_lm_sblk, + .lm_pair =3D LM_0, + .pingpong =3D PINGPONG_1, + }, +}; + +static const struct dpu_pingpong_cfg msm8953_pp[] =3D { + { + .name =3D "pingpong_0", .id =3D PINGPONG_0, + .base =3D 0x70000, .len =3D 0xd4, + .features =3D PINGPONG_MSM8996_MASK, + .sblk =3D &msm8996_pp_sblk, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), + }, { + .name =3D "pingpong_1", .id =3D PINGPONG_1, + .base =3D 0x70800, .len =3D 0xd4, + .features =3D PINGPONG_MSM8996_MASK, + .sblk =3D &msm8996_pp_sblk, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), + }, +}; + +static const struct dpu_dspp_cfg msm8953_dspp[] =3D { + { + .name =3D "dspp_0", .id =3D DSPP_0, + .base =3D 0x54000, .len =3D 0x1800, + .features =3D DSPP_SC7180_MASK, + .sblk =3D &msm8998_dspp_sblk, + }, +}; + +static const struct dpu_intf_cfg msm8953_intf[] =3D { + { + .name =3D "intf_0", .id =3D INTF_0, + .base =3D 0x6a000, .len =3D 0x268, + .type =3D INTF_NONE, + .prog_fetch_lines_worst_case =3D 14, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), + .intr_tear_rd_ptr =3D -1, + }, { + .name =3D "intf_1", .id =3D INTF_1, + .base =3D 0x6a800, .len =3D 0x268, + .type =3D INTF_DSI, + .controller_id =3D MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 14, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr =3D -1, + }, { + .name =3D "intf_2", .id =3D INTF_2, + .base =3D 0x6b000, .len =3D 0x268, + .type =3D INTF_DSI, + .controller_id =3D MSM_DSI_CONTROLLER_1, + .prog_fetch_lines_worst_case =3D 14, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), + .intr_tear_rd_ptr =3D -1, + }, +}; + +static const struct dpu_perf_cfg msm8953_perf_data =3D { + .max_bw_low =3D 3400000, + .max_bw_high =3D 3400000, + .min_core_ib =3D 2400000, + .min_llcc_ib =3D 0, /* No LLCC on this SoC */ + .min_dram_ib =3D 800000, + .undersized_prefill_lines =3D 2, + .xtra_prefill_lines =3D 2, + .dest_scale_prefill_lines =3D 3, + .macrotile_prefill_lines =3D 4, + .yuv_nv12_prefill_lines =3D 8, + .linear_prefill_lines =3D 1, + .downscaling_prefill_lines =3D 1, + .amortizable_threshold =3D 25, + .min_prefill_lines =3D 14, + .danger_lut_tbl =3D {0xf, 0xffff, 0x0}, + .safe_lut_tbl =3D {0xfffc, 0xff00, 0xffff}, + .qos_lut_tbl =3D { + {.nentry =3D ARRAY_SIZE(msm8998_qos_linear), + .entries =3D msm8998_qos_linear + }, + {.nentry =3D ARRAY_SIZE(msm8998_qos_macrotile), + .entries =3D msm8998_qos_macrotile + }, + {.nentry =3D ARRAY_SIZE(msm8998_qos_nrt), + .entries =3D msm8998_qos_nrt + }, + }, + .cdp_cfg =3D { + {.rd_enable =3D 1, .wr_enable =3D 1}, + {.rd_enable =3D 1, .wr_enable =3D 0} + }, + .clk_inefficiency_factor =3D 105, + .bw_inefficiency_factor =3D 120, +}; + +static const struct dpu_mdss_version msm8953_mdss_ver =3D { + .core_major_ver =3D 1, + .core_minor_ver =3D 16, +}; + +const struct dpu_mdss_cfg dpu_msm8953_cfg =3D { + .mdss_ver =3D &msm8953_mdss_ver, + .caps =3D &msm8953_dpu_caps, + .mdp =3D msm8953_mdp, + .ctl_count =3D ARRAY_SIZE(msm8953_ctl), + .ctl =3D msm8953_ctl, + .sspp_count =3D ARRAY_SIZE(msm8953_sspp), + .sspp =3D msm8953_sspp, + .mixer_count =3D ARRAY_SIZE(msm8953_lm), + .mixer =3D msm8953_lm, + .dspp_count =3D ARRAY_SIZE(msm8953_dspp), + .dspp =3D msm8953_dspp, + .pingpong_count =3D ARRAY_SIZE(msm8953_pp), + .pingpong =3D msm8953_pp, + .intf_count =3D ARRAY_SIZE(msm8953_intf), + .intf =3D msm8953_intf, + .vbif_count =3D ARRAY_SIZE(msm8996_vbif), + .vbif =3D msm8996_vbif, + .perf =3D &msm8953_perf_data, +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 03274c8fcd9fda3167bd2daad796157a1a496b2c..3049d7d15a34605455ad5f0db2c= c118315c64bee 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -21,6 +21,11 @@ (VIG_BASE_MASK | \ BIT(DPU_SSPP_CSC_10BIT)) =20 +#define VIG_MSM8953_MASK \ + (BIT(DPU_SSPP_QOS) |\ + BIT(DPU_SSPP_SCALER_QSEED2) |\ + BIT(DPU_SSPP_CSC)) + #define VIG_MSM8996_MASK \ (BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_CDP) |\ BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_SCALER_QSEED2) |\ @@ -37,6 +42,9 @@ =20 #define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL)) =20 +#define DMA_MSM8953_MASK \ + (BIT(DPU_SSPP_QOS)) + #define DMA_MSM8996_MASK \ (BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_CDP)) =20 @@ -71,6 +79,9 @@ #define DMA_CURSOR_MSM8998_MASK \ (DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR)) =20 +#define RGB_MSM8953_MASK \ + (BIT(DPU_SSPP_QOS)) + #define RGB_MSM8996_MASK \ (BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_CDP) |\ BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_SCALER_RGB)) @@ -768,6 +779,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = =3D { *************************************************************/ =20 #include "catalog/dpu_1_7_msm8996.h" +#include "catalog/dpu_1_16_msm8953.h" =20 #include "catalog/dpu_3_0_msm8998.h" #include "catalog/dpu_3_2_sdm660.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 69f089431901b020e7766f6628c0fca35c3703ce..68c1364c3ffe10ddf784079006e= ce2d73e62a4bf 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -831,6 +831,7 @@ struct dpu_mdss_cfg { const struct dpu_format_extended *vig_formats; }; =20 +extern const struct dpu_mdss_cfg dpu_msm8953_cfg; extern const struct dpu_mdss_cfg dpu_msm8996_cfg; extern const struct dpu_mdss_cfg dpu_msm8998_cfg; extern const struct dpu_mdss_cfg dpu_sdm630_cfg; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index b3e53de6a82acd191eb7c3524eb1e0e2216e8885..33f6a854461eb63b4b14b6525e8= 8799342a7df54 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1445,6 +1445,7 @@ static const struct dev_pm_ops dpu_pm_ops =3D { }; =20 static const struct of_device_id dpu_dt_match[] =3D { + { .compatible =3D "qcom,msm8953-mdp5", .data =3D &dpu_msm8953_cfg, }, { .compatible =3D "qcom,msm8996-mdp5", .data =3D &dpu_msm8996_cfg, }, { .compatible =3D "qcom,msm8998-dpu", .data =3D &dpu_msm8998_cfg, }, { .compatible =3D "qcom,qcm2290-dpu", .data =3D &dpu_qcm2290_cfg, }, diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 93944ebc08718ec1387ff9e2945b332786d7acf8..ea2e39f002f2aa7871efcb0a398= 3069077a094b1 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -983,6 +983,7 @@ module_param(prefer_mdp5, bool, 0444); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240930-dpu-msm8953-msm8996-v2-3-594c3e3190b4@mainlining.org> References: <20240930-dpu-msm8953-msm8996-v2-0-594c3e3190b4@mainlining.org> In-Reply-To: <20240930-dpu-msm8953-msm8996-v2-0-594c3e3190b4@mainlining.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Simona Vetter Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727721359; l=9486; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=okZgb4+yWJwwh7RgmIFm2ZMiFghdKsHJEbDfV6kHm8M=; b=eAs1TSgkJdWGvBW2bitoABQyu65WMFx3TbQLnV4PMSbm99aJRmz9YImeOqESq7I6fpZds32O5 yxhBiMTpPTTAYwdVbhTn/bzLFah5kahxFKocoDLjdBLm/TVSuBmnsVm X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= From: Dmitry Baryshkov Add support for MSM8937, which has MDP5 v1.14. It looks like trimmed down version of MSM8996. Less SSPP, LM and PP blocks. No DSC, etc. Signed-off-by: Dmitry Baryshkov [Remove intr_start from CTLs config, reword the commit] Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n Reviewed-by: Dmitry Baryshkov --- .../drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 210 +++++++++++++++++= ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + drivers/gpu/drm/msm/msm_drv.c | 1 + 5 files changed, 214 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h new file mode 100644 index 0000000000000000000000000000000000000000..ab3dfb0b374ead36c7f07b0a77c= 703fb2c09ff8a --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h @@ -0,0 +1,210 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DPU_1_14_MSM8937_H +#define _DPU_1_14_MSM8937_H + +static const struct dpu_caps msm8937_dpu_caps =3D { + .max_mixer_width =3D DEFAULT_DPU_LINE_WIDTH, + .max_mixer_blendstages =3D 0x4, + .max_linewidth =3D DEFAULT_DPU_LINE_WIDTH, + .pixel_ram_size =3D 40 * 1024, + .max_hdeci_exp =3D MAX_HORZ_DECIMATION, + .max_vdeci_exp =3D MAX_VERT_DECIMATION, +}; + +static const struct dpu_mdp_cfg msm8937_mdp[] =3D { + { + .name =3D "top_0", + .base =3D 0x0, .len =3D 0x454, + .features =3D BIT(DPU_MDP_VSYNC_SEL), + .clk_ctrls =3D { + [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, + [DPU_CLK_CTRL_RGB0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 4 }, + [DPU_CLK_CTRL_RGB1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 4 }, + [DPU_CLK_CTRL_DMA0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 8 }, + [DPU_CLK_CTRL_CURSOR0] =3D { .reg_off =3D 0x3a8, .bit_off =3D 16 }, + }, + }, +}; + +static const struct dpu_ctl_cfg msm8937_ctl[] =3D { + { + .name =3D "ctl_0", .id =3D CTL_0, + .base =3D 0x1000, .len =3D 0x64, + }, { + .name =3D "ctl_1", .id =3D CTL_1, + .base =3D 0x1200, .len =3D 0x64, + }, { + .name =3D "ctl_2", .id =3D CTL_2, + .base =3D 0x1400, .len =3D 0x64, + }, +}; + +static const struct dpu_sspp_cfg msm8937_sspp[] =3D { + { + .name =3D "sspp_0", .id =3D SSPP_VIG0, + .base =3D 0x4000, .len =3D 0x150, + .features =3D VIG_MSM8953_MASK, + .sblk =3D &dpu_vig_sblk_qseed2, + .xin_id =3D 0, + .type =3D SSPP_TYPE_VIG, + .clk_ctrl =3D DPU_CLK_CTRL_VIG0, + }, { + .name =3D "sspp_4", .id =3D SSPP_RGB0, + .base =3D 0x14000, .len =3D 0x150, + .features =3D RGB_MSM8953_MASK, + .sblk =3D &dpu_rgb_sblk, + .xin_id =3D 1, + .type =3D SSPP_TYPE_RGB, + .clk_ctrl =3D DPU_CLK_CTRL_RGB0, + }, { + .name =3D "sspp_5", .id =3D SSPP_RGB1, + .base =3D 0x16000, .len =3D 0x150, + .features =3D RGB_MSM8953_MASK, + .sblk =3D &dpu_rgb_sblk, + .xin_id =3D 5, + .type =3D SSPP_TYPE_RGB, + .clk_ctrl =3D DPU_CLK_CTRL_RGB1, + }, { + .name =3D "sspp_8", .id =3D SSPP_DMA0, + .base =3D 0x24000, .len =3D 0x150, + .features =3D DMA_MSM8953_MASK | BIT(DPU_SSPP_CURSOR), + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 2, + .type =3D SSPP_TYPE_DMA, + .clk_ctrl =3D DPU_CLK_CTRL_DMA0, + }, +}; + +static const struct dpu_lm_cfg msm8937_lm[] =3D { + { + .name =3D "lm_0", .id =3D LM_0, + .base =3D 0x44000, .len =3D 0x320, + .sblk =3D &msm8998_lm_sblk, + .lm_pair =3D LM_1, + .pingpong =3D PINGPONG_0, + .dspp =3D DSPP_0, + }, { + .name =3D "lm_1", .id =3D LM_1, + .base =3D 0x45000, .len =3D 0x320, + .sblk =3D &msm8998_lm_sblk, + .lm_pair =3D LM_0, + .pingpong =3D PINGPONG_1, + }, +}; + +static const struct dpu_pingpong_cfg msm8937_pp[] =3D { + { + .name =3D "pingpong_0", .id =3D PINGPONG_0, + .base =3D 0x70000, .len =3D 0xd4, + .features =3D PINGPONG_MSM8996_MASK, + .sblk =3D &msm8996_pp_sblk, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), + }, { + .name =3D "pingpong_1", .id =3D PINGPONG_1, + .base =3D 0x70800, .len =3D 0xd4, + .features =3D PINGPONG_MSM8996_MASK, + .sblk =3D &msm8996_pp_sblk, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), + }, +}; + +static const struct dpu_dspp_cfg msm8937_dspp[] =3D { + { + .name =3D "dspp_0", .id =3D DSPP_0, + .base =3D 0x54000, .len =3D 0x1800, + .features =3D DSPP_SC7180_MASK, + .sblk =3D &msm8998_dspp_sblk, + }, +}; + +static const struct dpu_intf_cfg msm8937_intf[] =3D { + { + .name =3D "intf_1", .id =3D INTF_1, + .base =3D 0x6a800, .len =3D 0x268, + .type =3D INTF_DSI, + .controller_id =3D MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 14, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr =3D -1, + }, { + .name =3D "intf_2", .id =3D INTF_2, + .base =3D 0x6b000, .len =3D 0x268, + .type =3D INTF_DSI, + .controller_id =3D MSM_DSI_CONTROLLER_1, + .prog_fetch_lines_worst_case =3D 14, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), + .intr_tear_rd_ptr =3D -1, + }, +}; + +static const struct dpu_perf_cfg msm8937_perf_data =3D { + .max_bw_low =3D 3100000, + .max_bw_high =3D 3100000, + .min_core_ib =3D 2400000, + .min_llcc_ib =3D 0, /* No LLCC on this SoC */ + .min_dram_ib =3D 800000, + .undersized_prefill_lines =3D 2, + .xtra_prefill_lines =3D 2, + .dest_scale_prefill_lines =3D 3, + .macrotile_prefill_lines =3D 4, + .yuv_nv12_prefill_lines =3D 8, + .linear_prefill_lines =3D 1, + .downscaling_prefill_lines =3D 1, + .amortizable_threshold =3D 25, + .min_prefill_lines =3D 14, + .danger_lut_tbl =3D {0xf, 0xffff, 0x0}, + .safe_lut_tbl =3D {0xfffc, 0xff00, 0xffff}, + .qos_lut_tbl =3D { + {.nentry =3D ARRAY_SIZE(msm8998_qos_linear), + .entries =3D msm8998_qos_linear + }, + {.nentry =3D ARRAY_SIZE(msm8998_qos_macrotile), + .entries =3D msm8998_qos_macrotile + }, + {.nentry =3D ARRAY_SIZE(msm8998_qos_nrt), + .entries =3D msm8998_qos_nrt + }, + }, + .cdp_cfg =3D { + {.rd_enable =3D 1, .wr_enable =3D 1}, + {.rd_enable =3D 1, .wr_enable =3D 0} + }, + .clk_inefficiency_factor =3D 105, + .bw_inefficiency_factor =3D 120, +}; + +static const struct dpu_mdss_version msm8937_mdss_ver =3D { + .core_major_ver =3D 1, + .core_minor_ver =3D 14, +}; + +const struct dpu_mdss_cfg dpu_msm8937_cfg =3D { + .mdss_ver =3D &msm8937_mdss_ver, + .caps =3D &msm8937_dpu_caps, + .mdp =3D msm8937_mdp, + .ctl_count =3D ARRAY_SIZE(msm8937_ctl), + .ctl =3D msm8937_ctl, + .sspp_count =3D ARRAY_SIZE(msm8937_sspp), + .sspp =3D msm8937_sspp, + .mixer_count =3D ARRAY_SIZE(msm8937_lm), + .mixer =3D msm8937_lm, + .dspp_count =3D ARRAY_SIZE(msm8937_dspp), + .dspp =3D msm8937_dspp, + .pingpong_count =3D ARRAY_SIZE(msm8937_pp), + .pingpong =3D msm8937_pp, + .intf_count =3D ARRAY_SIZE(msm8937_intf), + .intf =3D msm8937_intf, + .vbif_count =3D ARRAY_SIZE(msm8996_vbif), + .vbif =3D msm8996_vbif, + .perf =3D &msm8937_perf_data, +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 3049d7d15a34605455ad5f0db2cc118315c64bee..374d478faec4a08138f3e6cf2b3= 96996eb082baa 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -779,6 +779,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = =3D { *************************************************************/ =20 #include "catalog/dpu_1_7_msm8996.h" +#include "catalog/dpu_1_14_msm8937.h" #include "catalog/dpu_1_16_msm8953.h" =20 #include "catalog/dpu_3_0_msm8998.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 68c1364c3ffe10ddf784079006ece2d73e62a4bf..cd9cd27f816969cf95ecdc46d0f= 5821ba851294c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -831,6 +831,7 @@ struct dpu_mdss_cfg { const struct dpu_format_extended *vig_formats; }; =20 +extern const struct dpu_mdss_cfg dpu_msm8937_cfg; extern const struct dpu_mdss_cfg dpu_msm8953_cfg; extern const struct dpu_mdss_cfg dpu_msm8996_cfg; extern const struct dpu_mdss_cfg dpu_msm8998_cfg; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 33f6a854461eb63b4b14b6525e88799342a7df54..778d11d6cb63235456451bec83f= 0b1d9127861b8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1445,6 +1445,7 @@ static const struct dev_pm_ops dpu_pm_ops =3D { }; =20 static const struct of_device_id dpu_dt_match[] =3D { + { .compatible =3D "qcom,msm8937-mdp5", .data =3D &dpu_msm8937_cfg, }, { .compatible =3D "qcom,msm8953-mdp5", .data =3D &dpu_msm8953_cfg, }, { .compatible =3D "qcom,msm8996-mdp5", .data =3D &dpu_msm8996_cfg, }, { .compatible =3D "qcom,msm8998-dpu", .data =3D &dpu_msm8998_cfg, }, diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index ea2e39f002f2aa7871efcb0a3983069077a094b1..d7e51a7c25aad10629aee5166cd= 501693e8ec4fd 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -983,6 +983,7 @@ module_param(prefer_mdp5, bool, 0444); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240930-dpu-msm8953-msm8996-v2-4-594c3e3190b4@mainlining.org> References: <20240930-dpu-msm8953-msm8996-v2-0-594c3e3190b4@mainlining.org> In-Reply-To: <20240930-dpu-msm8953-msm8996-v2-0-594c3e3190b4@mainlining.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Simona Vetter Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727721359; l=8688; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=F2jqljH4/t6/YDSegE+tlioH0EQ6ekV53AbWjz1E41g=; b=t4asC6FtLq8RnAekUKGRLFiWf0A3277AWqbOOa1Z4TuYEeDGkNq/RpsKrnSTpArUcbR/AjFd2 kYagvoOQAt3D+EKcOHZro0oAfTCB7r1eqzMS1Kmmfbex3YFg/0UCT/W X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= From: Dmitry Baryshkov Add support for MSM8917, which has MDP5 v1.15. It looks like trimmed down version of MSM8937. Even fewer PP, LM and no DSI1. Signed-off-by: Dmitry Baryshkov [Remove intr_start from CTLs config, reword the commit] Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n Reviewed-by: Dmitry Baryshkov --- .../drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h | 187 +++++++++++++++++= ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + drivers/gpu/drm/msm/msm_drv.c | 1 + 5 files changed, 191 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h new file mode 100644 index 0000000000000000000000000000000000000000..6bdaecca676144f9162ab1839d9= 9f3e2e3386dc7 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h @@ -0,0 +1,187 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DPU_1_14_MSM8917_H +#define _DPU_1_14_MSM8917_H + +static const struct dpu_caps msm8917_dpu_caps =3D { + .max_mixer_width =3D DEFAULT_DPU_LINE_WIDTH, + .max_mixer_blendstages =3D 0x4, + .max_linewidth =3D DEFAULT_DPU_LINE_WIDTH, + .pixel_ram_size =3D 16 * 1024, + .max_hdeci_exp =3D MAX_HORZ_DECIMATION, + .max_vdeci_exp =3D MAX_VERT_DECIMATION, +}; + +static const struct dpu_mdp_cfg msm8917_mdp[] =3D { + { + .name =3D "top_0", + .base =3D 0x0, .len =3D 0x454, + .features =3D BIT(DPU_MDP_VSYNC_SEL), + .clk_ctrls =3D { + [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, + [DPU_CLK_CTRL_RGB0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 4 }, + [DPU_CLK_CTRL_RGB1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 4 }, + [DPU_CLK_CTRL_DMA0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 8 }, + [DPU_CLK_CTRL_CURSOR0] =3D { .reg_off =3D 0x3a8, .bit_off =3D 16 }, + }, + }, +}; + +static const struct dpu_ctl_cfg msm8917_ctl[] =3D { + { + .name =3D "ctl_0", .id =3D CTL_0, + .base =3D 0x1000, .len =3D 0x64, + }, { + .name =3D "ctl_1", .id =3D CTL_1, + .base =3D 0x1200, .len =3D 0x64, + }, { + .name =3D "ctl_2", .id =3D CTL_2, + .base =3D 0x1400, .len =3D 0x64, + }, +}; + +static const struct dpu_sspp_cfg msm8917_sspp[] =3D { + { + .name =3D "sspp_0", .id =3D SSPP_VIG0, + .base =3D 0x4000, .len =3D 0x150, + .features =3D VIG_MSM8953_MASK, + .sblk =3D &dpu_vig_sblk_qseed2, + .xin_id =3D 0, + .type =3D SSPP_TYPE_VIG, + .clk_ctrl =3D DPU_CLK_CTRL_VIG0, + }, { + .name =3D "sspp_4", .id =3D SSPP_RGB0, + .base =3D 0x14000, .len =3D 0x150, + .features =3D RGB_MSM8953_MASK, + .sblk =3D &dpu_rgb_sblk, + .xin_id =3D 1, + .type =3D SSPP_TYPE_RGB, + .clk_ctrl =3D DPU_CLK_CTRL_RGB0, + }, { + .name =3D "sspp_5", .id =3D SSPP_RGB1, + .base =3D 0x16000, .len =3D 0x150, + .features =3D RGB_MSM8953_MASK, + .sblk =3D &dpu_rgb_sblk, + .xin_id =3D 5, + .type =3D SSPP_TYPE_RGB, + .clk_ctrl =3D DPU_CLK_CTRL_RGB1, + }, { + .name =3D "sspp_8", .id =3D SSPP_DMA0, + .base =3D 0x24000, .len =3D 0x150, + .features =3D DMA_MSM8953_MASK | BIT(DPU_SSPP_CURSOR), + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 2, + .type =3D SSPP_TYPE_DMA, + .clk_ctrl =3D DPU_CLK_CTRL_DMA0, + }, +}; + +static const struct dpu_lm_cfg msm8917_lm[] =3D { + { + .name =3D "lm_0", .id =3D LM_0, + .base =3D 0x44000, .len =3D 0x320, + .sblk =3D &msm8998_lm_sblk, + .pingpong =3D PINGPONG_0, + .dspp =3D DSPP_0, + }, +}; + +static const struct dpu_pingpong_cfg msm8917_pp[] =3D { + { + .name =3D "pingpong_0", .id =3D PINGPONG_0, + .base =3D 0x70000, .len =3D 0xd4, + .features =3D PINGPONG_MSM8996_MASK, + .sblk =3D &msm8996_pp_sblk, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), + }, +}; + +static const struct dpu_dspp_cfg msm8917_dspp[] =3D { + { + .name =3D "dspp_0", .id =3D DSPP_0, + .base =3D 0x54000, .len =3D 0x1800, + .features =3D DSPP_SC7180_MASK, + .sblk =3D &msm8998_dspp_sblk, + }, +}; + +static const struct dpu_intf_cfg msm8917_intf[] =3D { + { + .name =3D "intf_1", .id =3D INTF_1, + .base =3D 0x6a800, .len =3D 0x268, + .type =3D INTF_DSI, + .controller_id =3D MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 14, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr =3D -1, + }, +}; + +static const struct dpu_perf_cfg msm8917_perf_data =3D { + .max_bw_low =3D 1800000, + .max_bw_high =3D 1800000, + .min_core_ib =3D 2400000, + .min_llcc_ib =3D 0, /* No LLCC on this SoC */ + .min_dram_ib =3D 800000, + .undersized_prefill_lines =3D 2, + .xtra_prefill_lines =3D 2, + .dest_scale_prefill_lines =3D 3, + .macrotile_prefill_lines =3D 4, + .yuv_nv12_prefill_lines =3D 8, + .linear_prefill_lines =3D 1, + .downscaling_prefill_lines =3D 1, + .amortizable_threshold =3D 25, + .min_prefill_lines =3D 21, + .danger_lut_tbl =3D {0xf, 0xffff, 0x0}, + .safe_lut_tbl =3D {0xfffc, 0xff00, 0xffff}, + .qos_lut_tbl =3D { + {.nentry =3D ARRAY_SIZE(msm8998_qos_linear), + .entries =3D msm8998_qos_linear + }, + {.nentry =3D ARRAY_SIZE(msm8998_qos_macrotile), + .entries =3D msm8998_qos_macrotile + }, + {.nentry =3D ARRAY_SIZE(msm8998_qos_nrt), + .entries =3D msm8998_qos_nrt + }, + }, + .cdp_cfg =3D { + {.rd_enable =3D 1, .wr_enable =3D 1}, + {.rd_enable =3D 1, .wr_enable =3D 0} + }, + .clk_inefficiency_factor =3D 105, + .bw_inefficiency_factor =3D 120, +}; + +static const struct dpu_mdss_version msm8917_mdss_ver =3D { + .core_major_ver =3D 1, + .core_minor_ver =3D 15, +}; + +const struct dpu_mdss_cfg dpu_msm8917_cfg =3D { + .mdss_ver =3D &msm8917_mdss_ver, + .caps =3D &msm8917_dpu_caps, + .mdp =3D msm8917_mdp, + .ctl_count =3D ARRAY_SIZE(msm8917_ctl), + .ctl =3D msm8917_ctl, + .sspp_count =3D ARRAY_SIZE(msm8917_sspp), + .sspp =3D msm8917_sspp, + .mixer_count =3D ARRAY_SIZE(msm8917_lm), + .mixer =3D msm8917_lm, + .dspp_count =3D ARRAY_SIZE(msm8917_dspp), + .dspp =3D msm8917_dspp, + .pingpong_count =3D ARRAY_SIZE(msm8917_pp), + .pingpong =3D msm8917_pp, + .intf_count =3D ARRAY_SIZE(msm8917_intf), + .intf =3D msm8917_intf, + .vbif_count =3D ARRAY_SIZE(msm8996_vbif), + .vbif =3D msm8996_vbif, + .perf =3D &msm8917_perf_data, +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 374d478faec4a08138f3e6cf2b396996eb082baa..431754b1187b455a69ecd0b3e51= 3f793087e2869 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -780,6 +780,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = =3D { =20 #include "catalog/dpu_1_7_msm8996.h" #include "catalog/dpu_1_14_msm8937.h" +#include "catalog/dpu_1_15_msm8917.h" #include "catalog/dpu_1_16_msm8953.h" =20 #include "catalog/dpu_3_0_msm8998.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index cd9cd27f816969cf95ecdc46d0f5821ba851294c..3dab1e1b8f72e3112f00c782527= 335af9a1d77c8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -831,6 +831,7 @@ struct dpu_mdss_cfg { const struct dpu_format_extended *vig_formats; }; =20 +extern const struct dpu_mdss_cfg dpu_msm8917_cfg; extern const struct dpu_mdss_cfg dpu_msm8937_cfg; extern const struct dpu_mdss_cfg dpu_msm8953_cfg; extern const struct dpu_mdss_cfg dpu_msm8996_cfg; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 778d11d6cb63235456451bec83f0b1d9127861b8..ecd66146d5e14a6b114d08e0fa4= f8fe7a13ada66 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1445,6 +1445,7 @@ static const struct dev_pm_ops dpu_pm_ops =3D { }; =20 static const struct of_device_id dpu_dt_match[] =3D { + { .compatible =3D "qcom,msm8917-mdp5", .data =3D &dpu_msm8917_cfg, }, { .compatible =3D "qcom,msm8937-mdp5", .data =3D &dpu_msm8937_cfg, }, { .compatible =3D "qcom,msm8953-mdp5", .data =3D &dpu_msm8953_cfg, }, { .compatible =3D "qcom,msm8996-mdp5", .data =3D &dpu_msm8996_cfg, }, diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index d7e51a7c25aad10629aee5166cd501693e8ec4fd..3557cf7af303fd8c744f60d4981= 5aebc7da41841 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -983,6 +983,7 @@ module_param(prefer_mdp5, bool, 0444); =20 /* list all platforms supported by both mdp5 and dpu drivers */ static const char *const msm_mdp5_dpu_migration[] =3D { + "qcom,msm8917-mdp5", "qcom,msm8937-mdp5", "qcom,msm8953-mdp5", "qcom,msm8996-mdp5", --=20 2.46.2