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[79.54.102.102]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a93c27776a1sm403176866b.8.2024.09.29.10.27.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Sep 2024 10:27:47 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , Stephen Boyd , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v2 1/6] dt-bindings: clock: imx8m-anatop: support spread spectrum clocking Date: Sun, 29 Sep 2024 19:27:11 +0200 Message-ID: <20240929172743.1758292-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240929172743.1758292-1-dario.binacchi@amarulasolutions.com> References: <20240929172743.1758292-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The patch adds the DT bindings for enabling and tuning spread spectrum clocking generation. Signed-off-by: Dario Binacchi --- Changes in v2: - Add "allOf:" and place it after "required:" block, like in the example schema. - Move the properties definition to the top-level. - Drop unit types as requested by the "make dt_binding_check" command. .../bindings/clock/fsl,imx8m-anatop.yaml | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml = b/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml index bbd22e95b319..a142c04fef00 100644 --- a/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml +++ b/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml @@ -33,11 +33,56 @@ properties: '#clock-cells': const: 1 =20 + fsl,ssc-clocks: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + List of phandle and clock specifier pairs of PLLs with spread + spectrum generation hardware capability. + maxItems: 4 + + fsl,ssc-modfreq-hz: + description: + The values of modulation frequency (Hz unit) of spread spectrum + clocking for each PLL. + maxItems: 4 + + fsl,ssc-modrate-percent: + description: + The percentage values of modulation rate of spread spectrum + clocking for each PLL. + maxItems: 4 + + fsl,ssc-modmethod: + $ref: /schemas/types.yaml#/definitions/string-array + description: + The modulation techniques of spread spectrum clocking for + each PLL. + oneOf: + - enum: + - down-spread + - up-spread + - center-spread + maxItems: 4 + required: - compatible - reg - '#clock-cells' =20 +allOf: + - if: + not: + properties: + compatible: + contains: + const: fsl,imx8mm-anatop + then: + properties: + fsl,ssc-clocks: false + fsl,ssc-modfreq-hz: false + fsl,ssc-modrate-percent: false + fsl,ssc-modmethod: false + additionalProperties: false =20 examples: --=20 2.43.0 From nobody Thu Nov 28 17:48:46 2024 Received: from mail-ej1-f50.google.com (mail-ej1-f50.google.com [209.85.218.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCA153398B for ; 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[79.54.102.102]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a93c27776a1sm403176866b.8.2024.09.29.10.27.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Sep 2024 10:27:48 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v2 2/6] clk: imx: pll14xx: support spread spectrum clock generation Date: Sun, 29 Sep 2024 19:27:12 +0200 Message-ID: <20240929172743.1758292-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240929172743.1758292-1-dario.binacchi@amarulasolutions.com> References: <20240929172743.1758292-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch adds support for spread spectrum clock (SSC) generation for the pll14xxx. The addition of the "imx_clk_hw_pll14xx_ssc" macro has minimized the number of changes required to avoid compilation errors following the addition of the SSC setup parameter to the "imx_dev_clk_hw_pll14xx" macro used in the files clk-imx8m{m,n,p}.c. The change to the clk-imx8mp-audiomix.c file prevents the patch from causing a compilation error. Signed-off-by: Dario Binacchi --- (no changes since v1) drivers/clk/imx/clk-imx8mp-audiomix.c | 2 +- drivers/clk/imx/clk-pll14xx.c | 102 +++++++++++++++++++++++++- drivers/clk/imx/clk.h | 24 +++++- 3 files changed, 124 insertions(+), 4 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mp-audiomix.c b/drivers/clk/imx/clk-im= x8mp-audiomix.c index b2cb157703c5..bfcf2975c217 100644 --- a/drivers/clk/imx/clk-imx8mp-audiomix.c +++ b/drivers/clk/imx/clk-imx8mp-audiomix.c @@ -365,7 +365,7 @@ static int clk_imx8mp_audiomix_probe(struct platform_de= vice *pdev) clk_hw_data->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL] =3D hw; =20 hw =3D imx_dev_clk_hw_pll14xx(dev, "sai_pll", "sai_pll_ref_sel", - base + 0x400, &imx_1443x_pll); + base + 0x400, &imx_1443x_pll, NULL); if (IS_ERR(hw)) { ret =3D PTR_ERR(hw); goto err_clk_register; diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index d63564dbb12c..76014e243a57 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -20,6 +20,8 @@ #define GNRL_CTL 0x0 #define DIV_CTL0 0x4 #define DIV_CTL1 0x8 +#define SSCG_CTRL 0xc + #define LOCK_STATUS BIT(31) #define LOCK_SEL_MASK BIT(29) #define CLKE_MASK BIT(11) @@ -31,6 +33,10 @@ #define KDIV_MASK GENMASK(15, 0) #define KDIV_MIN SHRT_MIN #define KDIV_MAX SHRT_MAX +#define SSCG_ENABLE BIT(31) +#define MFREQ_CTL_MASK GENMASK(19, 12) +#define MRAT_CTL_MASK GENMASK(9, 4) +#define SEL_PF_MASK GENMASK(1, 0) =20 #define LOCK_TIMEOUT_US 10000 =20 @@ -40,6 +46,7 @@ struct clk_pll14xx { enum imx_pll14xx_type type; const struct imx_pll14xx_rate_table *rate_table; int rate_count; + struct imx_pll14xx_ssc ssc; }; =20 #define to_clk_pll14xx(_hw) container_of(_hw, struct clk_pll14xx, hw) @@ -347,6 +354,27 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, un= signed long drate, return 0; } =20 +static void clk_pll1443x_set_sscg(struct clk_hw *hw, unsigned long parent_= rate, + unsigned int pdiv, unsigned int mdiv) +{ + struct clk_pll14xx *pll =3D to_clk_pll14xx(hw); + struct imx_pll14xx_ssc *ssc =3D &pll->ssc; + u32 sscg_ctrl =3D readl_relaxed(pll->base + SSCG_CTRL); + + sscg_ctrl &=3D + ~(SSCG_ENABLE | MFREQ_CTL_MASK | MRAT_CTL_MASK | SEL_PF_MASK); + if (ssc->enable) { + u32 mfr =3D parent_rate / (ssc->mod_freq * pdiv * (1 << 5)); + u32 mrr =3D (ssc->mod_rate * mdiv * (1 << 6)) / (100 * mfr); + + sscg_ctrl |=3D SSCG_ENABLE | FIELD_PREP(MFREQ_CTL_MASK, mfr) | + FIELD_PREP(MRAT_CTL_MASK, mrr) | + FIELD_PREP(SEL_PF_MASK, ssc->mod_type); + } + + writel_relaxed(sscg_ctrl, pll->base + SSCG_CTRL); +} + static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) { @@ -368,6 +396,9 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, uns= igned long drate, writel_relaxed(FIELD_PREP(KDIV_MASK, rate.kdiv), pll->base + DIV_CTL1); =20 + if (pll->ssc.enable) + clk_pll1443x_set_sscg(hw, prate, rate.pdiv, rate.mdiv); + return 0; } =20 @@ -408,6 +439,9 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, uns= igned long drate, gnrl_ctl &=3D ~BYPASS_MASK; writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL); =20 + if (pll->ssc.enable) + clk_pll1443x_set_sscg(hw, prate, rate.pdiv, rate.mdiv); + return 0; } =20 @@ -487,7 +521,8 @@ static const struct clk_ops clk_pll1443x_ops =3D { =20 struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, const char *parent_name, void __iomem *base, - const struct imx_pll14xx_clk *pll_clk) + const struct imx_pll14xx_clk *pll_clk, + const struct imx_pll14xx_ssc *ssc) { struct clk_pll14xx *pll; struct clk_hw *hw; @@ -525,6 +560,8 @@ struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *de= v, const char *name, pll->type =3D pll_clk->type; pll->rate_table =3D pll_clk->rate_table; pll->rate_count =3D pll_clk->rate_count; + if (ssc) + memcpy(&pll->ssc, ssc, sizeof(pll->ssc)); =20 val =3D readl_relaxed(pll->base + GNRL_CTL); val &=3D ~BYPASS_MASK; @@ -542,3 +579,66 @@ struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *d= ev, const char *name, return hw; } EXPORT_SYMBOL_GPL(imx_dev_clk_hw_pll14xx); + +static enum imx_pll14xx_ssc_mod_type clk_pll14xx_ssc_mode(const char *name, + enum imx_pll14xx_ssc_mod_type def) +{ + int i; + struct { + const char *name; + enum imx_pll14xx_ssc_mod_type id; + } mod_methods[] =3D { + { .name =3D "down-spread", .id =3D IMX_PLL14XX_SSC_DOWN_SPREAD }, + { .name =3D "up-spread", .id =3D IMX_PLL14XX_SSC_UP_SPREAD }, + { .name =3D "center-spread", .id =3D IMX_PLL14XX_SSC_CENTER_SPREAD } + }; + + for (i =3D 0; i < ARRAY_SIZE(mod_methods); i++) { + if (!strcmp(name, mod_methods[i].name)) + return mod_methods[i].id; + } + + return def; +} + +void imx_clk_pll14xx_get_ssc_conf(struct device_node *np, int pll_id, + struct imx_pll14xx_ssc *ssc) +{ + int i, ret, offset, num_clks; + u32 clk_id, clk_cell_size; + const char *s; + + if (!ssc) + return; + + memset(ssc, 0, sizeof(*ssc)); + + num_clks =3D of_count_phandle_with_args(np, "fsl,ssc-clocks", + "#clock-cells"); + if (num_clks <=3D 0) + return; + + ret =3D of_property_read_u32(np, "#clock-cells", &clk_cell_size); + if (ret) + return; + + for (i =3D 0; i < num_clks; i++) { + offset =3D i * clk_cell_size + 1; + of_property_read_u32_index(np, "fsl,ssc-clocks", offset, + &clk_id); + if (clk_id !=3D pll_id) + continue; + + of_property_read_u32_index(np, "fsl,ssc-modfreq-hz", i, + &ssc->mod_freq); + of_property_read_u32_index(np, "fsl,ssc-modrate-percent", i, + &ssc->mod_rate); + if (!of_property_read_string(np, "fsl,ssc-modmethod", &s)) + ssc->mod_type =3D clk_pll14xx_ssc_mode( + s, IMX_PLL14XX_SSC_DOWN_SPREAD); + + ssc->enable =3D true; + break; + } +} +EXPORT_SYMBOL_GPL(imx_clk_pll14xx_get_ssc_conf); diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index aa5202f284f3..8cbc75480569 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -62,6 +62,19 @@ struct imx_pll14xx_rate_table { unsigned int kdiv; }; =20 +enum imx_pll14xx_ssc_mod_type { + IMX_PLL14XX_SSC_DOWN_SPREAD, + IMX_PLL14XX_SSC_UP_SPREAD, + IMX_PLL14XX_SSC_CENTER_SPREAD, +}; + +struct imx_pll14xx_ssc { + bool enable; + unsigned int mod_freq; + unsigned int mod_rate; + enum imx_pll14xx_ssc_mod_type mod_type; +}; + struct imx_pll14xx_clk { enum imx_pll14xx_type type; const struct imx_pll14xx_rate_table *rate_table; @@ -222,11 +235,18 @@ extern struct imx_fracn_gppll_clk imx_fracn_gppll_int= eger; __imx_clk_hw_divider(name, parent, reg, shift, width, flags) =20 #define imx_clk_hw_pll14xx(name, parent_name, base, pll_clk) \ - imx_dev_clk_hw_pll14xx(NULL, name, parent_name, base, pll_clk) + imx_dev_clk_hw_pll14xx(NULL, name, parent_name, base, pll_clk, NULL) + +#define imx_clk_hw_pll14xx_ssc(name, parent_name, base, pll_clk, ssc) \ + imx_dev_clk_hw_pll14xx(NULL, name, parent_name, base, pll_clk, ssc) =20 struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, const char *parent_name, void __iomem *base, - const struct imx_pll14xx_clk *pll_clk); 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[79.54.102.102]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a93c27776a1sm403176866b.8.2024.09.29.10.27.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Sep 2024 10:27:50 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v2 3/6] clk: imx8mm: support spread spectrum clock generation Date: Sun, 29 Sep 2024 19:27:13 +0200 Message-ID: <20240929172743.1758292-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240929172743.1758292-1-dario.binacchi@amarulasolutions.com> References: <20240929172743.1758292-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The patch adds support for spread spectrum clock generation for the audio, video, and DRAM PLLs. Signed-off-by: Dario Binacchi --- (no changes since v1) drivers/clk/imx/clk-imx8mm.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 342049b847b9..0acf2979c929 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -301,6 +301,7 @@ static int imx8mm_clocks_probe(struct platform_device *= pdev) struct device *dev =3D &pdev->dev; struct device_node *np =3D dev->of_node; void __iomem *base; + struct imx_pll14xx_ssc pll1443x_ssc; int ret; =20 clk_hw_data =3D kzalloc(struct_size(clk_hw_data, hws, @@ -334,10 +335,14 @@ static int imx8mm_clocks_probe(struct platform_device= *pdev) hws[IMX8MM_ARM_PLL_REF_SEL] =3D imx_clk_hw_mux("arm_pll_ref_sel", base + = 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MM_SYS_PLL3_REF_SEL] =3D imx_clk_hw_mux("sys_pll3_ref_sel", base = + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); =20 - hws[IMX8MM_AUDIO_PLL1] =3D imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_r= ef_sel", base, &imx_1443x_pll); - hws[IMX8MM_AUDIO_PLL2] =3D imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_r= ef_sel", base + 0x14, &imx_1443x_pll); - hws[IMX8MM_VIDEO_PLL1] =3D imx_clk_hw_pll14xx("video_pll1", "video_pll1_r= ef_sel", base + 0x28, &imx_1443x_pll); - hws[IMX8MM_DRAM_PLL] =3D imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel= ", base + 0x50, &imx_1443x_dram_pll); + imx_clk_pll14xx_get_ssc_conf(np, IMX8MM_AUDIO_PLL1, &pll1443x_ssc); + hws[IMX8MM_AUDIO_PLL1] =3D imx_clk_hw_pll14xx_ssc("audio_pll1", "audio_pl= l1_ref_sel", base, &imx_1443x_pll, &pll1443x_ssc); + imx_clk_pll14xx_get_ssc_conf(np, IMX8MM_AUDIO_PLL2, &pll1443x_ssc); + hws[IMX8MM_AUDIO_PLL2] =3D imx_clk_hw_pll14xx_ssc("audio_pll2", "audio_pl= l2_ref_sel", base + 0x14, &imx_1443x_pll, &pll1443x_ssc); + imx_clk_pll14xx_get_ssc_conf(np, IMX8MM_VIDEO_PLL1, &pll1443x_ssc); + hws[IMX8MM_VIDEO_PLL1] =3D imx_clk_hw_pll14xx_ssc("video_pll1", "video_pl= l1_ref_sel", base + 0x28, &imx_1443x_pll, &pll1443x_ssc); + imx_clk_pll14xx_get_ssc_conf(np, IMX8MM_DRAM_PLL, &pll1443x_ssc); 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[79.54.102.102]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a93c27776a1sm403176866b.8.2024.09.29.10.27.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Sep 2024 10:27:51 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v2 4/6] clk: imx8mn: support spread spectrum clock generation Date: Sun, 29 Sep 2024 19:27:14 +0200 Message-ID: <20240929172743.1758292-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240929172743.1758292-1-dario.binacchi@amarulasolutions.com> References: <20240929172743.1758292-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The patch adds support for spread spectrum clock generation for the audio, video, and DRAM PLLs. Signed-off-by: Dario Binacchi --- (no changes since v1) drivers/clk/imx/clk-imx8mn.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index ab77e148e70c..b33590a9b7b7 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -321,6 +321,7 @@ static int imx8mn_clocks_probe(struct platform_device *= pdev) struct device *dev =3D &pdev->dev; struct device_node *np =3D dev->of_node; void __iomem *base; + struct imx_pll14xx_ssc pll1443x_ssc; int ret; =20 clk_hw_data =3D devm_kzalloc(dev, struct_size(clk_hw_data, hws, @@ -356,10 +357,14 @@ static int imx8mn_clocks_probe(struct platform_device= *pdev) hws[IMX8MN_ARM_PLL_REF_SEL] =3D imx_clk_hw_mux("arm_pll_ref_sel", base + = 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MN_SYS_PLL3_REF_SEL] =3D imx_clk_hw_mux("sys_pll3_ref_sel", base = + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); =20 - hws[IMX8MN_AUDIO_PLL1] =3D imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_r= ef_sel", base, &imx_1443x_pll); - hws[IMX8MN_AUDIO_PLL2] =3D imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_r= ef_sel", base + 0x14, &imx_1443x_pll); - hws[IMX8MN_VIDEO_PLL] =3D imx_clk_hw_pll14xx("video_pll", "video_pll_ref_= sel", base + 0x28, &imx_1443x_pll); - hws[IMX8MN_DRAM_PLL] =3D imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel= ", base + 0x50, &imx_1443x_dram_pll); + imx_clk_pll14xx_get_ssc_conf(np, IMX8MN_AUDIO_PLL1, &pll1443x_ssc); + hws[IMX8MN_AUDIO_PLL1] =3D imx_clk_hw_pll14xx_ssc("audio_pll1", "audio_pl= l1_ref_sel", base, &imx_1443x_pll, &pll1443x_ssc); + imx_clk_pll14xx_get_ssc_conf(np, IMX8MN_AUDIO_PLL2, &pll1443x_ssc); + hws[IMX8MN_AUDIO_PLL2] =3D imx_clk_hw_pll14xx_ssc("audio_pll2", "audio_pl= l2_ref_sel", base + 0x14, &imx_1443x_pll, &pll1443x_ssc); + imx_clk_pll14xx_get_ssc_conf(np, IMX8MN_VIDEO_PLL, &pll1443x_ssc); + hws[IMX8MN_VIDEO_PLL] =3D imx_clk_hw_pll14xx_ssc("video_pll", "video_pll_= ref_sel", base + 0x28, &imx_1443x_pll, &pll1443x_ssc); + imx_clk_pll14xx_get_ssc_conf(np, IMX8MN_DRAM_PLL, &pll1443x_ssc); + hws[IMX8MN_DRAM_PLL] =3D imx_clk_hw_pll14xx_ssc("dram_pll", "dram_pll_ref= _sel", base + 0x50, &imx_1443x_dram_pll, &pll1443x_ssc); hws[IMX8MN_GPU_PLL] =3D imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", = base + 0x64, &imx_1416x_pll); hws[IMX8MN_M7_ALT_PLL] =3D imx_clk_hw_pll14xx("m7_alt_pll", "m7_alt_pll_r= ef_sel", base + 0x74, &imx_1416x_pll); hws[IMX8MN_ARM_PLL] =3D imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", = base + 0x84, &imx_1416x_pll); --=20 2.43.0 From nobody Thu Nov 28 17:48:46 2024 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 351ED43155 for ; Sun, 29 Sep 2024 17:27:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727630877; cv=none; b=th4MZq6JRO8ohGzZoISbzBwQZr+QsbnudE60nz9/6blUpI1gYksD66ZUEVDyyT8CYWMCg4wtWE7JWt3S6Ftd/XI32ZHg5B2YuiS/DHTCiBZBcQwaJhnOotRD1826YL88o0cZKG0g1mQNl7lyi8t0OgFdbRe0Khg9uxbRhI+3WpQ= ARC-Message-Signature: i=1; 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[79.54.102.102]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a93c27776a1sm403176866b.8.2024.09.29.10.27.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Sep 2024 10:27:53 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v2 5/6] clk: imx8mp: don't lose the anatop device node Date: Sun, 29 Sep 2024 19:27:15 +0200 Message-ID: <20240929172743.1758292-6-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240929172743.1758292-1-dario.binacchi@amarulasolutions.com> References: <20240929172743.1758292-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Setting the "clk" (clock-controller@30380000) device node caused the reference to the "anatop" (clock-controller@30360000) device node to be lost. This patch, similar to what was already done for the base address, now distinguishes between the "anatop" device node and the "clk" device node. This change is preparatory for future developments. Signed-off-by: Dario Binacchi --- (no changes since v1) drivers/clk/imx/clk-imx8mp.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 516dbd170c8a..b2778958a572 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -408,13 +408,13 @@ static struct clk_hw_onecell_data *clk_hw_data; static int imx8mp_clocks_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; - struct device_node *np; + struct device_node *np, *anatop_np; void __iomem *anatop_base, *ccm_base; int err; =20 - np =3D of_find_compatible_node(NULL, NULL, "fsl,imx8mp-anatop"); - anatop_base =3D devm_of_iomap(dev, np, 0, NULL); - of_node_put(np); + anatop_np =3D of_find_compatible_node(NULL, NULL, "fsl,imx8mp-anatop"); + anatop_base =3D devm_of_iomap(dev, anatop_np, 0, NULL); + of_node_put(anatop_np); if (WARN_ON(IS_ERR(anatop_base))) return PTR_ERR(anatop_base); =20 --=20 2.43.0 From nobody Thu Nov 28 17:48:46 2024 Received: from mail-ej1-f50.google.com (mail-ej1-f50.google.com [209.85.218.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F4C95466B for ; Sun, 29 Sep 2024 17:27:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727630880; cv=none; b=WgM9C1OToI1RwX1ZGkWddNAjCDOJAcbakJ/uVWdeTYA6mLWWwPNuaYlE9LWS86kkUK18xv8e3TE7gfIT44AzvglgsXGQ+4PU0jPCFvqotWO9h8J5uVx1iRVzQr/wYwc1g4Vd6wbAQAXJ1PnYWVYCr+ACoEig1iNdDFQqNVg/mW4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727630880; c=relaxed/simple; bh=Ug7wY8jPGPHXKlaEJWDLzwP2YJRZZ0pjcvr+/Y2WFTE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Z7bP+ifeZ0cQ84jeDKESVDgYFQXNQxvMLO3iLMzV4AVMUxRoI8e200+/0wWZOGp5cwAhNKhhoQNBBWpnQfRJYr06yy+5M9aYuKeUh+kRuKKet78II5AQDw7EjWb/x7CIPZ7FsWF6i0zkGLkghs5Y4Aw1V4NMOaqmDb+3wLA9apQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=mjd9rIgy; arc=none smtp.client-ip=209.85.218.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="mjd9rIgy" Received: by mail-ej1-f50.google.com with SMTP id a640c23a62f3a-a8b155b5e9eso575185566b.1 for ; Sun, 29 Sep 2024 10:27:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1727630876; x=1728235676; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=y0iBp/WuiGBbwsQFlblUsJsTztRh00umfcE38KK4N/I=; b=mjd9rIgyX9GxmSpEmUu7uwgD2LDP/qz66a0VwV6m1I5pXL5w6KlKTcDFKd4sy0LA6O SHIY8R7bhLuLzI636+w9O5cNQLadR8VK7LcqxgUSLdY0GqLtBxy5ofdyd9DSTTpKf5Xd hhs2AQIVkO2MnxB6xjDGjSWevJAhcJTCj3J7A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727630876; x=1728235676; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=y0iBp/WuiGBbwsQFlblUsJsTztRh00umfcE38KK4N/I=; b=pjk1GDVqew/+TXxKw7fKKIiY416WBEkzjqWtsq4+6dvxPQZPHdZ3238L/+gP5FzTvO 3FIltPcDtVjw2CVJNAOI399NSxPdSyelwtMCNC+IcJruMlF/HYb94rhc+XKZydmJQjbv UXBgPghUVCNXmHHUXmxA089gl0rDGpfIPE+m6KAP0Gj1bDv5DIvMmdCQ8ETdYt7W7du1 8kNrq2Kt0X2n69wnZS9RR63EU7vFNdgSN01qVu2WBvEC4KuSLlT1eMsazm7PfWbKPehA FeDPu7M/lW2e07VyD7vVKT2/yNBgodx1jNGvnxOPaLlyLVrf+PYBVX2KcbPwPRfNOsQS g6uA== X-Gm-Message-State: AOJu0Yx4A2mGbu6fnxFYVHJbseLNZBOrOBlrEwXsC6uPO5VMtHcXx/UT HsyhsoI0JzFJImE4sJhdIKVruBxiTg53TaGrhxc8HmsCaxgjuWXoQboHRo+XOv80V+Qcn7GWPjm IghE= X-Google-Smtp-Source: AGHT+IGLXVyYvBPaOSAKwxQv4nClWIr3rmZocj2kb4LCU/k1nVaoIjd/hf0Piycmvcx3tLSB+8EClg== X-Received: by 2002:a17:907:6d20:b0:a8a:8c92:1c9c with SMTP id a640c23a62f3a-a93c4967869mr949147066b.29.1727630876427; Sun, 29 Sep 2024 10:27:56 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-79-54-102-102.retail.telecomitalia.it. [79.54.102.102]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a93c27776a1sm403176866b.8.2024.09.29.10.27.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Sep 2024 10:27:55 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v2 6/6] clk: imx8mp: support spread spectrum clock generation Date: Sun, 29 Sep 2024 19:27:16 +0200 Message-ID: <20240929172743.1758292-7-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240929172743.1758292-1-dario.binacchi@amarulasolutions.com> References: <20240929172743.1758292-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The patch adds support for spread spectrum clock generation for the audio, video, and DRAM PLLs. Signed-off-by: Dario Binacchi --- (no changes since v1) drivers/clk/imx/clk-imx8mp.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index b2778958a572..460e8271def5 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -410,6 +410,7 @@ static int imx8mp_clocks_probe(struct platform_device *= pdev) struct device *dev =3D &pdev->dev; struct device_node *np, *anatop_np; void __iomem *anatop_base, *ccm_base; + struct imx_pll14xx_ssc pll1443x_ssc; int err; =20 anatop_np =3D of_find_compatible_node(NULL, NULL, "fsl,imx8mp-anatop"); @@ -449,10 +450,14 @@ static int imx8mp_clocks_probe(struct platform_device= *pdev) hws[IMX8MP_SYS_PLL2_REF_SEL] =3D imx_clk_hw_mux("sys_pll2_ref_sel", anato= p_base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MP_SYS_PLL3_REF_SEL] =3D imx_clk_hw_mux("sys_pll3_ref_sel", anato= p_base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); =20 - hws[IMX8MP_AUDIO_PLL1] =3D imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_r= ef_sel", anatop_base, &imx_1443x_pll); - hws[IMX8MP_AUDIO_PLL2] =3D imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_r= ef_sel", anatop_base + 0x14, &imx_1443x_pll); - hws[IMX8MP_VIDEO_PLL1] =3D imx_clk_hw_pll14xx("video_pll1", "video_pll1_r= ef_sel", anatop_base + 0x28, &imx_1443x_pll); - hws[IMX8MP_DRAM_PLL] =3D imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel= ", anatop_base + 0x50, &imx_1443x_dram_pll); + imx_clk_pll14xx_get_ssc_conf(anatop_np, IMX8MP_AUDIO_PLL1, &pll1443x_ssc); + hws[IMX8MP_AUDIO_PLL1] =3D imx_clk_hw_pll14xx_ssc("audio_pll1", "audio_pl= l1_ref_sel", anatop_base, &imx_1443x_pll, &pll1443x_ssc); + imx_clk_pll14xx_get_ssc_conf(anatop_np, IMX8MP_AUDIO_PLL2, &pll1443x_ssc); + hws[IMX8MP_AUDIO_PLL2] =3D imx_clk_hw_pll14xx_ssc("audio_pll2", "audio_pl= l2_ref_sel", anatop_base + 0x14, &imx_1443x_pll, &pll1443x_ssc); + imx_clk_pll14xx_get_ssc_conf(anatop_np, IMX8MP_VIDEO_PLL1, &pll1443x_ssc); + hws[IMX8MP_VIDEO_PLL1] =3D imx_clk_hw_pll14xx_ssc("video_pll1", "video_pl= l1_ref_sel", anatop_base + 0x28, &imx_1443x_pll, &pll1443x_ssc); + imx_clk_pll14xx_get_ssc_conf(anatop_np, IMX8MP_DRAM_PLL, &pll1443x_ssc); + hws[IMX8MP_DRAM_PLL] =3D imx_clk_hw_pll14xx_ssc("dram_pll", "dram_pll_ref= _sel", anatop_base + 0x50, &imx_1443x_dram_pll, &pll1443x_ssc); hws[IMX8MP_GPU_PLL] =3D imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", = anatop_base + 0x64, &imx_1416x_pll); hws[IMX8MP_VPU_PLL] =3D imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", = anatop_base + 0x74, &imx_1416x_pll); hws[IMX8MP_ARM_PLL] =3D imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", = anatop_base + 0x84, &imx_1416x_pll); --=20 2.43.0