From nobody Thu Nov 28 22:43:24 2024 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB4771F5EA; Sat, 28 Sep 2024 22:43:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727563384; cv=none; b=jbyRHtC4np3SnghGDBqQ+cE5SKugkqN41qZXcpYbYGQV+ineyiXwVEjJZm1q8kAsHz5SwDU5K4tOE2SgFZbqSfn5WME/gJR3TGk+CqdyYBhOhqixL7LL5PRWAphVy6z13Nln+EGNbHF8ejXeogyo4worj8PDGkO65IbBhMuLGqY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727563384; c=relaxed/simple; bh=PWp4kT7s/Fwc0Ox0LJ6sW4hsvPXd/Aa5dXhIqR1ulxs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=cbSBCWGWDe0OepP1pBpZPLUX+GoUvzMT0WBj9FLSJ/Pu+o3Ecy7jZdIU/bQ7sf7+vvu7Ibxkm8gQoOVH1FWLfgkXIof4SrYITOJibKnlUgfXjETPnWiNCNCqaUZ5W10D4si5bvhilpx1539XdwVge8RFVzXQtreFKuFbjQXoaWY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=Nk6h6Cf7; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="Nk6h6Cf7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1727563047; bh=PWp4kT7s/Fwc0Ox0LJ6sW4hsvPXd/Aa5dXhIqR1ulxs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Nk6h6Cf7BsTQTVY48F64WDRzOFCouCvbHM2iKdAejo4Y1wRqsmuOok08cekvWbgyd MSa7wVSKP3dNeSELbov6L/O6yNNm+qsFC2jaTc3UNN1OOQBYm6jtXRoFal+2lu/U/C 5TZ0QRfw3QnJIIRGUGp0eCB0rM7Q4wGwciyU6NVJVR+xGgRgEsyX+yD7fBp7VfkJXk Wu3KI+ZImuRbAO8WQuccfYTM0xT4c1xMQrQcE+lLo9pwby/2/IlWsB1YLMbkxnpbP9 NcjrvDHRJphhHzaXCQiVXdIZcLa5qwQoijJ4YYGj3G8WNphH9CU+gyik/VChontf3t EtHTkXLpEELMA== Received: from localhost (100.121.120.78.rev.sfr.net [78.120.121.100]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id 4290817E0E64; Sun, 29 Sep 2024 00:37:27 +0200 (CEST) From: Cristian Ciocaltea Date: Sun, 29 Sep 2024 01:36:48 +0300 Subject: [PATCH v8 2/3] dt-bindings: display: rockchip: Add schema for RK3588 HDMI TX Controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240929-b4-rk3588-bridge-upstream-v8-2-83538c2cc325@collabora.com> References: <20240929-b4-rk3588-bridge-upstream-v8-0-83538c2cc325@collabora.com> In-Reply-To: <20240929-b4-rk3588-bridge-upstream-v8-0-83538c2cc325@collabora.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mark Yao , Sascha Hauer , Simona Vetter , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com, Alexandre ARNOUD , Luis de Arquer , Krzysztof Kozlowski X-Mailer: b4 0.14.1 Rockchip RK3588 SoC integrates the Synopsys DesignWare HDMI 2.1 Quad-Pixel (QP) TX controller IP. Since this is a new IP block, quite different from those used in the previous generations of Rockchip SoCs, add a dedicated binding file. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Cristian Ciocaltea --- .../rockchip/rockchip,rk3588-dw-hdmi-qp.yaml | 188 +++++++++++++++++= ++++ 1 file changed, 188 insertions(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,rk= 3588-dw-hdmi-qp.yaml b/Documentation/devicetree/bindings/display/rockchip/r= ockchip,rk3588-dw-hdmi-qp.yaml new file mode 100644 index 000000000000..d8e761865f27 --- /dev/null +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3588-dw= -hdmi-qp.yaml @@ -0,0 +1,188 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/rockchip/rockchip,rk3588-dw-hdm= i-qp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip DW HDMI QP TX Encoder + +maintainers: + - Cristian Ciocaltea + +description: | + Rockchip RK3588 SoC integrates the Synopsys DesignWare HDMI QP TX contro= ller + IP and a HDMI/eDP TX Combo PHY based on a Samsung IP block, providing the + following features, among others: + + * Fixed Rate Link (FRL) + * Display Stream Compression (DSC) + * 4K@120Hz and 8K@60Hz video modes + * Variable Refresh Rate (VRR) including Quick Media Switching (QMS) + * Fast Vactive (FVA) + * SCDC I2C DDC access + * Multi-stream audio + * Enhanced Audio Return Channel (EARC) + +allOf: + - $ref: /schemas/sound/dai-common.yaml# + +properties: + compatible: + enum: + - rockchip,rk3588-dw-hdmi-qp + + reg: + maxItems: 1 + + clocks: + items: + - description: Peripheral/APB bus clock + - description: EARC RX biphase clock + - description: Reference clock + - description: Audio interface clock + - description: TMDS/FRL link clock + - description: Video datapath clock + + clock-names: + items: + - const: pclk + - const: earc + - const: ref + - const: aud + - const: hdp + - const: hclk_vo1 + + interrupts: + items: + - description: AVP Unit interrupt + - description: CEC interrupt + - description: eARC RX interrupt + - description: Main Unit interrupt + - description: HPD interrupt + + interrupt-names: + items: + - const: avp + - const: cec + - const: earc + - const: main + - const: hpd + + phys: + maxItems: 1 + description: The HDMI/eDP PHY + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Video port for RGB/YUV input. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Video port for HDMI/eDP output. + + required: + - port@0 + - port@1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 2 + + reset-names: + items: + - const: ref + - const: hdp + + "#sound-dai-cells": + const: 0 + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Some HDMI QP related data is accessed through SYS GRF regs. + + rockchip,vo-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Additional HDMI QP related data is accessed through VO GRF regs. + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - interrupt-names + - phys + - ports + - resets + - reset-names + - rockchip,grf + - rockchip,vo-grf + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + hdmi@fde80000 { + compatible =3D "rockchip,rk3588-dw-hdmi-qp"; + reg =3D <0x0 0xfde80000 0x0 0x20000>; + clocks =3D <&cru PCLK_HDMITX0>, + <&cru CLK_HDMITX0_EARC>, + <&cru CLK_HDMITX0_REF>, + <&cru MCLK_I2S5_8CH_TX>, + <&cru CLK_HDMIHDP0>, + <&cru HCLK_VO1>; + clock-names =3D "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; + interrupts =3D , + , + , + , + ; + interrupt-names =3D "avp", "cec", "earc", "main", "hpd"; + phys =3D <&hdptxphy_hdmi0>; + power-domains =3D <&power RK3588_PD_VO1>; + resets =3D <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>; + reset-names =3D "ref", "hdp"; + rockchip,grf =3D <&sys_grf>; + rockchip,vo-grf =3D <&vo1_grf>; + #sound-dai-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + hdmi0_in_vp0: endpoint { + remote-endpoint =3D <&vp0_out_hdmi0>; + }; + }; + + port@1 { + reg =3D <1>; + + hdmi0_out_con0: endpoint { + remote-endpoint =3D <&hdmi_con0_in>; + }; + }; + }; + }; + }; --=20 2.46.1