From nobody Thu Nov 28 20:04:50 2024 Received: from mail-ej1-f48.google.com (mail-ej1-f48.google.com [209.85.218.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9648B19EEC0 for ; Sat, 28 Sep 2024 08:38:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727512699; cv=none; b=I98atFHY3OsmEv25rB3G6ohettPh1EIMItvNjQ4pK7t+Poun5z6fV44kxmMxeiMZdhaSqgwLgwA1tz90jFZm1nX/8VG1JChiJrCTTKDZ/7neu5Olk4BNQ3//U5Mx7M2QTxBoOo5OaltWth9rrZztc/gwibc2UCTbm3QrpvaOs2w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727512699; c=relaxed/simple; bh=Lja37Vxknt4vNnaSkdJb0D6DbUgmwOpWSwtN5vUK9Yo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oaw70+T0esVJunHnrqXKSM/wTJ2D0FvU9TbxbDCSsGC6GsU/9PtcTX51XWd9lsz+5TDh9rWQnt4Q+z9WusQzClhAZVtYrw1Uzn7cIGDFn8Zmkba5zV1BG4K+l3si5EJG3nzz55qbp+X0+yi4rehoeQC6mCjc5A5DSH0vhL0NufE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=KcutP+KY; arc=none smtp.client-ip=209.85.218.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="KcutP+KY" Received: by mail-ej1-f48.google.com with SMTP id a640c23a62f3a-a8a6d1766a7so370850466b.3 for ; Sat, 28 Sep 2024 01:38:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1727512696; x=1728117496; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hgBA2YgBzcVdnVEoc6s2KOvaf1NpbuG7MmZKT5HNBsQ=; b=KcutP+KYLBaaKxVBaMldgqD2POa0Pfx85E4rx5uo/bx0+6T1pw+rViVss5DJr8lKgY u1NHsUSEDDWH2D9n+ambUVGmBG8NhzS+In3x6tpqUxmTbCjnILly3+cx5XqTvvYbu+qP 3WX4i/+zKzdKYuAt1wyESSeCc8yKo9CtebYOI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727512696; x=1728117496; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hgBA2YgBzcVdnVEoc6s2KOvaf1NpbuG7MmZKT5HNBsQ=; b=pptcUUI5dYp9R5Cs4EejYvFe1qNr7W2ID7AKbGkXobMm8PRzTDqgPEuHpDfLqMH7M7 X/vgHzOO/Q5Pb+un+TLfVcu/633xymyyiaotMObTn/fEJJfDfEX/vX2blgOo/GynFnYi CEvMJ8z+ukrU9Z7c6ofYVVFxuMQRtlYGDXCE4ZfCR7owFnCPk8yuOT3yI0oV4azF4VsK v2oLtYJ+f0+IZP1E3W9bF+o20q7AAO8fxt1/3LkszZMn/zj9fGrz7e07eKFMvuaZkeM1 sNRSLgkMPoZbgxhd2/FRX9qq81NctRgmcCszobhrVTPCZ/qiyiIvqE69FsfbWcL77a1H mryg== X-Gm-Message-State: AOJu0YxPfZT9FPQF6r9eKb1pUjkxR9S+kSYJ1ia6Zv4QHLfrxx3VNFXw QlqmHey+veza8HAst8oOnH2wEAji5YB4wMIEAE0yShcV8lVLTTxTkBKIvPKWfSDaGJmd5N3NCVZ /Qbw= X-Google-Smtp-Source: AGHT+IHW+mNjedKWSVNhjRyLls2JlxbznPHja/LY2bWHOSPBdNL3yKePDnTYBIPjvZtBQUPB/9/APQ== X-Received: by 2002:a17:907:1c19:b0:a80:bf95:7743 with SMTP id a640c23a62f3a-a93c48f8a9emr546855266b.13.1727512695646; Sat, 28 Sep 2024 01:38:15 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-79-54-102-102.retail.telecomitalia.it. [79.54.102.102]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a93c2947a48sm223679466b.118.2024.09.28.01.38.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 28 Sep 2024 01:38:15 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , Stephen Boyd , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH 1/6] dt-bindings: clock: imx8m-anatop: support spread spectrum clocking Date: Sat, 28 Sep 2024 10:37:49 +0200 Message-ID: <20240928083804.1073942-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240928083804.1073942-1-dario.binacchi@amarulasolutions.com> References: <20240928083804.1073942-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The patch adds the DT bindings for enabling and tuning spread spectrum clocking generation. Signed-off-by: Dario Binacchi --- .../bindings/clock/fsl,imx8m-anatop.yaml | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml = b/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml index bbd22e95b319..c91eb4229ed3 100644 --- a/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml +++ b/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml @@ -32,6 +32,47 @@ properties: =20 '#clock-cells': const: 1 +if: + properties: + compatible: + contains: + enum: + - fsl,imx8mm-anatop + +then: + properties: + fsl,ssc-clocks: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + The phandles to the PLLs with spread spectrum clock generation + hardware capability. + maxItems: 4 + + fsl,ssc-modfreq-hz: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + The values of modulation frequency (Hz unit) of spread spectrum + clocking for each PLL. + maxItems: 4 + + fsl,ssc-modrate-percent: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + The percentage values of modulation rate of spread spectrum + clocking for each PLL. + maxItems: 4 + + fsl,ssc-modmethod: + $ref: /schemas/types.yaml#/definitions/string-array + description: + The modulation techniques of spread spectrum clocking for + each PLL. + oneOf: + - enum: + - down-spread + - up-spread + - center-spread + maxItems: 4 =20 required: - compatible --=20 2.43.0 From nobody Thu Nov 28 20:04:50 2024 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6432819E99F for ; Sat, 28 Sep 2024 08:38:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727512701; cv=none; b=adW5SC3IGLuUAsi82ntlE2V/gwW9HQvwSXjMA7S6dmUaCSA07Kj6jLhaTMlvpumt34ablbB8c/g3R3tnjUppYuZfLuJPLuuoaI4LnhuXk/EmR7lMLFlwnrFQhnidRuIbWWF9BSVYvZe/gDKvjSMLXwTcutpAx0zIPRmHbI92wF8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727512701; c=relaxed/simple; bh=ZUYA+pWZpY2DRc3cAVwVXQSDu+K0xkkk/o8s2GO9A2s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QDVrDxLwdyAfyUHZrrnpvMCsMYjgvb0sIJlhu22pkH1w/snBiFwQq2ubzetm9yhqWoKI3+2hAFsjFtNbEaANNrHfMwlObGAsvsC872tT8veaffbGwzcZLR80A+PIXW0CBnKtfENyOL1y+Mqd+UGDQrr/XRN/Dkk+YH/e5/amfqM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=jg3P3Npd; arc=none smtp.client-ip=209.85.221.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="jg3P3Npd" Received: by mail-wr1-f41.google.com with SMTP id ffacd0b85a97d-37cd26c6dd1so2040303f8f.3 for ; Sat, 28 Sep 2024 01:38:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1727512697; x=1728117497; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=k379zOY8JpOCRdB0yzVh9VgxfCdVDSaVvSc2yhV6i0U=; b=jg3P3NpdlmHYPvvObjwxajKsDUFTKm8Iqp292ScxLf+SPN538pXpTbu5o4NwNdHrbg NsYhxGbLocDg4WqtX037aiBjwte7DfrtrexoLNEL2+0es7UQbweCUSeDDcN5RHdm7lCa mCyo2ULwueN5WFC+w35Ciqcw7eX+Y8iUVqQjw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727512697; x=1728117497; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=k379zOY8JpOCRdB0yzVh9VgxfCdVDSaVvSc2yhV6i0U=; b=dbVdSEXePbOz7AYJISWvkST6MCV7wINmebUSGkPxEhI1+wLXNZWFIcDWKi33psK7Or H7SJMPMCRjGRmIvvWsdHx6QuhabWP6iPaEOGMpSSdyGhBs6MBBhBG6rYRITVsSI7qxu7 WmfjqS73nA0Gqq5NqENiSLG4/9vSH9WQA+qB4qmCoTpBsDtxL5/ASrug3mDT5Lf4o8WW 1lAEvHCAtbCRNMX80hCvYIPDC80+Mmz+RgauZnKdzE/aWvjyWZMO2+hxcQQRvLKnlaVK BvC55P0t8XLJchDMBT3bHrGj+q7Vi3m6cokISYj1XvdW9kb3KzDmx0viPWeJmZ56Z2nN r3Hg== X-Gm-Message-State: AOJu0YxO2QMG+Cg5s74wW/vqvNf08HfNw/2Ed+dCi3QqoFwyImveXEMK k+o6gqNeXhSBiQjrnpe4+GFkQ8LT/I8vs9IbPEp2q8BDwQIRQ9mKi6tusxaWBIvRj4+X/WuDHJK ykXQ= X-Google-Smtp-Source: AGHT+IHCyQ8skwu32yu2SwDHwvsHGmAVmHkmWH0xMp/ynee+PdhG3tyDaW/28q4Wvdxhu/O3lEXDmQ== X-Received: by 2002:adf:fa88:0:b0:37c:cce6:997d with SMTP id ffacd0b85a97d-37cd5a8c952mr5708720f8f.20.1727512697418; Sat, 28 Sep 2024 01:38:17 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-79-54-102-102.retail.telecomitalia.it. [79.54.102.102]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a93c2947a48sm223679466b.118.2024.09.28.01.38.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 28 Sep 2024 01:38:17 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH 2/6] clk: imx: pll14xx: support spread spectrum clock generation Date: Sat, 28 Sep 2024 10:37:50 +0200 Message-ID: <20240928083804.1073942-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240928083804.1073942-1-dario.binacchi@amarulasolutions.com> References: <20240928083804.1073942-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch adds support for spread spectrum clock (SSC) generation for the pll14xxx. The addition of the "imx_clk_hw_pll14xx_ssc" macro has minimized the number of changes required to avoid compilation errors following the addition of the SSC setup parameter to the "imx_dev_clk_hw_pll14xx" macro used in the files clk-imx8m{m,n,p}.c. The change to the clk-imx8mp-audiomix.c file prevents the patch from causing a compilation error. Signed-off-by: Dario Binacchi --- drivers/clk/imx/clk-imx8mp-audiomix.c | 2 +- drivers/clk/imx/clk-pll14xx.c | 102 +++++++++++++++++++++++++- drivers/clk/imx/clk.h | 24 +++++- 3 files changed, 124 insertions(+), 4 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mp-audiomix.c b/drivers/clk/imx/clk-im= x8mp-audiomix.c index b2cb157703c5..bfcf2975c217 100644 --- a/drivers/clk/imx/clk-imx8mp-audiomix.c +++ b/drivers/clk/imx/clk-imx8mp-audiomix.c @@ -365,7 +365,7 @@ static int clk_imx8mp_audiomix_probe(struct platform_de= vice *pdev) clk_hw_data->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL] =3D hw; =20 hw =3D imx_dev_clk_hw_pll14xx(dev, "sai_pll", "sai_pll_ref_sel", - base + 0x400, &imx_1443x_pll); + base + 0x400, &imx_1443x_pll, NULL); if (IS_ERR(hw)) { ret =3D PTR_ERR(hw); goto err_clk_register; diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index d63564dbb12c..76014e243a57 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -20,6 +20,8 @@ #define GNRL_CTL 0x0 #define DIV_CTL0 0x4 #define DIV_CTL1 0x8 +#define SSCG_CTRL 0xc + #define LOCK_STATUS BIT(31) #define LOCK_SEL_MASK BIT(29) #define CLKE_MASK BIT(11) @@ -31,6 +33,10 @@ #define KDIV_MASK GENMASK(15, 0) #define KDIV_MIN SHRT_MIN #define KDIV_MAX SHRT_MAX +#define SSCG_ENABLE BIT(31) +#define MFREQ_CTL_MASK GENMASK(19, 12) +#define MRAT_CTL_MASK GENMASK(9, 4) +#define SEL_PF_MASK GENMASK(1, 0) =20 #define LOCK_TIMEOUT_US 10000 =20 @@ -40,6 +46,7 @@ struct clk_pll14xx { enum imx_pll14xx_type type; const struct imx_pll14xx_rate_table *rate_table; int rate_count; + struct imx_pll14xx_ssc ssc; }; =20 #define to_clk_pll14xx(_hw) container_of(_hw, struct clk_pll14xx, hw) @@ -347,6 +354,27 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, un= signed long drate, return 0; } =20 +static void clk_pll1443x_set_sscg(struct clk_hw *hw, unsigned long parent_= rate, + unsigned int pdiv, unsigned int mdiv) +{ + struct clk_pll14xx *pll =3D to_clk_pll14xx(hw); + struct imx_pll14xx_ssc *ssc =3D &pll->ssc; + u32 sscg_ctrl =3D readl_relaxed(pll->base + SSCG_CTRL); + + sscg_ctrl &=3D + ~(SSCG_ENABLE | MFREQ_CTL_MASK | MRAT_CTL_MASK | SEL_PF_MASK); + if (ssc->enable) { + u32 mfr =3D parent_rate / (ssc->mod_freq * pdiv * (1 << 5)); + u32 mrr =3D (ssc->mod_rate * mdiv * (1 << 6)) / (100 * mfr); + + sscg_ctrl |=3D SSCG_ENABLE | FIELD_PREP(MFREQ_CTL_MASK, mfr) | + FIELD_PREP(MRAT_CTL_MASK, mrr) | + FIELD_PREP(SEL_PF_MASK, ssc->mod_type); + } + + writel_relaxed(sscg_ctrl, pll->base + SSCG_CTRL); +} + static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) { @@ -368,6 +396,9 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, uns= igned long drate, writel_relaxed(FIELD_PREP(KDIV_MASK, rate.kdiv), pll->base + DIV_CTL1); =20 + if (pll->ssc.enable) + clk_pll1443x_set_sscg(hw, prate, rate.pdiv, rate.mdiv); + return 0; } =20 @@ -408,6 +439,9 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, uns= igned long drate, gnrl_ctl &=3D ~BYPASS_MASK; writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL); =20 + if (pll->ssc.enable) + clk_pll1443x_set_sscg(hw, prate, rate.pdiv, rate.mdiv); + return 0; } =20 @@ -487,7 +521,8 @@ static const struct clk_ops clk_pll1443x_ops =3D { =20 struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, const char *parent_name, void __iomem *base, - const struct imx_pll14xx_clk *pll_clk) + const struct imx_pll14xx_clk *pll_clk, + const struct imx_pll14xx_ssc *ssc) { struct clk_pll14xx *pll; struct clk_hw *hw; @@ -525,6 +560,8 @@ struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *de= v, const char *name, pll->type =3D pll_clk->type; pll->rate_table =3D pll_clk->rate_table; pll->rate_count =3D pll_clk->rate_count; + if (ssc) + memcpy(&pll->ssc, ssc, sizeof(pll->ssc)); =20 val =3D readl_relaxed(pll->base + GNRL_CTL); val &=3D ~BYPASS_MASK; @@ -542,3 +579,66 @@ struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *d= ev, const char *name, return hw; } EXPORT_SYMBOL_GPL(imx_dev_clk_hw_pll14xx); + +static enum imx_pll14xx_ssc_mod_type clk_pll14xx_ssc_mode(const char *name, + enum imx_pll14xx_ssc_mod_type def) +{ + int i; + struct { + const char *name; + enum imx_pll14xx_ssc_mod_type id; + } mod_methods[] =3D { + { .name =3D "down-spread", .id =3D IMX_PLL14XX_SSC_DOWN_SPREAD }, + { .name =3D "up-spread", .id =3D IMX_PLL14XX_SSC_UP_SPREAD }, + { .name =3D "center-spread", .id =3D IMX_PLL14XX_SSC_CENTER_SPREAD } + }; + + for (i =3D 0; i < ARRAY_SIZE(mod_methods); i++) { + if (!strcmp(name, mod_methods[i].name)) + return mod_methods[i].id; + } + + return def; +} + +void imx_clk_pll14xx_get_ssc_conf(struct device_node *np, int pll_id, + struct imx_pll14xx_ssc *ssc) +{ + int i, ret, offset, num_clks; + u32 clk_id, clk_cell_size; + const char *s; + + if (!ssc) + return; + + memset(ssc, 0, sizeof(*ssc)); + + num_clks =3D of_count_phandle_with_args(np, "fsl,ssc-clocks", + "#clock-cells"); + if (num_clks <=3D 0) + return; + + ret =3D of_property_read_u32(np, "#clock-cells", &clk_cell_size); + if (ret) + return; + + for (i =3D 0; i < num_clks; i++) { + offset =3D i * clk_cell_size + 1; + of_property_read_u32_index(np, "fsl,ssc-clocks", offset, + &clk_id); + if (clk_id !=3D pll_id) + continue; + + of_property_read_u32_index(np, "fsl,ssc-modfreq-hz", i, + &ssc->mod_freq); + of_property_read_u32_index(np, "fsl,ssc-modrate-percent", i, + &ssc->mod_rate); + if (!of_property_read_string(np, "fsl,ssc-modmethod", &s)) + ssc->mod_type =3D clk_pll14xx_ssc_mode( + s, IMX_PLL14XX_SSC_DOWN_SPREAD); + + ssc->enable =3D true; + break; + } +} +EXPORT_SYMBOL_GPL(imx_clk_pll14xx_get_ssc_conf); diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index aa5202f284f3..8cbc75480569 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -62,6 +62,19 @@ struct imx_pll14xx_rate_table { unsigned int kdiv; }; =20 +enum imx_pll14xx_ssc_mod_type { + IMX_PLL14XX_SSC_DOWN_SPREAD, + IMX_PLL14XX_SSC_UP_SPREAD, + IMX_PLL14XX_SSC_CENTER_SPREAD, +}; + +struct imx_pll14xx_ssc { + bool enable; + unsigned int mod_freq; + unsigned int mod_rate; + enum imx_pll14xx_ssc_mod_type mod_type; +}; + struct imx_pll14xx_clk { enum imx_pll14xx_type type; const struct imx_pll14xx_rate_table *rate_table; @@ -222,11 +235,18 @@ extern struct imx_fracn_gppll_clk imx_fracn_gppll_int= eger; __imx_clk_hw_divider(name, parent, reg, shift, width, flags) =20 #define imx_clk_hw_pll14xx(name, parent_name, base, pll_clk) \ - imx_dev_clk_hw_pll14xx(NULL, name, parent_name, base, pll_clk) + imx_dev_clk_hw_pll14xx(NULL, name, parent_name, base, pll_clk, NULL) + +#define imx_clk_hw_pll14xx_ssc(name, parent_name, base, pll_clk, ssc) \ + imx_dev_clk_hw_pll14xx(NULL, name, parent_name, base, pll_clk, ssc) =20 struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, const char *parent_name, void __iomem *base, - const struct imx_pll14xx_clk *pll_clk); + const struct imx_pll14xx_clk *pll_clk, + const struct imx_pll14xx_ssc *ssc); + +void imx_clk_pll14xx_get_ssc_conf(struct device_node *np, int pll_id, + struct imx_pll14xx_ssc *ssc); =20 struct clk_hw *imx_clk_hw_pllv1(enum imx_pllv1_type type, const char *name, const char *parent, void __iomem *base); --=20 2.43.0 From nobody Thu Nov 28 20:04:50 2024 Received: from mail-ed1-f51.google.com (mail-ed1-f51.google.com [209.85.208.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9EA1F19F40D for ; Sat, 28 Sep 2024 08:38:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727512702; cv=none; b=kEKYFeB5O0+ScNDdm9MXlsNtpebQHEOCuMUbq7MIQqXngzDxtXjc+U9C4CgJycBdLL7TvcaASudfulcikcEggDnLcSQqK0WlHjIg4WkrDLjJXu0sbSwQrzkTV3us2Z7lr9OlR0J6e96rgSFyFr8OtUFfdjLPvZTbWbyryBDcBWU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727512702; c=relaxed/simple; bh=+LIG3cg9UTPBwV/5p8kY6zB2pD8tcc+5yEpopWLpDMY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EmrwVEGSh7Nba8FwHB4fxesbNW0X1aA3bTaYjYGiJWscdn1oLVBKizWBucrvEr0CvLuN8q+hvvBAq9RZejWV2IDaa+gNlenvLR6URD2N6hQ5iIfYJk0XD2L/Ek6QbFsClrMwnf+JYm6xbH06y7/QCXzUA0ExchO1LYMh/wrLHk0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=A2Aun4Z0; arc=none smtp.client-ip=209.85.208.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="A2Aun4Z0" Received: by mail-ed1-f51.google.com with SMTP id 4fb4d7f45d1cf-5c5b954c359so3018705a12.1 for ; Sat, 28 Sep 2024 01:38:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1727512699; x=1728117499; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3VEkdzuU9Qc4GQ7KPC08t+6l9YpInoSw+Q79uFbywaU=; b=A2Aun4Z02w9N4+BRwswYbeySAFywHBwl23gXhEXAAxet1isDpET223/0wRy8SlxrCG 0WtZY9lhvM+qLD0pk6dK2mbAV29b3JJiWuIYtkW0jtOSyIfhDw72SBXbImUE0k6YPqRT 7FJAnzd/78DUfpt6iUlBT90DRFXvs1uztb8vc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727512699; x=1728117499; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3VEkdzuU9Qc4GQ7KPC08t+6l9YpInoSw+Q79uFbywaU=; b=DC7yfsw3bn48i5Vx+DRhz6qNWItost9P6Qxh7iOkODOg2innHc0Pgf0Cu1wbB67V+D oRgOCXd0Gx/LD8/YGhhTw0CgGTilBEd0BdCcX60osXT5T9QdHqxzT/7ogUNJAtnPOD7W c/y8kfFYBSNdEWIaxQocc8jcBbKaQ1Bq9TCPIH9LRSD8yqqNE0BgLi3IdBTtQicW23G9 cF2w7L+eNWqO8tSxfDd9mqNmqzY6tP/d1futLRpCkH8areQOPibtLWkiSejVZAedi7Wy juGqhmFIdANoWJ4eNRQ95dOFrAq1f64KPpT/IcEFDDbW5B84NkBvlKz5lN7R/kytC7S0 XViA== X-Gm-Message-State: AOJu0YzjFXvJeH1roXEB7hlQik47NdPXS/T0Cso1q5Yqcs2dHtoKRWNQ sCnKa5B9ThpYUfZcmdM31zxRBCA5kwonp2r7tcfsy1u+St1yk4KyN+9sMAq1a9PMtvO2S4fRscl zlks= X-Google-Smtp-Source: AGHT+IFa7csnZDelf35kuoatw+A4XX53RvHi8+qFq8X4RDr+Ud2jdFWJt1egnboit9+Z95EazZREyw== X-Received: by 2002:a17:907:3f17:b0:a8d:c3b:b16 with SMTP id a640c23a62f3a-a93c49299c3mr607559266b.28.1727512698854; Sat, 28 Sep 2024 01:38:18 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-79-54-102-102.retail.telecomitalia.it. [79.54.102.102]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a93c2947a48sm223679466b.118.2024.09.28.01.38.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 28 Sep 2024 01:38:18 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH 3/6] clk: imx8mm: support spread spectrum clock generation Date: Sat, 28 Sep 2024 10:37:51 +0200 Message-ID: <20240928083804.1073942-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240928083804.1073942-1-dario.binacchi@amarulasolutions.com> References: <20240928083804.1073942-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The patch adds support for spread spectrum clock generation for the audio, video, and DRAM PLLs. Signed-off-by: Dario Binacchi --- drivers/clk/imx/clk-imx8mm.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 342049b847b9..0acf2979c929 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -301,6 +301,7 @@ static int imx8mm_clocks_probe(struct platform_device *= pdev) struct device *dev =3D &pdev->dev; struct device_node *np =3D dev->of_node; void __iomem *base; + struct imx_pll14xx_ssc pll1443x_ssc; int ret; =20 clk_hw_data =3D kzalloc(struct_size(clk_hw_data, hws, @@ -334,10 +335,14 @@ static int imx8mm_clocks_probe(struct platform_device= *pdev) hws[IMX8MM_ARM_PLL_REF_SEL] =3D imx_clk_hw_mux("arm_pll_ref_sel", base + = 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MM_SYS_PLL3_REF_SEL] =3D imx_clk_hw_mux("sys_pll3_ref_sel", base = + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); =20 - hws[IMX8MM_AUDIO_PLL1] =3D imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_r= ef_sel", base, &imx_1443x_pll); - hws[IMX8MM_AUDIO_PLL2] =3D imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_r= ef_sel", base + 0x14, &imx_1443x_pll); - hws[IMX8MM_VIDEO_PLL1] =3D imx_clk_hw_pll14xx("video_pll1", "video_pll1_r= ef_sel", base + 0x28, &imx_1443x_pll); - hws[IMX8MM_DRAM_PLL] =3D imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel= ", base + 0x50, &imx_1443x_dram_pll); + imx_clk_pll14xx_get_ssc_conf(np, IMX8MM_AUDIO_PLL1, &pll1443x_ssc); + hws[IMX8MM_AUDIO_PLL1] =3D imx_clk_hw_pll14xx_ssc("audio_pll1", "audio_pl= l1_ref_sel", base, &imx_1443x_pll, &pll1443x_ssc); + imx_clk_pll14xx_get_ssc_conf(np, IMX8MM_AUDIO_PLL2, &pll1443x_ssc); + hws[IMX8MM_AUDIO_PLL2] =3D imx_clk_hw_pll14xx_ssc("audio_pll2", "audio_pl= l2_ref_sel", base + 0x14, &imx_1443x_pll, &pll1443x_ssc); + imx_clk_pll14xx_get_ssc_conf(np, IMX8MM_VIDEO_PLL1, &pll1443x_ssc); + hws[IMX8MM_VIDEO_PLL1] =3D imx_clk_hw_pll14xx_ssc("video_pll1", "video_pl= l1_ref_sel", base + 0x28, &imx_1443x_pll, &pll1443x_ssc); + imx_clk_pll14xx_get_ssc_conf(np, IMX8MM_DRAM_PLL, &pll1443x_ssc); + hws[IMX8MM_DRAM_PLL] =3D imx_clk_hw_pll14xx_ssc("dram_pll", "dram_pll_ref= _sel", base + 0x50, &imx_1443x_dram_pll, &pll1443x_ssc); hws[IMX8MM_GPU_PLL] =3D imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", = base + 0x64, &imx_1416x_pll); hws[IMX8MM_VPU_PLL] =3D imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", = base + 0x74, &imx_1416x_pll); hws[IMX8MM_ARM_PLL] =3D imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", = base + 0x84, &imx_1416x_pll); --=20 2.43.0 From nobody Thu Nov 28 20:04:50 2024 Received: from mail-ej1-f49.google.com (mail-ej1-f49.google.com [209.85.218.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A9F719F43F for ; Sat, 28 Sep 2024 08:38:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727512703; cv=none; b=RqAu2PV6L9SpYeG6yawPt1ozDoRZXyAEMkOXOat52IgImnPK8gZwS7SCI8EWVtioXilLRe130dwHd3KrfWh061oFmDjByhvTxVeQsapKrjvl1Zm4s3stpujGjEhS0oW0lgeXxKVhyOpJHbrR3MY5uKEdlG2V4P95W2y4Ti8biao= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727512703; c=relaxed/simple; bh=WnBuei5JYuZ25wbUZLj6WluWlAFoI6AsCHTUlKHiiiE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FBcq0MuUSnrM7Jw7dTLJP/3LYtKiUwkP/Yy/VOSszu7GpMyu2UGUlNp2NRYlm3ksY3wItOKCycH8OlFXEVvusP+GKN4l+J1MCbrX2qkYCCsEmAFp0Z/DqhGbpR7maRYWMH/cW/3zZZ+KekEuFsMejQeV9VrCVQFlM0QD1N6F2ws= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=M0n7efuV; arc=none smtp.client-ip=209.85.218.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="M0n7efuV" Received: by mail-ej1-f49.google.com with SMTP id a640c23a62f3a-a8d24f98215so404296266b.1 for ; Sat, 28 Sep 2024 01:38:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1727512700; x=1728117500; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8yZI1Cll/jgswR1C/8/RE7gUqkNMAx5u3jKxacFOTcY=; b=M0n7efuVqvwCip0fimXsaUiwqMbH9OY9N7K1nhpprD+mLIu1by0mYx4xHS7DDgf0Y5 qWMSJqpFyJ8FrY4zYtILHZpEcfQNIhw+pWYqz09AVcDWUAcwmJYYULLe90/8Dfqnlohz 9CM0cJi0Q+MUi16FHIqCtzhLEy5z29m2g10ac= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727512700; x=1728117500; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8yZI1Cll/jgswR1C/8/RE7gUqkNMAx5u3jKxacFOTcY=; b=RXVmm5FxIrsPrTH4EwW5pN020gJaPBDtpOC/YIsAjIdBQlGb5HD08gNGAYm1e394NZ fw5kcZLaQogOLaGy1re6ndjR2gX0TOh5C7g+etGWKMNEsPJG/WzpMza5P4NgFt+pLPdn 1zjg9BuHjbXehvn+iFhCzed4ADJKRhAWRfxXWjuTcCYNHNwPQuFBGhGkbat3gWFbgFjp G7LmxSeWV4p9eMm8SQOSzipWbQky7NOYjbnRICS/8e4sSmYxhd5typeHMQ+GXPrQmrk2 RctaSY9ysGlY/RdVGK7//MxcTOZ8iOO2EQ3SHDlKARYDGE3GjXjV8mwJcLpb7WoUqhan Kpag== X-Gm-Message-State: AOJu0YwOws+TNbtB//0hXoo0XZPaC/vBNCxVazZqbFmOIcjlW3qR3ugp cidQj5uEhzzO1YuGcizHAEbutIlSzL0sYF3YfJPAaYQU/V5v8Hg59ki7VIHkFA1n9uynN1IFp/2 iMrc= X-Google-Smtp-Source: AGHT+IEpHCIIkW74i8daN8Da+0LfjBKkKzdVA5122EIzP6PQGBfEDmDMRqPpOckP0H6LzAyxWWQDkQ== X-Received: by 2002:a17:907:3203:b0:a86:851e:3a2b with SMTP id a640c23a62f3a-a93c49299e7mr544249166b.29.1727512700295; Sat, 28 Sep 2024 01:38:20 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-79-54-102-102.retail.telecomitalia.it. [79.54.102.102]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a93c2947a48sm223679466b.118.2024.09.28.01.38.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 28 Sep 2024 01:38:20 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH 4/6] clk: imx8mn: support spread spectrum clock generation Date: Sat, 28 Sep 2024 10:37:52 +0200 Message-ID: <20240928083804.1073942-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240928083804.1073942-1-dario.binacchi@amarulasolutions.com> References: <20240928083804.1073942-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The patch adds support for spread spectrum clock generation for the audio, video, and DRAM PLLs. Signed-off-by: Dario Binacchi --- drivers/clk/imx/clk-imx8mn.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index ab77e148e70c..b33590a9b7b7 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -321,6 +321,7 @@ static int imx8mn_clocks_probe(struct platform_device *= pdev) struct device *dev =3D &pdev->dev; struct device_node *np =3D dev->of_node; void __iomem *base; + struct imx_pll14xx_ssc pll1443x_ssc; int ret; =20 clk_hw_data =3D devm_kzalloc(dev, struct_size(clk_hw_data, hws, @@ -356,10 +357,14 @@ static int imx8mn_clocks_probe(struct platform_device= *pdev) hws[IMX8MN_ARM_PLL_REF_SEL] =3D imx_clk_hw_mux("arm_pll_ref_sel", base + = 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MN_SYS_PLL3_REF_SEL] =3D imx_clk_hw_mux("sys_pll3_ref_sel", base = + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); =20 - hws[IMX8MN_AUDIO_PLL1] =3D imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_r= ef_sel", base, &imx_1443x_pll); - hws[IMX8MN_AUDIO_PLL2] =3D imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_r= ef_sel", base + 0x14, &imx_1443x_pll); - hws[IMX8MN_VIDEO_PLL] =3D imx_clk_hw_pll14xx("video_pll", "video_pll_ref_= sel", base + 0x28, &imx_1443x_pll); - hws[IMX8MN_DRAM_PLL] =3D imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel= ", base + 0x50, &imx_1443x_dram_pll); + imx_clk_pll14xx_get_ssc_conf(np, IMX8MN_AUDIO_PLL1, &pll1443x_ssc); + hws[IMX8MN_AUDIO_PLL1] =3D imx_clk_hw_pll14xx_ssc("audio_pll1", "audio_pl= l1_ref_sel", base, &imx_1443x_pll, &pll1443x_ssc); + imx_clk_pll14xx_get_ssc_conf(np, IMX8MN_AUDIO_PLL2, &pll1443x_ssc); + hws[IMX8MN_AUDIO_PLL2] =3D imx_clk_hw_pll14xx_ssc("audio_pll2", "audio_pl= l2_ref_sel", base + 0x14, &imx_1443x_pll, &pll1443x_ssc); + imx_clk_pll14xx_get_ssc_conf(np, IMX8MN_VIDEO_PLL, &pll1443x_ssc); + hws[IMX8MN_VIDEO_PLL] =3D imx_clk_hw_pll14xx_ssc("video_pll", "video_pll_= ref_sel", base + 0x28, &imx_1443x_pll, &pll1443x_ssc); + imx_clk_pll14xx_get_ssc_conf(np, IMX8MN_DRAM_PLL, &pll1443x_ssc); + hws[IMX8MN_DRAM_PLL] =3D imx_clk_hw_pll14xx_ssc("dram_pll", "dram_pll_ref= _sel", base + 0x50, &imx_1443x_dram_pll, &pll1443x_ssc); hws[IMX8MN_GPU_PLL] =3D imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", = base + 0x64, &imx_1416x_pll); hws[IMX8MN_M7_ALT_PLL] =3D imx_clk_hw_pll14xx("m7_alt_pll", "m7_alt_pll_r= ef_sel", base + 0x74, &imx_1416x_pll); hws[IMX8MN_ARM_PLL] =3D imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", = base + 0x84, &imx_1416x_pll); --=20 2.43.0 From nobody Thu Nov 28 20:04:50 2024 Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B75919F485 for ; Sat, 28 Sep 2024 08:38:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727512705; cv=none; b=aTOMRACZsyLItn7qLZEV2PnABEzoTQEvcFXcGQvEdA2lKzz6nZjxkBYLPdCbAXrPYbatIryVWSvpdgVlaBxd4ovnhESHX12dshQJUocrvXKyO3eoq5nLyP00TMdxosQl2EKwg2KaRX+xT4rB5AZF43QtLz/LWnPk54weh5+A/gs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727512705; c=relaxed/simple; bh=LJPl+PM/ybnwsGuR1t5bZ68xGmDFx3Tf0fdhTqB9WHs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IuiQ7V92Cge60LLTlUbxwfz+9APHYkwTRY/jAyQd+PSQVcNMAxEIL6tQLSl/28EMkkVgmxU4gndYCzq+jP3CivrDQG+3XDYUnpR/cC0I1u+T+E4fBKbT/uzxwOn8j0feZeaGmSgMXGvjsgllv6zn/m9pdMKu50FygBasIoLUb3U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=XTU1bsLC; arc=none smtp.client-ip=209.85.218.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="XTU1bsLC" Received: by mail-ej1-f54.google.com with SMTP id a640c23a62f3a-a93b2070e0cso326362166b.3 for ; Sat, 28 Sep 2024 01:38:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1727512702; x=1728117502; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sANYTc56l1dzuSb6OkWAQtijEDV1flO+WLT+P2kRW58=; b=XTU1bsLC9mdss7jplmg2js1Uqe5uR3I8yCGyKUfz7q3Vwenl53d12XtSMdrR9LTjiP Dde6nolCYmfC+mAdKuXjxn5D7mBebgwWTGK6IjX5eJeMGlldJtyZetFiHXAIT/M/wmE9 AwpC7g6Uod7B90HvEhuiT4E6yUorMO8uX2GTk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727512702; x=1728117502; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sANYTc56l1dzuSb6OkWAQtijEDV1flO+WLT+P2kRW58=; b=vP8A1shWDQ2p6juwRnbKLuQ9xrwf817cwwwqMilmAt1LzOR/UTCWFrdAv3fx6a3umF 9cZeuy6w91rZMo+bkoK+GJD2bXSXMvrbLHJYMYhe0VjvPsdWGrHXty1MEZFRgrY467JJ /L9222IIHwwolCwEUveckAE1IGjTArrx1r2gfohUADnxyDxPnZxzpVhgxaZsxFPtRfRF aCkFY/RfnevkHb2YMfpHd9Y6iHxd3JHhyjcaJiHLf83XTG1xj84p34KId+a7wDzXwAOQ a4lMQBgAL6CQUkFkxts6Mi2qj+kT3zuq4fFp5J2/L5JBXnzAmM8KWbjTChboY5lLvTl0 qkSQ== X-Gm-Message-State: AOJu0YymMngPmBLSxkkYH0BQLdqycUJVNzU0g6oW+hmkp76FSLaUmaGn nI0aAYumCgA5+Dag1bXocXKIvDxYE3kUr/d+6cg2mQTylxJeMtJ+agahJFSptKQgeoLgER5jTe/ Th3s= X-Google-Smtp-Source: AGHT+IEQNTGrd7nRTduYyFXKYNHcURQgmU386XHHP3cI20GYQr7olx3OUCxS6nGdYAY+ZIc3kLmHPw== X-Received: by 2002:a17:906:fe04:b0:a8b:6ee7:ba29 with SMTP id a640c23a62f3a-a93c4ac9401mr576566566b.44.1727512701885; Sat, 28 Sep 2024 01:38:21 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-79-54-102-102.retail.telecomitalia.it. [79.54.102.102]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a93c2947a48sm223679466b.118.2024.09.28.01.38.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 28 Sep 2024 01:38:21 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH 5/6] clk: imx8mp: don't lose the anatop device node Date: Sat, 28 Sep 2024 10:37:53 +0200 Message-ID: <20240928083804.1073942-6-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240928083804.1073942-1-dario.binacchi@amarulasolutions.com> References: <20240928083804.1073942-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Setting the "clk" (clock-controller@30380000) device node caused the reference to the "anatop" (clock-controller@30360000) device node to be lost. This patch, similar to what was already done for the base address, now distinguishes between the "anatop" device node and the "clk" device node. This change is preparatory for future developments. Signed-off-by: Dario Binacchi --- drivers/clk/imx/clk-imx8mp.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 516dbd170c8a..b2778958a572 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -408,13 +408,13 @@ static struct clk_hw_onecell_data *clk_hw_data; static int imx8mp_clocks_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; - struct device_node *np; + struct device_node *np, *anatop_np; void __iomem *anatop_base, *ccm_base; int err; =20 - np =3D of_find_compatible_node(NULL, NULL, "fsl,imx8mp-anatop"); - anatop_base =3D devm_of_iomap(dev, np, 0, NULL); - of_node_put(np); + anatop_np =3D of_find_compatible_node(NULL, NULL, "fsl,imx8mp-anatop"); + anatop_base =3D devm_of_iomap(dev, anatop_np, 0, NULL); + of_node_put(anatop_np); if (WARN_ON(IS_ERR(anatop_base))) return PTR_ERR(anatop_base); =20 --=20 2.43.0 From nobody Thu Nov 28 20:04:50 2024 Received: from mail-ej1-f42.google.com (mail-ej1-f42.google.com [209.85.218.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3938A19FA8F for ; Sat, 28 Sep 2024 08:38:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727512708; cv=none; b=Y7qGyklYFrE1s177BXXqdSRQl/aeVpH9TpV3sXp2L+wrh6K289ivV8U7yIdrCiufrdkiQRlEiE525felh976IeW4pR0lwN9IRS2JJ7H5Y2wGhTQeHgZQiwttmCcFO/RgGXerSRamRipr2HsWcgI+T6SzQu8OHCNbl8IxJcwcDwY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727512708; c=relaxed/simple; bh=V3GcAzqNjwMg5/Hvh9jUbJqltmtUfAEm3aT6HuannLg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=s2AzrKG0QGfRSSexELzRzNdJZU3h1crErXgFPd4kkxav4060tLVOQG8ZqVustupqlyIr6+xj09oR3f2H7mmmXO5YtpQEatAFwu4Ym0+tVnIgEUhF0ZIthe5y/o2XPo3SDE97bF5pt7z+PbdRVu8EW8Av9JweFqt9+48glowFD8g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=qiSANEgL; arc=none smtp.client-ip=209.85.218.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="qiSANEgL" Received: by mail-ej1-f42.google.com with SMTP id a640c23a62f3a-a93a1cda54dso379293366b.2 for ; Sat, 28 Sep 2024 01:38:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1727512703; x=1728117503; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SqdVHCjP2z3b3GmppGHkZvxobZmXnCslqoKDvGYxVNw=; b=qiSANEgLeOLGWQyy5tnnP6VXs0nVQe/dPqlz9M3tZaeTLRNTj2PVG2InewFnFt3XbO 7NSgi6bIUGpdy1kyJLaXbpNIYrawe7VFbx2eHc8pkMi64I3clIT68CFMedBFQdA/fSuE WowWWPiwlkjhpLcIDROVbNN54lFHWDoSa/FfM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727512703; x=1728117503; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SqdVHCjP2z3b3GmppGHkZvxobZmXnCslqoKDvGYxVNw=; b=BSlNM/r0xI9My0mtuS3QmoppJ+ozS3haUnLUyUpnE62M7rBNYHlFxHZJgaliCZPVIj HNOk7wGZ30qvybW7BgK/1oxqis+58lPs1/dfLimWyXq7DwRmhVQxFEOSeatazOWHKyfb r2CHxrHQNdOTlyQydnk7o1pSZQiboSowCS+0ojT8ysWobdYZ1Na8ClRleGWjax33CE1A 0kedxKcNwl8ixV1+DUVsQ2l4X/paIcKdfcm0tMbeC9wRvkPcL8gdcQ/EHgl18HVyaPVm Q1F+RTACYKPbzW2xv4fLORWMyT9tgabo9bnxlZ5xA8pItBi0xPXiKH+PkUILyswb2zL/ HCDg== X-Gm-Message-State: AOJu0YxokieT2cQepriBTQkwh+nvCTEKJ5yq5IL9o6y5yUXgSk+QsOpp Vx1ZCZAz5SHtTXbAAxgqLleNGFAhDeC3JGSqk6PN3Vt7au8UGuaoS9OTWwdrg+fQDxBHdLXD39R vAj4= X-Google-Smtp-Source: AGHT+IFep0uHWu7o5r2mN7w6qghEp9xGMWpGJDUw5UfEylXMOmM7N6REhb0d7hr9vD0ZU94R0/JpCA== X-Received: by 2002:a17:907:74c:b0:a8a:3ece:d073 with SMTP id a640c23a62f3a-a93c48f1b54mr526812266b.10.1727512703361; Sat, 28 Sep 2024 01:38:23 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-79-54-102-102.retail.telecomitalia.it. [79.54.102.102]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a93c2947a48sm223679466b.118.2024.09.28.01.38.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 28 Sep 2024 01:38:23 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH 6/6] clk: imx8mp: support spread spectrum clock generation Date: Sat, 28 Sep 2024 10:37:54 +0200 Message-ID: <20240928083804.1073942-7-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240928083804.1073942-1-dario.binacchi@amarulasolutions.com> References: <20240928083804.1073942-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The patch adds support for spread spectrum clock generation for the audio, video, and DRAM PLLs. Signed-off-by: Dario Binacchi --- drivers/clk/imx/clk-imx8mp.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index b2778958a572..460e8271def5 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -410,6 +410,7 @@ static int imx8mp_clocks_probe(struct platform_device *= pdev) struct device *dev =3D &pdev->dev; struct device_node *np, *anatop_np; void __iomem *anatop_base, *ccm_base; + struct imx_pll14xx_ssc pll1443x_ssc; int err; =20 anatop_np =3D of_find_compatible_node(NULL, NULL, "fsl,imx8mp-anatop"); @@ -449,10 +450,14 @@ static int imx8mp_clocks_probe(struct platform_device= *pdev) hws[IMX8MP_SYS_PLL2_REF_SEL] =3D imx_clk_hw_mux("sys_pll2_ref_sel", anato= p_base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MP_SYS_PLL3_REF_SEL] =3D imx_clk_hw_mux("sys_pll3_ref_sel", anato= p_base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); =20 - hws[IMX8MP_AUDIO_PLL1] =3D imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_r= ef_sel", anatop_base, &imx_1443x_pll); - hws[IMX8MP_AUDIO_PLL2] =3D imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_r= ef_sel", anatop_base + 0x14, &imx_1443x_pll); - hws[IMX8MP_VIDEO_PLL1] =3D imx_clk_hw_pll14xx("video_pll1", "video_pll1_r= ef_sel", anatop_base + 0x28, &imx_1443x_pll); - hws[IMX8MP_DRAM_PLL] =3D imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel= ", anatop_base + 0x50, &imx_1443x_dram_pll); + imx_clk_pll14xx_get_ssc_conf(anatop_np, IMX8MP_AUDIO_PLL1, &pll1443x_ssc); + hws[IMX8MP_AUDIO_PLL1] =3D imx_clk_hw_pll14xx_ssc("audio_pll1", "audio_pl= l1_ref_sel", anatop_base, &imx_1443x_pll, &pll1443x_ssc); + imx_clk_pll14xx_get_ssc_conf(anatop_np, IMX8MP_AUDIO_PLL2, &pll1443x_ssc); + hws[IMX8MP_AUDIO_PLL2] =3D imx_clk_hw_pll14xx_ssc("audio_pll2", "audio_pl= l2_ref_sel", anatop_base + 0x14, &imx_1443x_pll, &pll1443x_ssc); + imx_clk_pll14xx_get_ssc_conf(anatop_np, IMX8MP_VIDEO_PLL1, &pll1443x_ssc); + hws[IMX8MP_VIDEO_PLL1] =3D imx_clk_hw_pll14xx_ssc("video_pll1", "video_pl= l1_ref_sel", anatop_base + 0x28, &imx_1443x_pll, &pll1443x_ssc); + imx_clk_pll14xx_get_ssc_conf(anatop_np, IMX8MP_DRAM_PLL, &pll1443x_ssc); + hws[IMX8MP_DRAM_PLL] =3D imx_clk_hw_pll14xx_ssc("dram_pll", "dram_pll_ref= _sel", anatop_base + 0x50, &imx_1443x_dram_pll, &pll1443x_ssc); hws[IMX8MP_GPU_PLL] =3D imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", = anatop_base + 0x64, &imx_1416x_pll); hws[IMX8MP_VPU_PLL] =3D imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", = anatop_base + 0x74, &imx_1416x_pll); hws[IMX8MP_ARM_PLL] =3D imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", = anatop_base + 0x84, &imx_1416x_pll); --=20 2.43.0