From nobody Thu Nov 28 20:41:13 2024 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B5ABF18C93F; Fri, 27 Sep 2024 12:57:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727441874; cv=none; b=qnyHNMJ1Zvzava/17QFuoYd6MODdqk58yqpLbBzbfNmH/HVijd2UAhNAWneA3jG8d3FlVALAms1q25misPfWFfFn1o3cfLHTrmxhv6QAEa5DeZywKpZ2OIJPnKNEQqKccr7DRf0cR5vPIh8uS9MCENJjG/5X30E0bd1is5fzvkM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727441874; c=relaxed/simple; bh=gx2AN6g8CBHOQhQWVvBpRtBLyzQubEgkJDNlqL08IzM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=TQem98eVnz8SFizuxxuqqEZWv+TDP/nh8NR2uTtqJMv4Kcmn15lIq0k9EaxotJeEQi+9cThIzULHDfF0tVxFykF9W6wJXVtzI0hkJhXgRooVMik2h0HqwBbgPULOy/0fHhpURWOpDB7+tOPf9CSlCO4F9HN18paZM8lXJskevcc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=HmMy0WRs; arc=none smtp.client-ip=209.85.128.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="HmMy0WRs" Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-42cb58d810eso19936435e9.0; Fri, 27 Sep 2024 05:57:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1727441871; x=1728046671; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GkinVYGPyGwJ32i1kYAOsHhIvbGugGjjdqxMHgIEwAU=; b=HmMy0WRskuyEpVCJ609g/mIwMX88CCeB9BtolcEEV/7FrUZzEWIsVJ0wys3HimsEoE GH/b3PYF2AFTZHXyKzoRZoXUVvOWC2T74WCP7vpvsff6LJzqE2ntw1OUJktb7P7U+6pW cvRZEf7qFq/hcNv74WaoaB/f2L7woM9Hg8n/v3Pd5Ecz8YXA04W6/McwOoFHFpJa2PVk fkbD53ACGwV10I4FLi3QJwxO/F5ZM/AxIEVvPSH1PR1lQzUFghS4yC/qIBCyT025WSnb 6xP6tf9Pf6tJVeKht5wuP7mG3B9jg8kPQUxdQt7LTn8HZzfI3dNu6S+3GKCnPPXkxueO kmng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727441871; x=1728046671; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GkinVYGPyGwJ32i1kYAOsHhIvbGugGjjdqxMHgIEwAU=; b=oHbFb1a4gWY1Agr31HyX06UckndRkdDuh9ojlv5MGlzGriVnxpTdKXJafZpSwA56QW Af0wg2rE4k/YOaYg7SDsO+NIGNy8CDRJ7itqOOZxsyxGxTlggjVF2gz7s2xJ9ttjVzAW TzffX5c/7rXDtR9xvmSnW8LVZ2cTdBeX7FglIOHIvg3J3W1wAWEXc/qb71DFb0FRdcyL Vqt4P0/u+cG6MkaVyT/65KmiheQc1dbMGagu0R4eBWFZt6SvF+ONqqZHf/NK3al+RgRV eGFmcn/whTrTQPFZ1dVeYNViAdw1CFZu3dG5d1kLOGR0kfIotsYshuj9ndx13QMvP98W FALQ== X-Forwarded-Encrypted: i=1; AJvYcCUF8F2VXj7MpJj3+t1qiuxh/OcCvG41LSVMuzx6i5pdpnmGoirbeILX0V1woJDe+fyswKvNJYXeyf6G@vger.kernel.org, AJvYcCVrkeAvr0eUZn6MASllnCgaQh9RnxU6yUFLDYPMEGtqdixb8yRif7ywxsddG0QE5LBchP1xL7hdAl3i@vger.kernel.org, AJvYcCWUOAzzHXD+3iycTQxzJL/kcVYid/dMW0YyiVFdPiZliPPFkFZe4hOXXQYBSoycsGRtUCJ1gm/P1pcJ91cB@vger.kernel.org X-Gm-Message-State: AOJu0YzAsu/aY7ZypoSZaacsZNSqz1uAn4eAV6LApLrTNkKyHAoL0cMc PZpZsueYt9TSpJLjqkdWF0llT/G8Ha7tUG6yJr/Q8Pltu/0FXYrn X-Google-Smtp-Source: AGHT+IHZM2N019AsM2bnF7unQ4hkd4Nozrw+aEvAA75aqfCNeBXvtBcEvRO+Mg4S4VFBtFH/LYy8Qg== X-Received: by 2002:a05:600c:1c1c:b0:42c:b54c:a6d7 with SMTP id 5b1f17b1804b1-42f52200c3dmr40652905e9.14.1727441870659; Fri, 27 Sep 2024 05:57:50 -0700 (PDT) Received: from debian.fritz.box ([2a00:79c0:666:ff00:303:6c5b:4b07:6715]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42e969ddad1sm73814575e9.9.2024.09.27.05.57.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Sep 2024 05:57:50 -0700 (PDT) From: Dimitri Fedrau To: Cc: Dimitri Fedrau , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v6 1/2] dt-bindings: pwm: add support for MC33XS2410 Date: Fri, 27 Sep 2024 14:57:44 +0200 Message-Id: <20240927125745.38367-2-dima.fedrau@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20240927125745.38367-1-dima.fedrau@gmail.com> References: <20240927125745.38367-1-dima.fedrau@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Adding documentation for NXPs MC33XS2410 high side switch. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dimitri Fedrau --- .../bindings/pwm/nxp,mc33xs2410.yaml | 118 ++++++++++++++++++ 1 file changed, 118 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/nxp,mc33xs2410.ya= ml diff --git a/Documentation/devicetree/bindings/pwm/nxp,mc33xs2410.yaml b/Do= cumentation/devicetree/bindings/pwm/nxp,mc33xs2410.yaml new file mode 100644 index 000000000000..1729fe5c3dfb --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/nxp,mc33xs2410.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/nxp,mc33xs2410.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: High-side switch MC33XS2410 + +maintainers: + - Dimitri Fedrau + +allOf: + - $ref: pwm.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + const: nxp,mc33xs2410 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 10000000 + + spi-cpha: true + + spi-cs-setup-delay-ns: + minimum: 100 + default: 100 + + spi-cs-hold-delay-ns: + minimum: 10 + default: 10 + + spi-cs-inactive-delay-ns: + minimum: 300 + default: 300 + + reset-gpios: + description: + GPIO connected to the active low reset pin. + maxItems: 1 + + "#pwm-cells": + const: 3 + + pwm-names: + items: + - const: di0 + - const: di1 + - const: di2 + - const: di3 + + pwms: + description: + Direct inputs(di0-3) are used to directly turn-on or turn-off the + outputs. + maxItems: 4 + + interrupts: + maxItems: 1 + + clocks: + description: + The external clock can be used if the internal clock doesn't meet + timing requirements over temperature and voltage operating range. + maxItems: 1 + + vdd-supply: + description: + Logic supply voltage + + vspi-supply: + description: + Supply voltage for SPI + + vpwr-supply: + description: + Power switch supply + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + #include + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + pwm@0 { + compatible =3D "nxp,mc33xs2410"; + reg =3D <0x0>; + spi-max-frequency =3D <4000000>; + spi-cpha; + spi-cs-setup-delay-ns =3D <100>; + spi-cs-hold-delay-ns =3D <10>; + spi-cs-inactive-delay-ns =3D <300>; + reset-gpios =3D <&gpio3 22 GPIO_ACTIVE_LOW>; + #pwm-cells =3D <3>; + pwm-names =3D "di0", "di1", "di2", "di3"; + pwms =3D <&pwm0 0 1000000>, + <&pwm1 0 1000000>, + <&pwm2 0 1000000>, + <&pwm3 0 1000000>; + interrupt-parent =3D <&gpio0>; + interrupts =3D <31 IRQ_TYPE_LEVEL_LOW>; + clocks =3D <&clk_ext_fixed>; + vdd-supply =3D <®_3v3>; + vspi-supply =3D <®_3v3>; + vpwr-supply =3D <®_24v0>; + }; + }; --=20 2.39.5 From nobody Thu Nov 28 20:41:13 2024 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C19D18DF68; Fri, 27 Sep 2024 12:57:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" The MC33XS2410 is a four channel high-side switch. Featuring advanced monitoring and control function, the device is operational from 3.0 V to 60 V. The device is controlled by SPI port for configuration. Signed-off-by: Dimitri Fedrau --- drivers/pwm/Kconfig | 12 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-mc33xs2410.c | 422 +++++++++++++++++++++++++++++++++++ 3 files changed, 435 insertions(+) create mode 100644 drivers/pwm/pwm-mc33xs2410.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 0915c1e7df16..f513513f9b2f 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -411,6 +411,18 @@ config PWM_LPSS_PLATFORM To compile this driver as a module, choose M here: the module will be called pwm-lpss-platform. =20 +config PWM_MC33XS2410 + tristate "MC33XS2410 PWM support" + depends on OF + depends on SPI + help + NXP MC33XS2410 high-side switch driver. The MC33XS2410 is a four + channel high-side switch. The device is operational from 3.0 V + to 60 V. The device is controlled by SPI port for configuration. + + To compile this driver as a module, choose M here: the module + will be called pwm-mc33xs2410. + config PWM_MESON tristate "Amlogic Meson PWM driver" depends on ARCH_MESON || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 9081e0c0e9e0..c75deeeace40 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_PWM_LPC32XX) +=3D pwm-lpc32xx.o obj-$(CONFIG_PWM_LPSS) +=3D pwm-lpss.o obj-$(CONFIG_PWM_LPSS_PCI) +=3D pwm-lpss-pci.o obj-$(CONFIG_PWM_LPSS_PLATFORM) +=3D pwm-lpss-platform.o +obj-$(CONFIG_PWM_MC33XS2410) +=3D pwm-mc33xs2410.o obj-$(CONFIG_PWM_MESON) +=3D pwm-meson.o obj-$(CONFIG_PWM_MEDIATEK) +=3D pwm-mediatek.o obj-$(CONFIG_PWM_MICROCHIP_CORE) +=3D pwm-microchip-core.o diff --git a/drivers/pwm/pwm-mc33xs2410.c b/drivers/pwm/pwm-mc33xs2410.c new file mode 100644 index 000000000000..f9a334a5e69b --- /dev/null +++ b/drivers/pwm/pwm-mc33xs2410.c @@ -0,0 +1,422 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Liebherr-Electronics and Drives GmbH + * + * Reference Manual : https://www.nxp.com/docs/en/data-sheet/MC33XS2410.pdf + * + * Limitations: + * - Supports frequencies between 0.5Hz and 2048Hz with following steps: + * - 0.5 Hz steps from 0.5 Hz to 32 Hz + * - 2 Hz steps from 2 Hz to 128 Hz + * - 8 Hz steps from 8 Hz to 512 Hz + * - 32 Hz steps from 32 Hz to 2048 Hz + * - Cannot generate a 0 % duty cycle. + * - Always produces low output if disabled. + * - Configuration isn't atomic. When changing polarity, duty cycle or per= iod + * the data is taken immediately, counters not being affected, resulting= in a + * behavior of the output pin that is neither the old nor the new state, + * rather something in between. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +#define MC33XS2410_GLB_CTRL 0x00 +#define MC33XS2410_GLB_CTRL_MODE GENMASK(7, 6) +#define MC33XS2410_GLB_CTRL_MODE_NORMAL FIELD_PREP(MC33XS2410_GLB_CTRL_MOD= E, 1) +#define MC33XS2410_PWM_CTRL1 0x05 +#define MC33XS2410_PWM_CTRL1_POL_INV(x) BIT(x) +#define MC33XS2410_PWM_CTRL3 0x07 +/* x in { 0 ... 3 } */ +#define MC33XS2410_PWM_CTRL3_EN(x) BIT(4 + (x)) +#define MC33XS2410_PWM_FREQ1 0x08 +/* x in { 1 ... 4 } */ +#define MC33XS2410_PWM_FREQ(x) (MC33XS2410_PWM_FREQ1 + (x - 1)) +#define MC33XS2410_PWM_FREQ_STEP_MASK GENMASK(7, 6) +#define MC33XS2410_PWM_FREQ_COUNT_MASK GENMASK(5, 0) +#define MC33XS2410_PWM_DC1 0x0c +/* x in { 1 ... 4 } */ +#define MC33XS2410_PWM_DC(x) (MC33XS2410_PWM_DC1 + (x - 1)) +#define MC33XS2410_WDT 0x14 + +#define MC33XS2410_WR BIT(7) +#define MC33XS2410_RD_CTRL BIT(7) +#define MC33XS2410_RD_DATA_MASK GENMASK(13, 0) + +#define MC33XS2410_MIN_PERIOD 488282 +#define MC33XS2410_MAX_PERIOD_STEP0 2000000000 +/* x in { 0 ... 3 } */ +#define MC33XS2410_MAX_PERIOD_STEP(x) (MC33XS2410_MAX_PERIOD_STEP0 >> (2 *= x)) + +#define MC33XS2410_MAX_TRANSFERS 5 +#define MC33XS2410_WORD_LEN 2 + +struct mc33xs2410_pwm { + struct spi_device *spi; +}; + +static inline struct mc33xs2410_pwm *mc33xs2410_from_chip(struct pwm_chip = *chip) +{ + return pwmchip_get_drvdata(chip); +} + +static int mc33xs2410_xfer_regs(struct spi_device *spi, bool read, u8 *reg, + u16 *val, bool *ctrl, int len) +{ + struct spi_transfer t[MC33XS2410_MAX_TRANSFERS] =3D { { 0 } }; + u8 tx[MC33XS2410_MAX_TRANSFERS * MC33XS2410_WORD_LEN]; + u8 rx[MC33XS2410_MAX_TRANSFERS * MC33XS2410_WORD_LEN]; + int i, ret, reg_i, val_i; + + if (!len) + return 0; + + if (read) + len++; + + if (len > MC33XS2410_MAX_TRANSFERS) + return -EINVAL; + + for (i =3D 0; i < len; i++) { + reg_i =3D i * MC33XS2410_WORD_LEN; + val_i =3D reg_i + 1; + if (read) { + if (i < len - 1) { + tx[reg_i] =3D reg[i]; + tx[val_i] =3D ctrl[i] ? MC33XS2410_RD_CTRL : 0; + t[i].tx_buf =3D &tx[reg_i]; + } + + if (i > 0) + t[i].rx_buf =3D &rx[reg_i - MC33XS2410_WORD_LEN]; + } else { + tx[reg_i] =3D reg[i] | MC33XS2410_WR; + tx[val_i] =3D val[i]; + t[i].tx_buf =3D &tx[reg_i]; + } + + t[i].len =3D MC33XS2410_WORD_LEN; + t[i].cs_change =3D 1; + } + + t[len - 1].cs_change =3D 0; + + ret =3D spi_sync_transfer(spi, &t[0], len); + if (ret < 0) + return ret; + + if (read) { + for (i =3D 0; i < len - 1; i++) { + reg_i =3D i * MC33XS2410_WORD_LEN; + val[i] =3D FIELD_GET(MC33XS2410_RD_DATA_MASK, + get_unaligned_be16(&rx[reg_i])); + } + } + + return 0; +} + +static +int mc33xs2410_write_regs(struct spi_device *spi, u8 *reg, u16 *val, int l= en) +{ + + return mc33xs2410_xfer_regs(spi, false, reg, val, NULL, len); +} + +static int mc33xs2410_read_regs(struct spi_device *spi, u8 *reg, bool *ctr= l, + u16 *val, u8 len) +{ + return mc33xs2410_xfer_regs(spi, true, reg, val, ctrl, len); +} + + +static int mc33xs2410_write_reg(struct spi_device *spi, u8 reg, u16 val) +{ + return mc33xs2410_write_regs(spi, ®, &val, 1); +} + +static +int mc33xs2410_read_reg(struct spi_device *spi, u8 reg, u16 *val, bool ctr= l) +{ + return mc33xs2410_read_regs(spi, ®, &ctrl, val, 1); +} + +static int mc33xs2410_read_reg_ctrl(struct spi_device *spi, u8 reg, u16 *v= al) +{ + return mc33xs2410_read_reg(spi, reg, val, true); +} + +static +int mc33xs2410_modify_reg(struct spi_device *spi, u8 reg, u16 mask, u16 va= l) +{ + u16 tmp; + int ret; + + ret =3D mc33xs2410_read_reg_ctrl(spi, reg, &tmp); + if (ret < 0) + return ret; + + tmp &=3D ~mask; + tmp |=3D val & mask; + + return mc33xs2410_write_reg(spi, reg, tmp); +} + +static u8 mc33xs2410_pwm_get_freq(u64 period) +{ + u8 step, count; + + /* + * Check which step is appropriate for the given period, starting with + * the highest frequency(lowest period). Higher frequencies are + * represented with better resolution by the device. Therefore favor + * frequency range with the better resolution to minimize error + * introduced by the frequency steps. + */ + + switch (period) { + case MC33XS2410_MIN_PERIOD ... MC33XS2410_MAX_PERIOD_STEP(3): + step =3D 3; + break; + case MC33XS2410_MAX_PERIOD_STEP(3) + 1 ... MC33XS2410_MAX_PERIOD_STEP(2): + step =3D 2; + break; + case MC33XS2410_MAX_PERIOD_STEP(2) + 1 ... MC33XS2410_MAX_PERIOD_STEP(1): + step =3D 1; + break; + case MC33XS2410_MAX_PERIOD_STEP(1) + 1 ... MC33XS2410_MAX_PERIOD_STEP(0): + step =3D 0; + break; + } + + /* + * Round up here because a higher count results in a higher frequency + * and so a smaller period. + */ + count =3D DIV_ROUND_UP((u32)MC33XS2410_MAX_PERIOD_STEP(step), (u32)period= ); + return FIELD_PREP(MC33XS2410_PWM_FREQ_STEP_MASK, step) | + FIELD_PREP(MC33XS2410_PWM_FREQ_COUNT_MASK, count - 1); +} + +static u64 mc33xs2410_pwm_get_period(u8 reg) +{ + u32 freq, code, doubled_steps; + + /* + * steps: + * - 0 =3D 0.5Hz + * - 1 =3D 2Hz + * - 2 =3D 8Hz + * - 3 =3D 32Hz + * frequency =3D (code + 1) x steps. + * + * To avoid losing precision in case steps value is zero, scale the + * steps value for now by two and keep it in mind when calculating the + * period that the frequency had been doubled. + */ + doubled_steps =3D 1 << (FIELD_GET(MC33XS2410_PWM_FREQ_STEP_MASK, reg) * 2= ); + code =3D FIELD_GET(MC33XS2410_PWM_FREQ_COUNT_MASK, reg); + freq =3D (code + 1) * doubled_steps; + + /* Convert frequency to period, considering the doubled frequency. */ + return DIV_ROUND_UP((u32)(2 * NSEC_PER_SEC), freq); +} + +static int mc33xs2410_pwm_get_relative_duty_cycle(u64 period, u64 duty_cyc= le) +{ + /* + * duty_cycle cannot overflow and period is not zero, since this is + * guaranteed by the caller. + */ + duty_cycle *=3D 256; + duty_cycle =3D div64_u64(duty_cycle, period); + + return duty_cycle - 1; +} + +static void mc33xs2410_pwm_set_relative_duty_cycle(struct pwm_state *state, + u16 duty_cycle) +{ + if (!state->enabled) + state->duty_cycle =3D 0; + else + state->duty_cycle =3D DIV_ROUND_UP_ULL((duty_cycle + 1) * state->period,= 256); +} + +static int mc33xs2410_pwm_apply(struct pwm_chip *chip, struct pwm_device *= pwm, + const struct pwm_state *state) +{ + struct mc33xs2410_pwm *mc33xs2410 =3D mc33xs2410_from_chip(chip); + struct spi_device *spi =3D mc33xs2410->spi; + u8 reg[4] =3D { + MC33XS2410_PWM_FREQ(pwm->hwpwm + 1), + MC33XS2410_PWM_DC(pwm->hwpwm + 1), + MC33XS2410_PWM_CTRL1, + MC33XS2410_PWM_CTRL3 + }; + bool ctrl[2] =3D { true, true }; + u64 period, duty_cycle; + int ret, rel_dc; + u16 val[4]; + u8 mask; + + period =3D min(state->period, MC33XS2410_MAX_PERIOD_STEP(0)); + if (period < MC33XS2410_MIN_PERIOD) + return -EINVAL; + + ret =3D mc33xs2410_read_regs(spi, ®[2], &ctrl[0], &val[2], 2); + if (ret < 0) + return ret; + + /* frequency */ + val[0] =3D mc33xs2410_pwm_get_freq(period); + /* Continue calculations with the possibly truncated period */ + period =3D mc33xs2410_pwm_get_period(val[0]); + + /* duty cycle */ + duty_cycle =3D min(period, state->duty_cycle); + rel_dc =3D mc33xs2410_pwm_get_relative_duty_cycle(period, duty_cycle); + val[1] =3D rel_dc < 0 ? 0 : rel_dc; + + /* polarity */ + mask =3D MC33XS2410_PWM_CTRL1_POL_INV(pwm->hwpwm); + val[2] =3D (state->polarity =3D=3D PWM_POLARITY_INVERSED) ? + (val[2] | mask) : (val[2] & ~mask); + + /* enable output */ + mask =3D MC33XS2410_PWM_CTRL3_EN(pwm->hwpwm); + val[3] =3D (state->enabled && rel_dc >=3D 0) ? (val[3] | mask) : + (val[3] & ~mask); + + return mc33xs2410_write_regs(spi, reg, val, 4); +} + +static int mc33xs2410_pwm_get_state(struct pwm_chip *chip, + struct pwm_device *pwm, + struct pwm_state *state) +{ + struct mc33xs2410_pwm *mc33xs2410 =3D mc33xs2410_from_chip(chip); + struct spi_device *spi =3D mc33xs2410->spi; + u8 reg[4] =3D { + MC33XS2410_PWM_FREQ(pwm->hwpwm + 1), + MC33XS2410_PWM_DC(pwm->hwpwm + 1), + MC33XS2410_PWM_CTRL1, + MC33XS2410_PWM_CTRL3, + }; + bool ctrl[4] =3D { true, true, true, true }; + u16 val[4]; + int ret; + + ret =3D mc33xs2410_read_regs(spi, reg, ctrl, val, 4); + if (ret < 0) + return ret; + + state->period =3D mc33xs2410_pwm_get_period(val[0]); + state->polarity =3D (val[2] & MC33XS2410_PWM_CTRL1_POL_INV(pwm->hwpwm)) ? + PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL; + state->enabled =3D !!(val[3] & MC33XS2410_PWM_CTRL3_EN(pwm->hwpwm)); + mc33xs2410_pwm_set_relative_duty_cycle(state, val[1]); + return 0; +} + +static const struct pwm_ops mc33xs2410_pwm_ops =3D { + .apply =3D mc33xs2410_pwm_apply, + .get_state =3D mc33xs2410_pwm_get_state, +}; + +static int mc33xs2410_reset(struct device *dev) +{ + struct gpio_desc *reset_gpio; + + reset_gpio =3D devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR_OR_NULL(reset_gpio)) + return PTR_ERR_OR_ZERO(reset_gpio); + + fsleep(1000); + gpiod_set_value_cansleep(reset_gpio, 0); + /* Wake-up time */ + fsleep(10000); + + return 0; +} + +static int mc33xs2410_probe(struct spi_device *spi) +{ + struct mc33xs2410_pwm *mc33xs2410; + struct device *dev =3D &spi->dev; + struct pwm_chip *chip; + int ret; + + chip =3D devm_pwmchip_alloc(dev, 4, sizeof(*mc33xs2410)); + if (IS_ERR(chip)) + return PTR_ERR(chip); + + mc33xs2410 =3D mc33xs2410_from_chip(chip); + mc33xs2410->spi =3D spi; + chip->ops =3D &mc33xs2410_pwm_ops; + + ret =3D mc33xs2410_reset(dev); + if (ret) + return ret; + + /* + * Disable watchdog and keep in mind that the watchdog won't trigger a + * reset of the machine when running into an timeout, instead the + * control over the outputs is handed over to the INx input logic + * signals of the device. Disabling it here just deactivates this + * feature until a proper solution is found. + */ + ret =3D mc33xs2410_write_reg(spi, MC33XS2410_WDT, 0x0); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to disable watchdog\n"); + + /* Transition to normal mode */ + ret =3D mc33xs2410_modify_reg(spi, MC33XS2410_GLB_CTRL, + MC33XS2410_GLB_CTRL_MODE, + MC33XS2410_GLB_CTRL_MODE_NORMAL); + if (ret < 0) + return dev_err_probe(dev, ret, + "Failed to transition to normal mode\n"); + + ret =3D devm_pwmchip_add(dev, chip); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to add pwm chip\n"); + + return 0; +} + +static const struct spi_device_id mc33xs2410_spi_id[] =3D { + { "mc33xs2410" }, + { } +}; +MODULE_DEVICE_TABLE(spi, mc33xs2410_spi_id); + +static const struct of_device_id mc33xs2410_of_match[] =3D { + { .compatible =3D "nxp,mc33xs2410" }, + { } +}; +MODULE_DEVICE_TABLE(of, mc33xs2410_of_match); + +static struct spi_driver mc33xs2410_driver =3D { + .driver =3D { + .name =3D "mc33xs2410-pwm", + .of_match_table =3D mc33xs2410_of_match, + }, + .probe =3D mc33xs2410_probe, + .id_table =3D mc33xs2410_spi_id, +}; +module_spi_driver(mc33xs2410_driver); + +MODULE_DESCRIPTION("NXP MC33XS2410 high-side switch driver"); +MODULE_AUTHOR("Dimitri Fedrau "); +MODULE_LICENSE("GPL"); --=20 2.39.5