From nobody Thu Nov 28 22:46:11 2024 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F5FD18A6BB; Fri, 27 Sep 2024 11:19:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727435942; cv=none; b=aeMfvFV2l7sQLvpzHh1NyBOndoNHlbwnWpfbdsgeTE14TTj3VJ66GKpogj4XRH0Pel0KiYUzFhI6dZtr9YdwQeyXjQMhT7CL0J+spAV45y7GWFADPsotFqsrjFocNNJkEuPIdxeuHdkxp+jFbOkWgzMbn7VMecMMMql3iW4qRfg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727435942; c=relaxed/simple; bh=Fqa9hGmVn1N8eJjVQ7NWS8v3GVHz4nMz2b3G4iZT1Vg=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=gpUqGPblnbXqjKwqHSsOdx6ePi95NM6vnyDzijnQaVOf8WppRvEUAJWUBDYcLZr0FX3qrt7bD6xazbWcQx+xtUe6zVJmKAwKU4HxKX49XFte2IPvFZ9gg1+2uDdw/vsSVZM6QKw8RLfPwxZJo3BuiM4wBuJE67iHfDap0tAY3vU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Fri, 27 Sep 2024 19:17:45 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 27 Sep 2024 19:17:45 +0800 From: Billy Tsai To: , , , , , , , , , , , , , , Subject: [PATCH v6 6/7] gpio: aspeed: Add the flush write to ensure the write complete. Date: Fri, 27 Sep 2024 19:17:43 +0800 Message-ID: <20240927111744.3511373-7-billy_tsai@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240927111744.3511373-1-billy_tsai@aspeedtech.com> References: <20240927111744.3511373-1-billy_tsai@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Performing a dummy read ensures that the register write operation is fully completed, mitigating any potential bus delays that could otherwise impact the frequency of bitbang usage. E.g., if the JTAG application uses GPIO to control the JTAG pins (TCK, TMS, TDI, TDO, and TRST), and the application sets the TCK clock to 1 MHz, the GPIO's high/low transitions will rely on a delay function to ensure the clock frequency does not exceed 1 MHz. However, this can lead to rapid toggling of the GPIO because the write operation is POSTed and does not wait for a bus acknowledgment. Signed-off-by: Billy Tsai Reviewed-by: Andrew Jeffery --- drivers/gpio/gpio-aspeed.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c index d6a35e230370..7cea3c5ba696 100644 --- a/drivers/gpio/gpio-aspeed.c +++ b/drivers/gpio/gpio-aspeed.c @@ -406,6 +406,8 @@ static void __aspeed_gpio_set(struct gpio_chip *gc, uns= igned int offset, struct aspeed_gpio *gpio =3D gpiochip_get_data(gc); =20 gpio->config->llops->reg_bit_set(gpio, offset, reg_val, val); + // flush write + gpio->config->llops->reg_bit_get(gpio, offset, reg_val); } =20 static void aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, --=20 2.25.1