From nobody Thu Nov 28 20:36:00 2024 Received: from mail-pj1-f45.google.com (mail-pj1-f45.google.com [209.85.216.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12A76185956 for ; Fri, 27 Sep 2024 10:36:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727433413; cv=none; b=IePHif1UJjDiUex/XuGiVCnQR80CvuxNpKqipB9BQeyyoaOaxEFCo5Yi3HXkNtqDzVXS0xTJR1RPUAQqvlloRCL1JC7zLA0ZJE+3HSG5IHHmfOg9ccTyD8bvHrlAOaQmPEuNxU7FImbtz9/HxJ/qMfiSqHrgMClygR+QZ4Gi0gE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727433413; c=relaxed/simple; bh=y3FXP+giOaa0bTHNOIiOqrz67Of+uUBaKr7xcqryCuE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MhQvdaKh83t1tcHEqOwmssCCo9t+bfUXRnnziJ4UV7eZLJA4C3g+rDPfiydYNMuxFrzURUkSsz7pKgB0dokbh1++y7f//dvRHvqQZzMPjYmkomxgB76qf/ifxvG+6QGbNxyRBPJ2xf29INzAbHYrhrGajorBNrB0E/opFBRw0Ew= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=endlessos.org; spf=pass smtp.mailfrom=endlessos.org; dkim=pass (2048-bit key) header.d=endlessos.org header.i=@endlessos.org header.b=jSGCrRrA; arc=none smtp.client-ip=209.85.216.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=endlessos.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=endlessos.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=endlessos.org header.i=@endlessos.org header.b="jSGCrRrA" Received: by mail-pj1-f45.google.com with SMTP id 98e67ed59e1d1-2e06acff261so1479118a91.2 for ; Fri, 27 Sep 2024 03:36:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=endlessos.org; s=google; t=1727433411; x=1728038211; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=G55JHJhI3qkxlwOlcFB2xhqazWP5g+D6GuyYd2HAN1Q=; b=jSGCrRrAOdE7/wjdcR20hhFGpGuuD/eAAqySx1LVLYIP/mOGevML0Lc1/EV74Y5nOJ PBDExRN501LK8WqEtm/eoUfu4+nrdhduVNns8yeNqZlQ0VmnmsOY3Tpr+Pui6FJV2MbZ DNSqwA9luvWFZsRcdfNzmG/TgtoK4vvw1oJ5URH4sLojLPtZSwY5Eola3MJfc38ySMb8 WCVEHbGh89xd2dGJB34g7v1elf4+NWftq2CV5WsouJkdhrWNdTsuOH5wBhOxiUjlOLcy r+zh/i1mgblvjbwlhV+y5TLL6xqCY8cOM/c4HL535yAA7bIi6bcirRUbwg0veJGoCAfS 8+hg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727433411; x=1728038211; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G55JHJhI3qkxlwOlcFB2xhqazWP5g+D6GuyYd2HAN1Q=; b=YueqOj7ld592oy/P+TTR0G8nhYaNtTnCPDINIHTR0ZYwUudtcWS9PLZBVQK8B/6m2J NbDIdnaG3lHczFi5i3aBxwp6jdDUmBHwJaZbzyYGl5XciaoRl2RO3B8XANHRXILi9RDC g36HB8KzwIGqk7J115KqZclVqEHjcboSwEvIdZ/WCwrvuMsExu86Tso4a9l6wRRv4MAv 2Qu+pOLoboxMPM6wW4X/sWFEnyf6Tqh2OzFo43OSRumkSSkxy4N1rDOktzkaVnQGP/Oh t8ZJdBF0p4emGfkBDJXof/fIASr4CLciAA9od2zURBkv7m0rmfbr89kvhclBqtplxgH6 b/3w== X-Forwarded-Encrypted: i=1; AJvYcCXgyW66fTB5wK7059hSEIyBN1cCbKFxoWRbSDt/+tyBnvzIX0OBJegIkYpUjpGUXXA7XU+IxtIwy7bCD9g=@vger.kernel.org X-Gm-Message-State: AOJu0YwydVc4eum3J/6ugESyVb6fX8Mt2Quwq2uhltsmvX0/F5XIvDqm HeKN2njGOoqw/XfmagS+xUW6OPAXlqv/UkNt7ScZGS5LoMQ8Yrcf8ztUZQS3yHg= X-Google-Smtp-Source: AGHT+IEOCmycZY2cGaK5utdLVzhwCqkIWWFB/+435nxWSLC1tqzJCayG612KqIrzMA24Q+k1herCcA== X-Received: by 2002:a17:90b:360c:b0:2d3:c87e:b888 with SMTP id 98e67ed59e1d1-2e0b8ebcd31mr3051772a91.27.1727433411235; Fri, 27 Sep 2024 03:36:51 -0700 (PDT) Received: from localhost.localdomain ([123.51.167.56]) by smtp.googlemail.com with ESMTPSA id 98e67ed59e1d1-2e06e1cd35asm5177819a91.24.2024.09.27.03.36.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Sep 2024 03:36:50 -0700 (PDT) From: Jian-Hong Pan To: Bjorn Helgaas Cc: Johan Hovold , David Box , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Kuppuswamy Sathyanarayanan , Nirmal Patel , Jonathan Derrick , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux@endlessos.org, Jian-Hong Pan Subject: [PATCH v10 1/3] PCI: vmd: Set PCI devices to D0 before enable PCI PM's L1 substates Date: Fri, 27 Sep 2024 18:36:12 +0800 Message-ID: <20240927103612.24582-1-jhp@endlessos.org> X-Mailer: git-send-email 2.46.2 In-Reply-To: <20240927103231.24244-2-jhp@endlessos.org> References: <20240927103231.24244-2-jhp@endlessos.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The remapped PCIe Root Port and the child device have PCI PM L1 substates capability, but they are disabled originally. Here is a failed example on ASUS B1400CEAE: Capabilities: [900 v1] L1 PM Substates L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1- L1_PM_Substates+ PortCommonModeRestoreTime=3D32us PortTPowerOnTime=3D10us L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1- T_CommonMode=3D0us LTR1.2_Threshold=3D101376ns L1SubCtl2: T_PwrOn=3D50us Power on all of the VMD remapped PCI devices to D0 before enable PCI-PM L1 PM Substates by following "PCIe r6.0, sec 5.5.4". Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D218394 Signed-off-by: Jian-Hong Pan Reviewed-by: Kuppuswamy Sathyanarayanan --- v2: - Power on the VMD remapped devices with pci_set_power_state_locked() - Prepare the PCIe LTR parameters before enable L1 Substates - Add note into the comments of both pci_enable_link_state() and pci_enable_link_state_locked() for kernel-doc. - The original patch set can be split as individual patches. v3: - Re-send for the missed version information. - Split drivers/pci/pcie/aspm.c modification into following patches. - Fix the comment for enasuring the PCI devices in D0. v4: - The same v5: - Tweak the commit title and message - Change the goto label from out_enable_link_state to out_state_change v6~8: - The same v9: - Update L1 PM Substates information against kernel v6.11 in commit message v10: - The same drivers/pci/controller/vmd.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/vmd.c b/drivers/pci/controller/vmd.c index 264a180403a0..11870d1fc818 100644 --- a/drivers/pci/controller/vmd.c +++ b/drivers/pci/controller/vmd.c @@ -740,11 +740,9 @@ static int vmd_pm_enable_quirk(struct pci_dev *pdev, v= oid *userdata) if (!(features & VMD_FEAT_BIOS_PM_QUIRK)) return 0; =20 - pci_enable_link_state_locked(pdev, PCIE_LINK_STATE_ALL); - pos =3D pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_LTR); if (!pos) - return 0; + goto out_state_change; =20 /* * Skip if the max snoop LTR is non-zero, indicating BIOS has set it @@ -752,7 +750,7 @@ static int vmd_pm_enable_quirk(struct pci_dev *pdev, vo= id *userdata) */ pci_read_config_dword(pdev, pos + PCI_LTR_MAX_SNOOP_LAT, <r_reg); if (!!(ltr_reg & (PCI_LTR_VALUE_MASK | PCI_LTR_SCALE_MASK))) - return 0; + goto out_state_change; =20 /* * Set the default values to the maximum required by the platform to @@ -764,6 +762,13 @@ static int vmd_pm_enable_quirk(struct pci_dev *pdev, v= oid *userdata) pci_write_config_dword(pdev, pos + PCI_LTR_MAX_SNOOP_LAT, ltr_reg); pci_info(pdev, "VMD: Default LTR value set by driver\n"); =20 +out_state_change: + /* + * Ensure devices are in D0 before enabling PCI-PM L1 PM Substates, per + * PCIe r6.0, sec 5.5.4. + */ + pci_set_power_state_locked(pdev, PCI_D0); + pci_enable_link_state_locked(pdev, PCIE_LINK_STATE_ALL); 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charset="utf-8" According to "PCIe r6.0, sec 5.5.4", add note about D0 requirement in pci_enable_link_state() kernel-doc. Signed-off-by: Jian-Hong Pan Acked-by: Bjorn Helgaas Reviewed-by: Kuppuswamy Sathyanarayanan --- v3: - Fix as readable comments v4: - The same v5: - Tweak and simplify the commit message v6~10: - The same drivers/pci/pcie/aspm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index cee2365e54b8..bd0a8a05647e 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -1442,6 +1442,9 @@ static int __pci_enable_link_state(struct pci_dev *pd= ev, int state, bool locked) * touch the LNKCTL register. Also note that this does not enable states * disabled by pci_disable_link_state(). Return 0 or a negative errno. * + * Note: Ensure devices are in D0 before enabling PCI-PM L1 PM Substates, = per + * PCIe r6.0, sec 5.5.4. + * * @pdev: PCI device * @state: Mask of ASPM link states to enable */ @@ -1458,6 +1461,9 @@ EXPORT_SYMBOL(pci_enable_link_state); * can't touch the LNKCTL register. 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Fri, 27 Sep 2024 03:37:55 -0700 (PDT) From: Jian-Hong Pan To: Bjorn Helgaas Cc: Johan Hovold , David Box , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Kuppuswamy Sathyanarayanan , Nirmal Patel , Jonathan Derrick , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux@endlessos.org, Jian-Hong Pan Subject: [PATCH v10 3/3] PCI/ASPM: Make pci_save_aspm_l1ss_state save both child and parent's L1SS configuration Date: Fri, 27 Sep 2024 18:37:24 +0800 Message-ID: <20240927103723.24622-2-jhp@endlessos.org> X-Mailer: git-send-email 2.46.2 In-Reply-To: <20240927103231.24244-2-jhp@endlessos.org> References: <20240927103231.24244-2-jhp@endlessos.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" PCI devices' parameters on the VMD bus have been programmed properly originally. But, cleared after pci_reset_bus() and have not been restored correctly. This leads the link's L1.2 between PCIe Root Port and child device gets wrong configs. Here is a failed example on ASUS B1400CEAE with enabled VMD. Both PCIe bridge and NVMe device should have the same LTR1.2_Threshold value. However, they are configured as different values in this case: 10000:e0:06.0 PCI bridge [0604]: Intel Corporation 11th Gen Core Processor = PCIe Controller [8086:9a09] (rev 01) (prog-if 00 [Normal decode]) ... Capabilities: [200 v1] L1 PM Substates L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substat= es+ PortCommonModeRestoreTime=3D45us PortTPowerOnTime=3D50us L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1- T_CommonMode=3D0us LTR1.2_Threshold=3D0ns L1SubCtl2: T_PwrOn=3D0us 10000:e1:00.0 Non-Volatile memory controller [0108]: Sandisk Corp WD Blue S= N550 NVMe SSD [15b7:5009] (rev 01) (prog-if 02 [NVM Express]) ... Capabilities: [900 v1] L1 PM Substates L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1- L1_PM_Substat= es+ PortCommonModeRestoreTime=3D32us PortTPowerOnTime=3D10us L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1- T_CommonMode=3D0us LTR1.2_Threshold=3D101376ns L1SubCtl2: T_PwrOn=3D50us Here is VMD mapped PCI device tree: -+-[0000:00]-+-00.0 Intel Corporation Device 9a04 | ... \-[10000:e0]-+-06.0-[e1]----00.0 Sandisk Corp WD Blue SN550 NVMe SSD \-17.0 Intel Corporation Tiger Lake-LP SATA Controller When pci_reset_bus() resets the bus [e1] of the NVMe, it only saves and restores NVMe's state before and after reset. Because bus [e1] has only one device: 10000:e1:00.0 NVMe. The PCIe bridge is missed. However, when it restores the NVMe's state, it also restores the ASPM L1SS between the PCIe bridge and the NVMe by pci_restore_aspm_l1ss_state(). The NVMe's L1SS is restored correctly. But, the PCIe bridge's L1SS is restored with the wrong value 0x0 [1]. Because, the parent device (PCIe bridge)'s L1SS is not saved by pci_save_aspm_l1ss_state() before reset. That is why pci_restore_aspm_l1ss_state() gets the parent device (PCIe bridge)'s saved state capability data and restores L1SS with value 0. So, if the PCI device has a parent, make pci_save_aspm_l1ss_state() save the parent's L1SS configuration, too. This is symmetric on pci_restore_aspm_l1ss_state(). [1]: https://lore.kernel.org/linux-pci/CAPpJ_eexU0gCHMbXw_z924WxXw0+B6SdS4e= G9oGpEX1wmnMLkQ@mail.gmail.com/ Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D218394 Signed-off-by: Jian-Hong Pan Suggested-by: Ilpo J=C3=A4rvinen --- v9: - Drop the v8 fix about drivers/pci/pcie/aspm.c. Use this in VMD instead. v10: - Drop the v9 fix about drivers/pci/controller/vmd.c - Fix in PCIe ASPM to make it symmetric between pci_save_aspm_l1ss_state() and pci_restore_aspm_l1ss_state() drivers/pci/pcie/aspm.c | 39 +++++++++++++++++++++++++++++++-------- 1 file changed, 31 insertions(+), 8 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index bd0a8a05647e..823aaf813978 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -81,24 +81,47 @@ void pci_configure_aspm_l1ss(struct pci_dev *pdev) =20 void pci_save_aspm_l1ss_state(struct pci_dev *pdev) { - struct pci_cap_saved_state *save_state; - u16 l1ss =3D pdev->l1ss; + struct pci_cap_saved_state *pl_save_state, *cl_save_state; + struct pci_dev *parent; u32 *cap; =20 /* * Save L1 substate configuration. The ASPM L0s/L1 configuration * in PCI_EXP_LNKCTL_ASPMC is saved by pci_save_pcie_state(). */ - if (!l1ss) + if (!pdev->l1ss) return; =20 - save_state =3D pci_find_saved_ext_cap(pdev, PCI_EXT_CAP_ID_L1SS); - if (!save_state) + cl_save_state =3D pci_find_saved_ext_cap(pdev, PCI_EXT_CAP_ID_L1SS); + if (!cl_save_state) return; =20 - cap =3D &save_state->cap.data[0]; - pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL2, cap++); - pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, cap++); + cap =3D &cl_save_state->cap.data[0]; + pci_read_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL2, cap++); + pci_read_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL1, cap++); + + /* + * If here is a parent device and it has not saved state, save parent's + * L1 substate configuration, too. This is symmetric on + * pci_restore_aspm_l1ss_state(). + */ + if (!pdev->bus || !pdev->bus->self) + return; + + parent =3D pdev->bus->self; + if (!parent->l1ss) + return; + + pl_save_state =3D pci_find_saved_ext_cap(parent, PCI_EXT_CAP_ID_L1SS); + if (!pl_save_state) + return; + + if (parent->state_saved) + return; + + cap =3D &pl_save_state->cap.data[0]; + pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, cap++); + pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, cap++); } =20 void pci_restore_aspm_l1ss_state(struct pci_dev *pdev) --=20 2.46.2