From nobody Fri Nov 29 00:40:58 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B38A173336; Fri, 27 Sep 2024 06:31:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727418704; cv=none; b=gQlah88i5iOXNKFDPWtHNq13k1bqSjYg37AHkBRxssPmCFIsMtFDmXiYY5nr524I+8H1UN317uVhzvw6ELY17AjpPnaFw7uJSClEnkkMGNQ38Lrj1jn3a2JMLq44olR8BEfspoQrowco8vsS26KtFUqUjo2FHYu6r9Va/kbUAyI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727418704; c=relaxed/simple; bh=/2dAba0R+HumaxxwOTWbg507C1IjCPjM+9qeOArLu04=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=hU5ObvaO8ykvOCwx5ZBx2997S8kigvHMCn+vrO9R02ejrEQ/ArKwAygEheHgyItdrfhw4AYXgU0N8M6+jWiRXJUDXeC3vmSNZRNbN8cIgg7Gx23ZFEQMBOR8Sxtuhtfv0wbz9a5dvGJhiK9mzESTCzbRz9FPGxFD7/vnVYDo3EM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=qualcomm.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=K8OGhxIH; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="K8OGhxIH" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48QG9dXY014808; Fri, 27 Sep 2024 06:31:34 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=8AnIdhR4FsD DjTZHfOLfyp5ljsb5boFCiTGmHd0DM9g=; b=K8OGhxIHhPx8ERbhXtfAgr50Q2h aAJGkGWOigRcOddC9qk/hxRo9cfQhcC5hwqv2/vSaLjHNXnRgSvM/QooYhNgil+g x2zho/e/iO4QKNmhQvdKbjqhTGlLm6o1+gsi7dsfyl6S+AI4xj8H11CmWaGssCEd rH8N8S+VB5aelLbDnLd7rEYyODcFu04jUfuXQzy1f77Y6N/PwKI2QWeC1J4bi93j Nm+Hv046bvjhZ7625Ra8hcXX6/Y4nJ//i34jigyHGOcmaFJ19Bj8ei7mz5djtDd1 JgemVHG/Hdhk60+hqHGE4mtalAz8AE78pZFaka2b9zmf9MWQmJUxeEgqJug== Received: from apblrppmta02.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 41spc31vhw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 27 Sep 2024 06:31:33 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 48R6UB6G000828; Fri, 27 Sep 2024 06:31:30 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 41sq7mnbnj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 27 Sep 2024 06:31:30 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 48R6VJGF001832; Fri, 27 Sep 2024 06:31:29 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-msavaliy-hyd.qualcomm.com [10.213.110.207]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 48R6VTeT001898 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 27 Sep 2024 06:31:29 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 429934) id 6C5B82408B; Fri, 27 Sep 2024 12:01:28 +0530 (+0530) From: Mukesh Kumar Savaliya To: konrad.dybcio@linaro.org, andersson@kernel.org, andi.shyti@kernel.org, linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, conor+dt@kernel.org, agross@kernel.org, devicetree@vger.kernel.org, vkoul@kernel.org, linux@treblig.org, dan.carpenter@linaro.org, Frank.Li@nxp.com, konradybcio@kernel.org, bryan.odonoghue@linaro.org, krzk+dt@kernel.org, robh@kernel.org Cc: Mukesh Kumar Savaliya Subject: [PATCH v3 3/4] soc: qcom: geni-se: Do not keep GPIOs to sleep state for shared SE usecase Date: Fri, 27 Sep 2024 12:01:07 +0530 Message-Id: <20240927063108.2773304-4-quic_msavaliy@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240927063108.2773304-1-quic_msavaliy@quicinc.com> References: <20240927063108.2773304-1-quic_msavaliy@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Jz-pNDjSefAdGgUj2qame-YoJtJU_MW0 X-Proofpoint-ORIG-GUID: Jz-pNDjSefAdGgUj2qame-YoJtJU_MW0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 suspectscore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 malwarescore=0 adultscore=0 phishscore=0 mlxlogscore=999 bulkscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409270043 Content-Type: text/plain; charset="utf-8" Currently the driver provides a function called geni_serial_resources_off() to turn off resources like clocks and pinctrl. For shared SE between two SS, we don't need to keep pinctrl to sleep state as other SS may be actively transferring data over SE. Hence,bypass keeping pinctrl to sleep state conditionally using shared_geni_se flag. Signed-off-by: Mukesh Kumar Savaliya --- drivers/soc/qcom/qcom-geni-se.c | 14 ++++++++++---- include/linux/soc/qcom/geni-se.h | 3 +++ 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-s= e.c index 2e8f24d5da80..89cf18699336 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. +// Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. =20 /* Disable MMIO tracing to prevent excessive logging of unwanted MMIO trac= es */ #define __DISABLE_TRACE_MMIO__ @@ -503,10 +504,15 @@ int geni_se_resources_off(struct geni_se *se) =20 if (has_acpi_companion(se->dev)) return 0; - - ret =3D pinctrl_pm_select_sleep_state(se->dev); - if (ret) - return ret; + /* Keep pinctrl to sleep state only for regular usecase. + * Do not sleep pinctrl for shared SE because other SS(subsystems) + * may continueto perform transfer. + */ + if (se->shared_geni_se =3D=3D false) { + ret =3D pinctrl_pm_select_sleep_state(se->dev); + if (ret) + return ret; + } =20 geni_se_clks_off(se); return 0; diff --git a/include/linux/soc/qcom/geni-se.h b/include/linux/soc/qcom/geni= -se.h index c3bca9c0bf2c..359041c64ad8 100644 --- a/include/linux/soc/qcom/geni-se.h +++ b/include/linux/soc/qcom/geni-se.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ =20 #ifndef _LINUX_QCOM_GENI_SE @@ -61,6 +62,7 @@ struct geni_icc_path { * @num_clk_levels: Number of valid clock levels in clk_perf_tbl * @clk_perf_tbl: Table of clock frequency input to serial engine clock * @icc_paths: Array of ICC paths for SE + * @shared_geni_se: Tells if SE is used by two SS in shared environment. */ struct geni_se { void __iomem *base; @@ -70,6 +72,7 @@ struct geni_se { unsigned int num_clk_levels; unsigned long *clk_perf_tbl; struct geni_icc_path icc_paths[3]; + bool shared_geni_se; }; =20 /* Common SE registers */ --=20 2.25.1