From nobody Thu Nov 28 21:50:28 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3168C749C; Fri, 27 Sep 2024 05:51:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727416314; cv=none; b=GZB5+Jzcb/yEGgUCtMMoJotqkN6HJBjoaYuoYvZ6YuI1LCw4EzegH5q76WT4Iphc+lAFULEO0LS+8sMMmw7eyDjjI0RsyZmQHreHP50NxKNOiDJG0KOKFrO1g9WxENEVOl7qtGFl7BEFJi8ZvF55oRX3Sf6ST6ycr4zN9YWiJco= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727416314; c=relaxed/simple; bh=vWZf6FFs4h1bjrlf72/WtC13v798TwiG9h+Y/cshKBs=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=eZ+1Ne+uKN5wGXo9fLyMyFumjG2cDA8DLQnkuKz56S5d2e7AlwUDSJNb9FM/bSC497HlP4Zc4uKLVE95GPdvbr1V0BJfbwX8ZVHGD5bLswiSyxdmm9QsvPVeSv4JdwTcTEs6Jvg7nzR3Blx7ae5W12k62uJyD0uX6D/ou6vsqf0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=F13NfxBv; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="F13NfxBv" X-UUID: 93721f067c9411ef8b96093e013ec31c-20240927 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=FZu0ZPTLpZWjX8yCbYqdxdHinvG8NnXZbGPHD2DiMCg=; b=F13NfxBvUXOLvVc5TZ35BA+kQkDddvFPEHO72FuhfZ2r9qUkxtJAcdXAkXAy+pE38r+deuVs6ak0F0Jg8WYCcvWCgb0466JXBdz+BD0t8gx1jZ4SB+XmzYPwmm1MwDKoDE39xa4o+vSVaADO7waKey0vWQHqF5r5OhLPw1gYEaY=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.41,REQID:f377f6a7-e040-4a52-8584-01eeb4d7394c,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:6dc6a47,CLOUDID:62cda59e-8e9a-4ac1-b510-390a86b53c0a,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULS X-UUID: 93721f067c9411ef8b96093e013ec31c-20240927 Received: from mtkmbs09n1.mediatek.inc [(172.21.101.35)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1090322006; Fri, 27 Sep 2024 13:51:44 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 27 Sep 2024 13:51:43 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 27 Sep 2024 13:51:43 +0800 From: Moudy Ho To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , "jason-jh . lin" , Macpaul Lin CC: , , , , , Moudy Ho , Moudy Ho Subject: [PATCH v2] dt-bindings: display: mediatek: split: add clocks count constraint for MT8195 Date: Fri, 27 Sep 2024 13:51:40 +0800 Message-ID: <20240927055140.19688-1-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Moudy Ho The display node in mt8195.dtsi was triggering a CHECK_DTBS error due to an excessively long 'clocks' property: display@14f06000: clocks: [[31, 14], [31, 43], [31, 44]] is too long To resolve this issue, apply the limit by setting 'maxItems: 3' in MT8195 additional condition. Fixes: 4ed545e7d100 ("dt-bindings: display: mediatek: disp: split each bloc= k to individual yaml") Signed-off-by: Macpaul Lin Signed-off-by: Moudy Ho -- The purpose of this patch is to separate the corrections for MediaTek SPLIT CHECK_DTBS error from the original mailing list mentioned below: https://lore.kernel.org/all/20240924103156.13119-2-macpaul.lin@mediatek.com/ Changes since v1: - Adding functional descriptions and quantity restrictions. --- .../bindings/display/mediatek/mediatek,split.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,sp= lit.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,spli= t.yaml index e4affc854f3d..bce1b8b866ce 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml @@ -57,6 +57,9 @@ properties: clocks: items: - description: SPLIT Clock + - description: HDMI RX Clock + - description: HDMI Metadata Clock + minItems: 1 =20 required: - compatible @@ -72,6 +75,9 @@ allOf: const: mediatek,mt8195-mdp3-split =20 then: + properties: + clocks: + maxItems: 3 required: - mediatek,gce-client-reg =20 --=20 2.34.1