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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e06e16d6d2sm5671744a91.2.2024.09.27.06.41.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Sep 2024 06:41:58 -0700 (PDT) From: Max Hsu Date: Fri, 27 Sep 2024 21:41:44 +0800 Subject: [PATCH RFC v2 2/3] riscv: Add Svukte extension support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240927-dev-maxh-svukte-rebase-2-v2-2-9afe57c33aee@sifive.com> References: <20240927-dev-maxh-svukte-rebase-2-v2-0-9afe57c33aee@sifive.com> In-Reply-To: <20240927-dev-maxh-svukte-rebase-2-v2-0-9afe57c33aee@sifive.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Atish Patra Cc: Palmer Dabbelt , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Max Hsu , Samuel Holland X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3103; i=max.hsu@sifive.com; h=from:subject:message-id; bh=2iAOqQjnUXTcZ5Cs8EpYQntXVuHf3Et98OZwyjYbx+4=; b=owEB7QES/pANAwAKAdID/Z0HeUC9AcsmYgBm9rYemwDJvWM0Es7Z0BdQVJl6wPqKNr+icYn8S ixNxmwo4PSJAbMEAAEKAB0WIQTqXmcbOhS2KZE9X2jSA/2dB3lAvQUCZva2HgAKCRDSA/2dB3lA vcTVC/9ZFgIJK+oxCZZJE7Vz0znghLwi7WZa3X3R3Oqf1yywBf3G37oy1p5ti/thDZgLMXxS6Tq hPXpTrYShGZRznXe9vclpZaFnaboitKby3ugrzpm6Q+y58OboJoP0ml+GP7cSms6Tl/uLJuOc7F g4mtWMwiqacecSkekyhswbCvL7lAOMBzW0lqiQ+I4hCxrh7/zJ+i6bGe1CJ/tdwlTc+PxZwcC3x eIJVccd2Hf1c15KRYMsaFK85hiiWzn/D+38vKxfAvP5pEPRCmhbNbnhQ/sgUG/6OlRL8BRYsyu8 bhGUkRnP4DA/rthVm/hqQ8xefxIlrC94xa9Kh3g7LPe8Noc4Jv+kC+Yb7zHUZXCO3UzvdrhhMO/ C9ooqjtoz/fDVqcV6VXY+Oqb3QvadyPTAiBTiDya9vQTqyQxmWUxzdQhOMFCHGKloihnXpB58Sn 9oeYze98ONfxd9i83FVmco+5C01cnnYYMdcu7zUr2nT2HDwKpFt4vaFOrAt/j2xxkrc4s= X-Developer-Key: i=max.hsu@sifive.com; a=openpgp; fpr=EA5E671B3A14B629913D5F68D203FD9D077940BD Svukte extension introduce senvcfg.UKTE, hstatus.HUKTE. This patch add CSR bit definition, and detects if Svukte ISA extension is available, cpufeature will set the correspond bit field so the svukte-qualified memory accesses are protected in a manner that is timing-independent of the faulting virtual address. Since hstatus.HU is not enabled by linux, enabling hstatus.HUKTE will not be affective. This patch depends on patch "riscv: Per-thread envcfg CSR support" [1] Link: https://lore.kernel.org/linux-riscv/20240814081126.956287-1-samuel.ho= lland@sifive.com/ [1] Reviewed-by: Samuel Holland Signed-off-by: Max Hsu Reviewed-by: Deepak Gupta --- arch/riscv/include/asm/csr.h | 2 ++ arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 4 ++++ 3 files changed, 7 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 25966995da04e090ff22a11e35be9bc24712f1a8..62b50667d539c50a0bfdadd1c6a= b06cda948f6a8 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -122,6 +122,7 @@ #define HSTATUS_VSXL _AC(0x300000000, UL) #define HSTATUS_VSXL_SHIFT 32 #endif +#define HSTATUS_HUKTE _AC(0x01000000, UL) #define HSTATUS_VTSR _AC(0x00400000, UL) #define HSTATUS_VTW _AC(0x00200000, UL) #define HSTATUS_VTVM _AC(0x00100000, UL) @@ -195,6 +196,7 @@ /* xENVCFG flags */ #define ENVCFG_STCE (_AC(1, ULL) << 63) #define ENVCFG_PBMTE (_AC(1, ULL) << 62) +#define ENVCFG_UKTE (_AC(1, UL) << 8) #define ENVCFG_CBZE (_AC(1, UL) << 7) #define ENVCFG_CBCFE (_AC(1, UL) << 6) #define ENVCFG_CBIE_SHIFT 4 diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 46d9de54179ed40aa7b1ea0ec011fd6eea7218df..3591a4f40131ff5958c07857a1b= d1624723d6550 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -93,6 +93,7 @@ #define RISCV_ISA_EXT_ZCMOP 84 #define RISCV_ISA_EXT_ZAWRS 85 #define RISCV_ISA_EXT_SVVPTC 86 +#define RISCV_ISA_EXT_SVUKTE 87 =20 #define RISCV_ISA_EXT_XLINUXENVCFG 127 =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 3a8eeaa9310c32fce2141aff534dc4432b32abbe..e0853cae1dc0ba844d5969a42c3= 0d44287e3250a 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -381,6 +381,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), + __RISCV_ISA_EXT_SUPERSET(svukte, RISCV_ISA_EXT_SVUKTE, riscv_xlinuxenvcfg= _exts), __RISCV_ISA_EXT_DATA(svvptc, RISCV_ISA_EXT_SVVPTC), }; =20 @@ -921,6 +922,9 @@ void riscv_user_isa_enable(void) { if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZI= CBOZ)) csr_set(CSR_ENVCFG, ENVCFG_CBZE); + + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SVUKTE)) + current->thread.envcfg |=3D ENVCFG_UKTE; } =20 #ifdef CONFIG_RISCV_ALTERNATIVE --=20 2.43.2