From nobody Thu Nov 28 23:57:08 2024 Received: from mail-yw1-f202.google.com (mail-yw1-f202.google.com [209.85.128.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69B201862BD for ; Thu, 26 Sep 2024 17:51:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727373071; cv=none; b=Qq2YZsNOeu8QYWGo+iMA4fhnaB1zOFQjMPkzWwDnowlEqo1mMupvcp2v8sShFmwq5WRg+Gu3EFvf0j3F0xsiay3MUJmtgiYe0+f+c1cF3x+SYL6dy+OgyOShULdFHB+j/ISv0amcz4r5I5s9CHyBisge3N/piQ55GdHcP8D2IqQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727373071; c=relaxed/simple; bh=xiYlCcj55q/KTy38gNYIg9xqcm3mQWwU1zaCis09kco=; h=Date:In-Reply-To:Message-Id:Mime-Version:References:Subject:From: To:Content-Type; b=R/8lZ85iG9VeK3JdVSHOzvTvcyUcJoMGnln6oOlA+KYMSnANPuaqyPj3ztLDIlW85y5nigEArv3HZoFTV6lkwRUpQGrhnRXPtqUaB6fT/AwnlnHFB5M78/yYA+eaKtlSINwY7DbEEBBkivEf/NS3jxWjVtoZRWx7HexoRtjDkt0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--irogers.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=h40Wt5TT; arc=none smtp.client-ip=209.85.128.202 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--irogers.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="h40Wt5TT" Received: by mail-yw1-f202.google.com with SMTP id 00721157ae682-6e211e439a3so24278447b3.3 for ; Thu, 26 Sep 2024 10:51:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1727373069; x=1727977869; darn=vger.kernel.org; h=to:from:subject:references:mime-version:message-id:in-reply-to:date :from:to:cc:subject:date:message-id:reply-to; bh=uYgybefDNqgi10ykyol6GXFWf2oN+4a+ozUSONYeQto=; b=h40Wt5TTvQUph1wWY5BFoMvvEMOanioQP6VKSoN6lrcVHDVmuelCHUg/to0bPyWCqv QE1tFgeQZxwfhCfCPj74dWkXUEvmGwKQmdxbfrJoN39AMZ9rFp0m9quhNe0YevYDvL5n ThjI3meFsadGLgzJ5XUphq8SvRfLalayWp+TALpZvTA+IFumVhErUlDifUiLLU2NDI14 MYX1zwmFQ6OFBXKO2JDwZPDGstl4GWzO4uw8wRX645KsdNcOEhEog9+ZnlFj+7dG9LMk Q3DbDcv2HnUt0dzHZiP/p2p/R4sHGx2HVdUCJea9U4Hmp7FoBPYTbVAfvz3mCPFQuqeH VedQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727373069; x=1727977869; h=to:from:subject:references:mime-version:message-id:in-reply-to:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=uYgybefDNqgi10ykyol6GXFWf2oN+4a+ozUSONYeQto=; b=Y7iu3wTg16T9+VohtoD/aheimc98pc66tksgSNbUloCnalbh99r5TN4d7jFUPX9Be4 Jr7mPwSU5zJ/so+ACHVRO7xMu8K0W6RxnKfw8f83LeKfs69SulSk/iIaq5gNqZ8B/Jnr apSbWtUCTpc/YGNmwT/LgJar6GBjPh2Vmuic1D8JsoZmmQ5tq5LBnVh5UurBK8igmU8t RaKSsDKjsTCfOOgzfd+s2GS0DC9JZDYWGxbXab46edRKiBUmDWBr28/vkyxi9qN0uA2N LB8STCY2yqb165VgA40LyNpqf9kh5X3zDoh027dyF2DxW0MnR61MNV7x03ol3JmQSzXq O56g== X-Forwarded-Encrypted: i=1; AJvYcCXR5EqmIAd98UDBckKS6FEsqMtjNGBiJSDnuwzHoDyp0kgD4CesEUhbHs5cgYyD7beBy3eomvYxB5jeCBY=@vger.kernel.org X-Gm-Message-State: AOJu0YwKHaASrWENgZCEGPErAhD26Zr7y1oAfr1d/lucwz/7T0dVvUn/ w7V+RUJJVYGIyklXXTFD2pI9+LsFWJTgGUqJLI8BhacZQxJaudEjfQ8PsIkkoFWMst9PrfvWBz1 Tj4HJBQ== X-Google-Smtp-Source: AGHT+IHQ92aHOX0/N/oCEF9QBP095GGMFbhVR9c/HKIZodCC4REiJ40TGb7Xaeh61No0JuXwRBjIbb+ISZi8 X-Received: from irogers.svl.corp.google.com ([2620:15c:2a3:200:6894:6d8b:d227:e5d2]) (user=irogers job=sendgmr) by 2002:a05:6902:1363:b0:e0b:fe07:1e22 with SMTP id 3f1490d57ef6-e2604b109cdmr224276.1.1727373069192; Thu, 26 Sep 2024 10:51:09 -0700 (PDT) Date: Thu, 26 Sep 2024 10:50:24 -0700 In-Reply-To: <20240926175035.408668-1-irogers@google.com> Message-Id: <20240926175035.408668-12-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240926175035.408668-1-irogers@google.com> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog Subject: [PATCH v4 11/22] perf jevents: Add load store breakdown metrics ldst for Intel From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Give breakdown of number of instructions. Use the counter mask (cmask) to show the number of cycles taken to retire the instructions. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/intel_metrics.py | 86 +++++++++++++++++++++++++- 1 file changed, 85 insertions(+), 1 deletion(-) diff --git a/tools/perf/pmu-events/intel_metrics.py b/tools/perf/pmu-events= /intel_metrics.py index 4ddc68006b10..d528b97e8822 100755 --- a/tools/perf/pmu-events/intel_metrics.py +++ b/tools/perf/pmu-events/intel_metrics.py @@ -2,7 +2,7 @@ # SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause) from metric import (d_ratio, has_event, max, CheckPmu, Event, JsonEncodeMe= tric, JsonEncodeMetricGroupDescriptions, Literal, LoadEvents, - Metric, MetricGroup, MetricRef, Select) + Metric, MetricConstraint, MetricGroup, MetricRef, Sele= ct) import argparse import json import math @@ -509,6 +509,89 @@ def IntelSwpf() -> Optional[MetricGroup]: ], description=3D"Software prefetch instruction breakdown") =20 =20 +def IntelLdSt() -> Optional[MetricGroup]: + if _args.model in [ + "bonnell", + "nehalemep", + "nehalemex", + "westmereep-dp", + "westmereep-sp", + "westmereex", + ]: + return None + LDST_LD =3D Event("MEM_INST_RETIRED.ALL_LOADS", "MEM_UOPS_RETIRED.ALL_LO= ADS") + LDST_ST =3D Event("MEM_INST_RETIRED.ALL_STORES", "MEM_UOPS_RETIRED.ALL_S= TORES") + LDST_LDC1 =3D Event(f"{LDST_LD.name}/cmask=3D1/") + LDST_STC1 =3D Event(f"{LDST_ST.name}/cmask=3D1/") + LDST_LDC2 =3D Event(f"{LDST_LD.name}/cmask=3D2/") + LDST_STC2 =3D Event(f"{LDST_ST.name}/cmask=3D2/") + LDST_LDC3 =3D Event(f"{LDST_LD.name}/cmask=3D3/") + LDST_STC3 =3D Event(f"{LDST_ST.name}/cmask=3D3/") + ins =3D Event("instructions") + LDST_CYC =3D Event("CPU_CLK_UNHALTED.THREAD", + "CPU_CLK_UNHALTED.CORE_P", + "CPU_CLK_UNHALTED.THREAD_P") + LDST_PRE =3D None + try: + LDST_PRE =3D Event("LOAD_HIT_PREFETCH.SWPF", "LOAD_HIT_PRE.SW_PF") + except: + pass + LDST_AT =3D None + try: + LDST_AT =3D Event("MEM_INST_RETIRED.LOCK_LOADS") + except: + pass + cyc =3D LDST_CYC + + ld_rate =3D d_ratio(LDST_LD, interval_sec) + st_rate =3D d_ratio(LDST_ST, interval_sec) + pf_rate =3D d_ratio(LDST_PRE, interval_sec) if LDST_PRE else None + at_rate =3D d_ratio(LDST_AT, interval_sec) if LDST_AT else None + + ldst_ret_constraint =3D MetricConstraint.GROUPED_EVENTS + if LDST_LD.name =3D=3D "MEM_UOPS_RETIRED.ALL_LOADS": + ldst_ret_constraint =3D MetricConstraint.NO_GROUP_EVENTS_NMI + + return MetricGroup("ldst", [ + MetricGroup("ldst_total", [ + Metric("ldst_total_loads", "Load/store instructions total loads", + ld_rate, "loads"), + Metric("ldst_total_stores", "Load/store instructions total store= s", + st_rate, "stores"), + ]), + MetricGroup("ldst_prcnt", [ + Metric("ldst_prcnt_loads", "Percent of all instructions that are= loads", + d_ratio(LDST_LD, ins), "100%"), + Metric("ldst_prcnt_stores", "Percent of all instructions that ar= e stores", + d_ratio(LDST_ST, ins), "100%"), + ]), + MetricGroup("ldst_ret_lds", [ + Metric("ldst_ret_lds_1", "Retired loads in 1 cycle", + d_ratio(max(LDST_LDC1 - LDST_LDC2, 0), cyc), "100%", + constraint =3D ldst_ret_constraint), + Metric("ldst_ret_lds_2", "Retired loads in 2 cycles", + d_ratio(max(LDST_LDC2 - LDST_LDC3, 0), cyc), "100%", + constraint =3D ldst_ret_constraint), + Metric("ldst_ret_lds_3", "Retired loads in 3 or more cycles", + d_ratio(LDST_LDC3, cyc), "100%"), + ]), + MetricGroup("ldst_ret_sts", [ + Metric("ldst_ret_sts_1", "Retired stores in 1 cycle", + d_ratio(max(LDST_STC1 - LDST_STC2, 0), cyc), "100%", + constraint =3D ldst_ret_constraint), + Metric("ldst_ret_sts_2", "Retired stores in 2 cycles", + d_ratio(max(LDST_STC2 - LDST_STC3, 0), cyc), "100%", + constraint =3D ldst_ret_constraint), + Metric("ldst_ret_sts_3", "Retired stores in 3 more cycles", + d_ratio(LDST_STC3, cyc), "100%"), + ]), + Metric("ldst_ld_hit_swpf", "Load hit software prefetches per second", + pf_rate, "swpf/s") if pf_rate else None, + Metric("ldst_atomic_lds", "Atomic loads per second", + at_rate, "loads/s") if at_rate else None, + ], description =3D "Breakdown of load/store instructions") + + def main() -> None: global _args =20 @@ -538,6 +621,7 @@ def main() -> None: Tsx(), IntelBr(), IntelL2(), + IntelLdSt(), IntelPorts(), IntelSwpf(), ]) --=20 2.46.1.824.gd892dcdcdd-goog