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Signed-off-by: Ian Rogers --- tools/perf/pmu-events/intel_metrics.py | 158 +++++++++++++++++++++++++ 1 file changed, 158 insertions(+) diff --git a/tools/perf/pmu-events/intel_metrics.py b/tools/perf/pmu-events= /intel_metrics.py index 3ef4eb868580..4ddc68006b10 100755 --- a/tools/perf/pmu-events/intel_metrics.py +++ b/tools/perf/pmu-events/intel_metrics.py @@ -261,6 +261,163 @@ def IntelBr(): description=3D"breakdown of retired branch instructio= ns") =20 =20 +def IntelL2() -> Optional[MetricGroup]: + try: + DC_HIT =3D Event("L2_RQSTS.DEMAND_DATA_RD_HIT") + except: + return None + try: + DC_MISS =3D Event("L2_RQSTS.DEMAND_DATA_RD_MISS") + l2_dmnd_miss =3D DC_MISS + l2_dmnd_rd_all =3D DC_MISS + DC_HIT + except: + DC_ALL =3D Event("L2_RQSTS.ALL_DEMAND_DATA_RD") + l2_dmnd_miss =3D DC_ALL - DC_HIT + l2_dmnd_rd_all =3D DC_ALL + l2_dmnd_mrate =3D d_ratio(l2_dmnd_miss, interval_sec) + l2_dmnd_rrate =3D d_ratio(l2_dmnd_rd_all, interval_sec) + + DC_PFH =3D None + DC_PFM =3D None + l2_pf_all =3D None + l2_pf_mrate =3D None + l2_pf_rrate =3D None + try: + DC_PFH =3D Event("L2_RQSTS.PF_HIT") + DC_PFM =3D Event("L2_RQSTS.PF_MISS") + l2_pf_all =3D DC_PFH + DC_PFM + l2_pf_mrate =3D d_ratio(DC_PFM, interval_sec) + l2_pf_rrate =3D d_ratio(l2_pf_all, interval_sec) + except: + pass + + DC_RFOH =3D Event("L2_RQSTS.RFO_HIT") + DC_RFOM =3D Event("L2_RQSTS.RFO_MISS") + l2_rfo_all =3D DC_RFOH + DC_RFOM + l2_rfo_mrate =3D d_ratio(DC_RFOM, interval_sec) + l2_rfo_rrate =3D d_ratio(l2_rfo_all, interval_sec) + + DC_CH =3D Event("L2_RQSTS.CODE_RD_HIT") + DC_CM =3D Event("L2_RQSTS.CODE_RD_MISS") + DC_IN =3D Event("L2_LINES_IN.ALL") + DC_OUT_NS =3D None + DC_OUT_S =3D None + l2_lines_out =3D None + l2_out_rate =3D None + wbn =3D None + isd =3D None + try: + DC_OUT_NS =3D Event("L2_LINES_OUT.NON_SILENT", + "L2_LINES_OUT.DEMAND_DIRTY", + "L2_LINES_IN.S") + DC_OUT_S =3D Event("L2_LINES_OUT.SILENT", + "L2_LINES_OUT.DEMAND_CLEAN", + "L2_LINES_IN.I") + if DC_OUT_S.name =3D=3D "L2_LINES_OUT.SILENT" and ( + args.model.startswith("skylake") or + args.model =3D=3D "cascadelakex"): + DC_OUT_S.name =3D "L2_LINES_OUT.SILENT/any/" + # bring is back to per-CPU + l2_s =3D Select(DC_OUT_S / 2, Literal("#smt_on"), DC_OUT_S) + l2_ns =3D DC_OUT_NS + l2_lines_out =3D l2_s + l2_ns; + l2_out_rate =3D d_ratio(l2_lines_out, interval_sec); + nlr =3D max(l2_ns - DC_WB_U - DC_WB_D, 0) + wbn =3D d_ratio(nlr, interval_sec) + isd =3D d_ratio(l2_s, interval_sec) + except: + pass + DC_OUT_U =3D None + l2_pf_useless =3D None + l2_useless_rate =3D None + try: + DC_OUT_U =3D Event("L2_LINES_OUT.USELESS_HWPF") + l2_pf_useless =3D DC_OUT_U + l2_useless_rate =3D d_ratio(l2_pf_useless, interval_sec) + except: + pass + DC_WB_U =3D None + DC_WB_D =3D None + wbu =3D None + wbd =3D None + try: + DC_WB_U =3D Event("IDI_MISC.WB_UPGRADE") + DC_WB_D =3D Event("IDI_MISC.WB_DOWNGRADE") + wbu =3D d_ratio(DC_WB_U, interval_sec) + wbd =3D d_ratio(DC_WB_D, interval_sec) + except: + pass + + l2_lines_in =3D DC_IN + l2_code_all =3D DC_CH + DC_CM + l2_code_rate =3D d_ratio(l2_code_all, interval_sec) + l2_code_miss_rate =3D d_ratio(DC_CM, interval_sec) + l2_in_rate =3D d_ratio(l2_lines_in, interval_sec) + + return MetricGroup("l2", [ + MetricGroup("l2_totals", [ + Metric("l2_totals_in", "L2 cache total in per second", + l2_in_rate, "In/s"), + Metric("l2_totals_out", "L2 cache total out per second", + l2_out_rate, "Out/s") if l2_out_rate else None, + ]), + MetricGroup("l2_rd", [ + Metric("l2_rd_hits", "L2 cache data read hits", + d_ratio(DC_HIT, l2_dmnd_rd_all), "100%"), + Metric("l2_rd_hits", "L2 cache data read hits", + d_ratio(l2_dmnd_miss, l2_dmnd_rd_all), "100%"), + Metric("l2_rd_requests", "L2 cache data read requests per second", + l2_dmnd_rrate, "requests/s"), + Metric("l2_rd_misses", "L2 cache data read misses per second", + l2_dmnd_mrate, "misses/s"), + ]), + MetricGroup("l2_hwpf", [ + Metric("l2_hwpf_hits", "L2 cache hardware prefetcher hits", + d_ratio(DC_PFH, l2_pf_all), "100%"), + Metric("l2_hwpf_misses", "L2 cache hardware prefetcher misses", + d_ratio(DC_PFM, l2_pf_all), "100%"), + Metric("l2_hwpf_useless", "L2 cache hardware prefetcher useless pref= etches per second", + l2_useless_rate, "100%") if l2_useless_rate else None, + Metric("l2_hwpf_requests", "L2 cache hardware prefetcher requests pe= r second", + l2_pf_rrate, "100%"), + Metric("l2_hwpf_misses", "L2 cache hardware prefetcher misses per se= cond", + l2_pf_mrate, "100%"), + ]) if DC_PFH else None, + MetricGroup("l2_rfo", [ + Metric("l2_rfo_hits", "L2 cache request for ownership (RFO) hits", + d_ratio(DC_RFOH, l2_rfo_all), "100%"), + Metric("l2_rfo_misses", "L2 cache request for ownership (RFO) misses= ", + d_ratio(DC_RFOM, l2_rfo_all), "100%"), + Metric("l2_rfo_requests", "L2 cache request for ownership (RFO) requ= ests per second", + l2_rfo_rrate, "requests/s"), + Metric("l2_rfo_misses", "L2 cache request for ownership (RFO) misses= per second", + l2_rfo_mrate, "misses/s"), + ]), + MetricGroup("l2_code", [ + Metric("l2_code_hits", "L2 cache code hits", + d_ratio(DC_CH, l2_code_all), "100%"), + Metric("l2_code_misses", "L2 cache code misses", + d_ratio(DC_CM, l2_code_all), "100%"), + Metric("l2_code_requests", "L2 cache code requests per second", + l2_code_rate, "requests/s"), + Metric("l2_code_misses", "L2 cache code misses per second", + l2_code_miss_rate, "misses/s"), + ]), + MetricGroup("l2_evict", [ + MetricGroup("l2_evict_mef_lines", [ + Metric("l2_evict_mef_lines_l3_hot_lru", "L2 evictions M/E/F lines = L3 hot LRU per second", + wbu, "HotLRU/s") if wbu else None, + Metric("l2_evict_mef_lines_l3_norm_lru", "L2 evictions M/E/F lines= L3 normal LRU per second", + wbn, "NormLRU/s") if wbn else None, + Metric("l2_evict_mef_lines_dropped", "L2 evictions M/E/F lines dro= pped per second", + wbd, "dropped/s") if wbd else None, + Metric("l2_evict_is_lines_dropped", "L2 evictions I/S lines droppe= d per second", + isd, "dropped/s") if isd else None, + ]), + ]), + ], description =3D "L2 data cache analysis") + + def IntelPorts() -> Optional[MetricGroup]: pipeline_events =3D json.load(open(f"{_args.events_path}/x86/{_args.mode= l}/pipeline.json")) =20 @@ -380,6 +537,7 @@ def main() -> None: Smi(), Tsx(), IntelBr(), + IntelL2(), IntelPorts(), IntelSwpf(), ]) --=20 2.46.1.824.gd892dcdcdd-goog