From nobody Thu Nov 28 21:31:34 2024 Received: from mail-yw1-f202.google.com (mail-yw1-f202.google.com [209.85.128.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 842BC161311 for ; Thu, 26 Sep 2024 17:50:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727373048; cv=none; b=As1DXCYcqWT84GQNTpMP46UtlTYTLpguQSWGM0uHitN+snc9ReOdV1htl7aZJQYnq5G+tEP5B4qvl8I/YBALGDQ5WsbqTx28zJirBKan6IQPTSKIUGauYczMUARDFIiwBqQg7Eie9DsBBaoQa4zUs9Vvn8mHyHZK6F+q+fYp7JY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727373048; c=relaxed/simple; bh=yvWeBnYlH5KHJguhy5lABIEriYvuqSdXJ0LPNpZjZm0=; h=Date:In-Reply-To:Message-Id:Mime-Version:References:Subject:From: To:Content-Type; b=GBPG1vKcRCwrKHwXt1KN6iaWhvJM8avfU+1J1aBdfxf3xvsVU3aGQ8X1z1yj+QOhaN1KkVd8pMJ8BMHfavb5c243x4fLAOcjCa/dLLPNxWXQlsAO/gnMCMhmP4xL4pAYP4wmkHdDtWDa6m9//mKBePG6AwnjBERGWl/hpjh/Mpw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--irogers.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=hdVC9bpU; arc=none smtp.client-ip=209.85.128.202 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--irogers.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="hdVC9bpU" Received: by mail-yw1-f202.google.com with SMTP id 00721157ae682-6d7124938d1so26110267b3.0 for ; Thu, 26 Sep 2024 10:50:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1727373045; x=1727977845; darn=vger.kernel.org; h=to:from:subject:references:mime-version:message-id:in-reply-to:date :from:to:cc:subject:date:message-id:reply-to; bh=hibi5LL08muBMKadiUp2UP2j1gIebwFeSAhkpXeIPd0=; b=hdVC9bpUvPUfLaQrkEY7mkyhknRcSl53Z2bsYTsK3jODq2Z2RivArl0+EoRnwwcKPL AGO7qim+dTHY/AyJeK65e2xvkoCMJZOOlMOTVwMEncvGPJxylEVnK/CSaAxGY7qaUqTn ujn8FTsBduPBRvZx8Aq2/JLZIOFKRx5p2B+nhU/PK+uMQP3oZX4vYV/oNsFpZYthed0k csLZ53u5CEW6CE9/N6HpwVnpfud+s5gwCsInOm/wtQM9lAOnJfgUdoQ9VoeObXRywmLi RNpWIsfgEkxrTE5gHr5/N3zlMqVvUItQnOAvj4rrFAnPbBRzl9R5sXcsoNInTezHtpIN vNLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727373045; x=1727977845; h=to:from:subject:references:mime-version:message-id:in-reply-to:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=hibi5LL08muBMKadiUp2UP2j1gIebwFeSAhkpXeIPd0=; b=mhBiIojHJq9i56n0TY8kY+14IEqJv7T6XVHFc/P5kgAV6T1HB7mdS3hBybW7ptLo3l ybSvPxha62dC7dNywV0v5w/0ePjFTY5roxlV/N1TVgcx4bGtGHi3Q0Ajq7/CZ9wz+kmk sTHmTi7g/JLHsl8PUXPWMfYjw8GBV17uGspLhxAt24r+FShjTsCzIaya6G93VVCRS8VY WILyPX3fSApjdkXgTfcG+6ASPMY6EAHLmrXIFAzxEA3ChAsuaHeNQ80TnmH3jCUL6i5Q o3B49jyQOpPvesmqIeCwtgV3e/u746DEzWY2Li+pC/Vk3wFU0wg8AxGB8MZmR+c/A8Zu uyfg== X-Forwarded-Encrypted: i=1; AJvYcCXua4gFHM62Rvb7YcTwnXeCgA+jd+DbPK8OYSO7PBtrIGGl62L5mShImmEV6rMfKuWXYF5nE6tbP0rmgDk=@vger.kernel.org X-Gm-Message-State: AOJu0YzETDsHz5ymyZ1AGZq5AVZgv2/ip4hpYmnelizFaskm0gdF9URV zv47E3jTOgZ4lCYsPxvHo62ktzmjRNOamD7Zky2kiH6VeWGbura8+6oviWntO7rCLR+2W8EARA1 5X8PnVA== X-Google-Smtp-Source: AGHT+IGjtALdnf6ddGtFaEXP98ir997IggxkQYyuuX+1kTF4EPazuXun9mwMq1dzOgF5lYkIa0aTZ/WZxsII X-Received: from irogers.svl.corp.google.com ([2620:15c:2a3:200:8872:3585:18ed:a056]) (user=irogers job=sendgmr) by 2002:a25:904:0:b0:e11:6a73:b0d with SMTP id 3f1490d57ef6-e2604b7c3f5mr185276.6.1727373045453; Thu, 26 Sep 2024 10:50:45 -0700 (PDT) Date: Thu, 26 Sep 2024 10:50:14 -0700 In-Reply-To: <20240926175035.408668-1-irogers@google.com> Message-Id: <20240926175035.408668-2-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240926175035.408668-1-irogers@google.com> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog Subject: [PATCH v4 01/22] perf jevents: Add RAPL metrics for all Intel models From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a 'cpu_power' metric group that computes the power consumption from RAPL events if they are present. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/intel_metrics.py | 45 ++++++++++++++++++++++++-- 1 file changed, 42 insertions(+), 3 deletions(-) diff --git a/tools/perf/pmu-events/intel_metrics.py b/tools/perf/pmu-events= /intel_metrics.py index 04a19d05c6c1..58e23eb48312 100755 --- a/tools/perf/pmu-events/intel_metrics.py +++ b/tools/perf/pmu-events/intel_metrics.py @@ -1,13 +1,49 @@ #!/usr/bin/env python3 # SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause) -from metric import (JsonEncodeMetric, JsonEncodeMetricGroupDescriptions, L= oadEvents, - MetricGroup) +from metric import (d_ratio, has_event, Event, JsonEncodeMetric, JsonEncod= eMetricGroupDescriptions, + LoadEvents, Metric, MetricGroup, Select) import argparse import json +import math import os =20 # Global command line arguments. _args =3D None +interval_sec =3D Event("duration_time") + +def Rapl() -> MetricGroup: + """Processor power consumption estimate. + + Use events from the running average power limit (RAPL) driver. + """ + # Watts =3D joules/second + pkg =3D Event("power/energy\-pkg/") + cond_pkg =3D Select(pkg, has_event(pkg), math.nan) + cores =3D Event("power/energy\-cores/") + cond_cores =3D Select(cores, has_event(cores), math.nan) + ram =3D Event("power/energy\-ram/") + cond_ram =3D Select(ram, has_event(ram), math.nan) + gpu =3D Event("power/energy\-gpu/") + cond_gpu =3D Select(gpu, has_event(gpu), math.nan) + psys =3D Event("power/energy\-psys/") + cond_psys =3D Select(psys, has_event(psys), math.nan) + scale =3D 2.3283064365386962890625e-10 + metrics =3D [ + Metric("cpu_power_pkg", "", + d_ratio(cond_pkg * scale, interval_sec), "Watts"), + Metric("cpu_power_cores", "", + d_ratio(cond_cores * scale, interval_sec), "Watts"), + Metric("cpu_power_ram", "", + d_ratio(cond_ram * scale, interval_sec), "Watts"), + Metric("cpu_power_gpu", "", + d_ratio(cond_gpu * scale, interval_sec), "Watts"), + Metric("cpu_power_psys", "", + d_ratio(cond_psys * scale, interval_sec), "Watts"), + ] + + return MetricGroup("cpu_power", metrics, + description=3D"Running Average Power Limit (RAPL) pow= er consumption estimates") + =20 def main() -> None: global _args @@ -31,7 +67,10 @@ def main() -> None: directory =3D f"{_args.events_path}/x86/{_args.model}/" LoadEvents(directory) =20 - all_metrics =3D MetricGroup("",[]) + all_metrics =3D MetricGroup("", [ + Rapl(), + ]) + =20 if _args.metricgroups: print(JsonEncodeMetricGroupDescriptions(all_metrics)) --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 21:31:34 2024 Received: from mail-yb1-f202.google.com (mail-yb1-f202.google.com [209.85.219.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCA62165F19 for ; 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Thu, 26 Sep 2024 10:50:47 -0700 (PDT) Date: Thu, 26 Sep 2024 10:50:15 -0700 In-Reply-To: <20240926175035.408668-1-irogers@google.com> Message-Id: <20240926175035.408668-3-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240926175035.408668-1-irogers@google.com> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog Subject: [PATCH v4 02/22] perf jevents: Add idle metric for Intel models From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Compute using the msr PMU the percentage of wallclock cycles where the CPUs are in a low power state. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/intel_metrics.py | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/tools/perf/pmu-events/intel_metrics.py b/tools/perf/pmu-events= /intel_metrics.py index 58e23eb48312..f875eb844c78 100755 --- a/tools/perf/pmu-events/intel_metrics.py +++ b/tools/perf/pmu-events/intel_metrics.py @@ -1,7 +1,8 @@ #!/usr/bin/env python3 # SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause) -from metric import (d_ratio, has_event, Event, JsonEncodeMetric, JsonEncod= eMetricGroupDescriptions, - LoadEvents, Metric, MetricGroup, Select) +from metric import (d_ratio, has_event, max, Event, JsonEncodeMetric, + JsonEncodeMetricGroupDescriptions, LoadEvents, Metric, + MetricGroup, Select) import argparse import json import math @@ -11,6 +12,16 @@ import os _args =3D None interval_sec =3D Event("duration_time") =20 +def Idle() -> Metric: + cyc =3D Event("msr/mperf/") + tsc =3D Event("msr/tsc/") + low =3D max(tsc - cyc, 0) + return Metric( + "idle", + "Percentage of total wallclock cycles where CPUs are in low power st= ate (C1 or deeper sleep state)", + d_ratio(low, tsc), "100%") + + def Rapl() -> MetricGroup: """Processor power consumption estimate. =20 @@ -68,6 +79,7 @@ def main() -> None: LoadEvents(directory) =20 all_metrics =3D MetricGroup("", [ + Idle(), Rapl(), ]) =20 --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 21:31:34 2024 Received: from mail-yb1-f201.google.com (mail-yb1-f201.google.com [209.85.219.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1465316130C for ; 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Thu, 26 Sep 2024 10:50:50 -0700 (PDT) Date: Thu, 26 Sep 2024 10:50:16 -0700 In-Reply-To: <20240926175035.408668-1-irogers@google.com> Message-Id: <20240926175035.408668-4-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240926175035.408668-1-irogers@google.com> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog Subject: [PATCH v4 03/22] perf jevents: Add smi metric group for Intel models From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Allow duplicated metric to be dropped from json files. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/intel_metrics.py | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/tools/perf/pmu-events/intel_metrics.py b/tools/perf/pmu-events= /intel_metrics.py index f875eb844c78..f34b4230a4ee 100755 --- a/tools/perf/pmu-events/intel_metrics.py +++ b/tools/perf/pmu-events/intel_metrics.py @@ -2,7 +2,7 @@ # SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause) from metric import (d_ratio, has_event, max, Event, JsonEncodeMetric, JsonEncodeMetricGroupDescriptions, LoadEvents, Metric, - MetricGroup, Select) + MetricGroup, MetricRef, Select) import argparse import json import math @@ -56,6 +56,24 @@ def Rapl() -> MetricGroup: description=3D"Running Average Power Limit (RAPL) pow= er consumption estimates") =20 =20 +def Smi() -> MetricGroup: + aperf =3D Event('msr/aperf/') + cycles =3D Event('cycles') + smi_num =3D Event('msr/smi/') + smi_cycles =3D Select(Select((aperf - cycles) / aperf, smi_num > 0, 0), + has_event(aperf), + 0) + return MetricGroup('smi', [ + Metric('smi_num', 'Number of SMI interrupts.', + Select(smi_num, has_event(smi_num), 0), 'SMI#'), + # Note, the smi_cycles "Event" is really a reference to the metric. + Metric('smi_cycles', + 'Percentage of cycles spent in System Management Interrupts= . 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charset="utf-8" CheckPmu can be used to determine if hybrid events are present, allowing for hybrid conditional metrics/events/pmus to be premised on the json files rather than hard coded tables. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/metric.py | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/tools/perf/pmu-events/metric.py b/tools/perf/pmu-events/metric= .py index 03312cd6d491..e1847cccfdb0 100644 --- a/tools/perf/pmu-events/metric.py +++ b/tools/perf/pmu-events/metric.py @@ -8,10 +8,12 @@ import re from enum import Enum from typing import Dict, List, Optional, Set, Tuple, Union =20 +all_pmus =3D set() all_events =3D set() =20 def LoadEvents(directory: str) -> None: """Populate a global set of all known events for the purpose of validati= ng Event names""" + global all_pmus global all_events all_events =3D { "context\-switches", @@ -24,12 +26,18 @@ def LoadEvents(directory: str) -> None: filename =3D os.fsdecode(file) if filename.endswith(".json"): for x in json.load(open(f"{directory}/{filename}")): + if "Unit" in x: + all_pmus.add(x["Unit"]) if "EventName" in x: all_events.add(x["EventName"]) elif "ArchStdEvent" in x: all_events.add(x["ArchStdEvent"]) =20 =20 +def CheckPmu(name: str) -> bool: + return name in all_pmus + + def CheckEvent(name: str) -> bool: """Check the event name exists in the set of all loaded events""" global all_events --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 21:31:34 2024 Received: from mail-yw1-f202.google.com (mail-yw1-f202.google.com [209.85.128.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D770E17C9AB for ; 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Thu, 26 Sep 2024 10:50:54 -0700 (PDT) Date: Thu, 26 Sep 2024 10:50:18 -0700 In-Reply-To: <20240926175035.408668-1-irogers@google.com> Message-Id: <20240926175035.408668-6-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240926175035.408668-1-irogers@google.com> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog Subject: [PATCH v4 05/22] perf jevents: Mark metrics with experimental events as experimental From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When metrics are made with experimental events it is desirable the metric description also carries this information in case of metric inaccuracies. Suggested-by: Perry Taylor Signed-off-by: Ian Rogers --- tools/perf/pmu-events/metric.py | 44 +++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/tools/perf/pmu-events/metric.py b/tools/perf/pmu-events/metric= .py index e1847cccfdb0..5a5b149dd286 100644 --- a/tools/perf/pmu-events/metric.py +++ b/tools/perf/pmu-events/metric.py @@ -10,11 +10,13 @@ from typing import Dict, List, Optional, Set, Tuple, Un= ion =20 all_pmus =3D set() all_events =3D set() +experimental_events =3D set() =20 def LoadEvents(directory: str) -> None: """Populate a global set of all known events for the purpose of validati= ng Event names""" global all_pmus global all_events + global experimental_events all_events =3D { "context\-switches", "cycles", @@ -30,6 +32,8 @@ def LoadEvents(directory: str) -> None: all_pmus.add(x["Unit"]) if "EventName" in x: all_events.add(x["EventName"]) + if "Experimental" in x and x["Experimental"] =3D=3D "1": + experimental_events.add(x["EventName"]) elif "ArchStdEvent" in x: all_events.add(x["ArchStdEvent"]) =20 @@ -55,6 +59,18 @@ def CheckEvent(name: str) -> bool: return name in all_events =20 =20 +def IsExperimentalEvent(name: str) -> bool: + global experimental_events + if ':' in name: + # Remove trailing modifier. + name =3D name[:name.find(':')] + elif '/' in name: + # Name could begin with a PMU or an event, for now assume it is not ex= perimental. + return False + + return name in experimental_events + + class MetricConstraint(Enum): GROUPED_EVENTS =3D 0 NO_GROUP_EVENTS =3D 1 @@ -76,6 +92,10 @@ class Expression: """Returns a simplified version of self.""" raise NotImplementedError() =20 + def HasExperimentalEvents(self) -> bool: + """Are experimental events used in the expression?""" + raise NotImplementedError() + def Equals(self, other) -> bool: """Returns true when two expressions are the same.""" raise NotImplementedError() @@ -243,6 +263,9 @@ class Operator(Expression): =20 return Operator(self.operator, lhs, rhs) =20 + def HasExperimentalEvents(self) -> bool: + return self.lhs.HasExperimentalEvents() or self.rhs.HasExperimentalEve= nts() + def Equals(self, other: Expression) -> bool: if isinstance(other, Operator): return self.operator =3D=3D other.operator and self.lhs.Equals( @@ -291,6 +314,10 @@ class Select(Expression): =20 return Select(true_val, cond, false_val) =20 + def HasExperimentalEvents(self) -> bool: + return (self.cond.HasExperimentalEvents() or self.true_val.HasExperime= ntalEvents() or + self.false_val.HasExperimentalEvents()) + def Equals(self, other: Expression) -> bool: if isinstance(other, Select): return self.cond.Equals(other.cond) and self.false_val.Equals( @@ -339,6 +366,9 @@ class Function(Expression): =20 return Function(self.fn, lhs, rhs) =20 + def HasExperimentalEvents(self) -> bool: + return self.lhs.HasExperimentalEvents() or (self.rhs and self.rhs.HasE= xperimentalEvents()) + def Equals(self, other: Expression) -> bool: if isinstance(other, Function): result =3D self.fn =3D=3D other.fn and self.lhs.Equals(other.lhs) @@ -378,6 +408,9 @@ class Event(Expression): global all_events raise Exception(f"No event {error} in:\n{all_events}") =20 + def HasExperimentalEvents(self) -> bool: + return IsExperimentalEvent(self.name) + def ToPerfJson(self): result =3D re.sub('/', '@', self.name) return result @@ -410,6 +443,9 @@ class MetricRef(Expression): def Simplify(self) -> Expression: return self =20 + def HasExperimentalEvents(self) -> bool: + return False + def Equals(self, other: Expression) -> bool: return isinstance(other, MetricRef) and self.name =3D=3D other.name =20 @@ -437,6 +473,9 @@ class Constant(Expression): def Simplify(self) -> Expression: return self =20 + def HasExperimentalEvents(self) -> bool: + return False + def Equals(self, other: Expression) -> bool: return isinstance(other, Constant) and self.value =3D=3D other.value =20 @@ -459,6 +498,9 @@ class Literal(Expression): def Simplify(self) -> Expression: return self =20 + def HasExperimentalEvents(self) -> bool: + return False + def Equals(self, other: Expression) -> bool: return isinstance(other, Literal) and self.value =3D=3D other.value =20 @@ -521,6 +563,8 @@ class Metric: self.name =3D name self.description =3D description self.expr =3D expr.Simplify() + if self.expr.HasExperimentalEvents(): + self.description +=3D " (metric should be considered experimental as= it contains experimental events)." # Workraound valid_only_metric hiding certain metrics based on unit. scale_unit =3D scale_unit.replace('/sec', ' per sec') if scale_unit[0].isdigit(): --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 21:31:34 2024 Received: from mail-yw1-f202.google.com (mail-yw1-f202.google.com [209.85.128.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 392651779BC for ; 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Thu, 26 Sep 2024 10:50:57 -0700 (PDT) Date: Thu, 26 Sep 2024 10:50:19 -0700 In-Reply-To: <20240926175035.408668-1-irogers@google.com> Message-Id: <20240926175035.408668-7-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240926175035.408668-1-irogers@google.com> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog Subject: [PATCH v4 06/22] perf jevents: Add tsx metric group for Intel models From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Allow duplicated metric to be dropped from json files. Detect when TSX is supported by a model by using the json events, use sysfs events at runtime as hypervisors, etc. may disable TSX. Add CheckPmu to metric to determine if which PMUs have been associated with the loaded events. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/intel_metrics.py | 52 +++++++++++++++++++++++++- 1 file changed, 51 insertions(+), 1 deletion(-) diff --git a/tools/perf/pmu-events/intel_metrics.py b/tools/perf/pmu-events= /intel_metrics.py index f34b4230a4ee..58e243695f0a 100755 --- a/tools/perf/pmu-events/intel_metrics.py +++ b/tools/perf/pmu-events/intel_metrics.py @@ -1,12 +1,13 @@ #!/usr/bin/env python3 # SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause) -from metric import (d_ratio, has_event, max, Event, JsonEncodeMetric, +from metric import (d_ratio, has_event, max, CheckPmu, Event, JsonEncodeMe= tric, JsonEncodeMetricGroupDescriptions, LoadEvents, Metric, MetricGroup, MetricRef, Select) import argparse import json import math import os +from typing import Optional =20 # Global command line arguments. _args =3D None @@ -74,6 +75,54 @@ def Smi() -> MetricGroup: ], description =3D 'System Management Interrupt metrics') =20 =20 +def Tsx() -> Optional[MetricGroup]: + pmu =3D "cpu_core" if CheckPmu("cpu_core") else "cpu" + cycles =3D Event('cycles') + cycles_in_tx =3D Event(f'{pmu}/cycles\-t/') + cycles_in_tx_cp =3D Event(f'{pmu}/cycles\-ct/') + try: + # Test if the tsx event is present in the json, prefer the + # sysfs version so that we can detect its presence at runtime. + transaction_start =3D Event("RTM_RETIRED.START") + transaction_start =3D Event(f'{pmu}/tx\-start/') + except: + return None + + elision_start =3D None + try: + # Elision start isn't supported by all models, but we'll not + # generate the tsx_cycles_per_elision metric in that + # case. Again, prefer the sysfs encoding of the event. + elision_start =3D Event("HLE_RETIRED.START") + elision_start =3D Event(f'{pmu}/el\-start/') + except: + pass + + return MetricGroup('transaction', [ + Metric('tsx_transactional_cycles', + 'Percentage of cycles within a transaction region.', + Select(cycles_in_tx / cycles, has_event(cycles_in_tx), 0), + '100%'), + Metric('tsx_aborted_cycles', 'Percentage of cycles in aborted transa= ctions.', + Select(max(cycles_in_tx - cycles_in_tx_cp, 0) / cycles, + has_event(cycles_in_tx), + 0), + '100%'), + Metric('tsx_cycles_per_transaction', + 'Number of cycles within a transaction divided by the number = of transactions.', + Select(cycles_in_tx / transaction_start, + has_event(cycles_in_tx), + 0), + "cycles / transaction"), + Metric('tsx_cycles_per_elision', + 'Number of cycles within a transaction divided by the number = of elisions.', + Select(cycles_in_tx / elision_start, + has_event(elision_start), + 0), + "cycles / elision") if elision_start else None, + ], description=3D"Breakdown of transactional memory statistics") + + def main() -> None: global _args =20 @@ -100,6 +149,7 @@ def main() -> None: Idle(), Rapl(), Smi(), + Tsx(), ]) =20 =20 --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 21:31:34 2024 Received: from mail-yb1-f201.google.com (mail-yb1-f201.google.com [209.85.219.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A59F8183CBC for ; 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Thu, 26 Sep 2024 10:50:59 -0700 (PDT) Date: Thu, 26 Sep 2024 10:50:20 -0700 In-Reply-To: <20240926175035.408668-1-irogers@google.com> Message-Id: <20240926175035.408668-8-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240926175035.408668-1-irogers@google.com> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog Subject: [PATCH v4 07/22] perf jevents: Add br metric group for branch statistics on Intel From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The br metric group for branches itself comprises metric groups for total, taken, conditional, fused and far metric groups using json events. Conditional taken and not taken metrics are specific to Icelake and later generations, so the presence of the event is used to determine whether the metric should exist. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/intel_metrics.py | 138 +++++++++++++++++++++++++ 1 file changed, 138 insertions(+) diff --git a/tools/perf/pmu-events/intel_metrics.py b/tools/perf/pmu-events= /intel_metrics.py index 58e243695f0a..09f7b7159e7c 100755 --- a/tools/perf/pmu-events/intel_metrics.py +++ b/tools/perf/pmu-events/intel_metrics.py @@ -123,6 +123,143 @@ def Tsx() -> Optional[MetricGroup]: ], description=3D"Breakdown of transactional memory statistics") =20 =20 +def IntelBr(): + ins =3D Event("instructions") + + def Total() -> MetricGroup: + br_all =3D Event ("BR_INST_RETIRED.ALL_BRANCHES", "BR_INST_RETIRED.ANY= ") + br_m_all =3D Event("BR_MISP_RETIRED.ALL_BRANCHES", + "BR_INST_RETIRED.MISPRED", + "BR_MISP_EXEC.ANY") + br_clr =3D None + try: + br_clr =3D Event("BACLEARS.ANY", "BACLEARS.ALL") + except: + pass + + br_r =3D d_ratio(br_all, interval_sec) + ins_r =3D d_ratio(ins, br_all) + misp_r =3D d_ratio(br_m_all, br_all) + clr_r =3D d_ratio(br_clr, interval_sec) if br_clr else None + + return MetricGroup("br_total", [ + Metric("br_total_retired", + "The number of branch instructions retired per second.", br= _r, + "insn/s"), + Metric( + "br_total_mispred", + "The number of branch instructions retired, of any type, that = were " + "not correctly predicted as a percentage of all branch instruc= ions.", + misp_r, "100%"), + Metric("br_total_insn_between_branches", + "The number of instructions divided by the number of branch= es.", + ins_r, "insn"), + Metric("br_total_insn_fe_resteers", + "The number of resync branches per second.", clr_r, "req/s" + ) if clr_r else None + ]) + + def Taken() -> MetricGroup: + br_all =3D Event("BR_INST_RETIRED.ALL_BRANCHES", "BR_INST_RETIRED.ANY") + br_m_tk =3D None + try: + br_m_tk =3D Event("BR_MISP_RETIRED.NEAR_TAKEN", + "BR_MISP_RETIRED.TAKEN_JCC", + "BR_INST_RETIRED.MISPRED_TAKEN") + except: + pass + br_r =3D d_ratio(br_all, interval_sec) + ins_r =3D d_ratio(ins, br_all) + misp_r =3D d_ratio(br_m_tk, br_all) if br_m_tk else None + return MetricGroup("br_taken", [ + Metric("br_taken_retired", + "The number of taken branches that were retired per second.= ", + br_r, "insn/s"), + Metric( + "br_taken_mispred", + "The number of retired taken branch instructions that were " + "mispredicted as a percentage of all taken branches.", misp_r, + "100%") if misp_r else None, + Metric( + "br_taken_insn_between_branches", + "The number of instructions divided by the number of taken bra= nches.", + ins_r, "insn"), + ]) + + def Conditional() -> Optional[MetricGroup]: + try: + br_cond =3D Event("BR_INST_RETIRED.COND", + "BR_INST_RETIRED.CONDITIONAL", + "BR_INST_RETIRED.TAKEN_JCC") + br_m_cond =3D Event("BR_MISP_RETIRED.COND", + "BR_MISP_RETIRED.CONDITIONAL", + "BR_MISP_RETIRED.TAKEN_JCC") + except: + return None + + br_cond_nt =3D None + br_m_cond_nt =3D None + try: + br_cond_nt =3D Event("BR_INST_RETIRED.COND_NTAKEN") + br_m_cond_nt =3D Event("BR_MISP_RETIRED.COND_NTAKEN") + except: + pass + br_r =3D d_ratio(br_cond, interval_sec) + ins_r =3D d_ratio(ins, br_cond) + misp_r =3D d_ratio(br_m_cond, br_cond) + taken_metrics =3D [ + Metric("br_cond_retired", "Retired conditional branch instructions= .", + br_r, "insn/s"), + Metric("br_cond_insn_between_branches", + "The number of instructions divided by the number of condit= ional " + "branches.", ins_r, "insn"), + Metric("br_cond_mispred", + "Retired conditional branch instructions mispredicted as a " + "percentage of all conditional branches.", misp_r, "100%"), + ] + if not br_m_cond_nt: + return MetricGroup("br_cond", taken_metrics) + + br_r =3D d_ratio(br_cond_nt, interval_sec) + ins_r =3D d_ratio(ins, br_cond_nt) + misp_r =3D d_ratio(br_m_cond_nt, br_cond_nt) + + not_taken_metrics =3D [ + Metric("br_cond_retired", "Retired conditional not taken branch in= structions.", + br_r, "insn/s"), + Metric("br_cond_insn_between_branches", + "The number of instructions divided by the number of not ta= ken conditional " + "branches.", ins_r, "insn"), + Metric("br_cond_mispred", + "Retired not taken conditional branch instructions mispredi= cted as a " + "percentage of all not taken conditional branches.", misp_r= , "100%"), + ] + return MetricGroup("br_cond", [ + MetricGroup("br_cond_nt", not_taken_metrics), + MetricGroup("br_cond_tkn", taken_metrics), + ]) + + def Far() -> Optional[MetricGroup]: + try: + br_far =3D Event("BR_INST_RETIRED.FAR_BRANCH") + except: + return None + + br_r =3D d_ratio(br_far, interval_sec) + ins_r =3D d_ratio(ins, br_far) + return MetricGroup("br_far", [ + Metric("br_far_retired", "Retired far control transfers per second= .", + br_r, "insn/s"), + Metric( + "br_far_insn_between_branches", + "The number of instructions divided by the number of far branc= hes.", + ins_r, "insn"), + ]) + + return MetricGroup("br", [Total(), Taken(), Conditional(), Far()], + description=3D"breakdown of retired branch instructio= ns") + + def main() -> None: global _args =20 @@ -150,6 +287,7 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(PDT) Date: Thu, 26 Sep 2024 10:50:21 -0700 In-Reply-To: <20240926175035.408668-1-irogers@google.com> Message-Id: <20240926175035.408668-9-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240926175035.408668-1-irogers@google.com> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog Subject: [PATCH v4 08/22] perf jevents: Add software prefetch (swpf) metric group for Intel From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add metrics that breakdown software prefetch instruction use. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/intel_metrics.py | 65 ++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/tools/perf/pmu-events/intel_metrics.py b/tools/perf/pmu-events= /intel_metrics.py index 09f7b7159e7c..f4707e964f75 100755 --- a/tools/perf/pmu-events/intel_metrics.py +++ b/tools/perf/pmu-events/intel_metrics.py @@ -260,6 +260,70 @@ def IntelBr(): description=3D"breakdown of retired branch instructio= ns") =20 =20 +def IntelSwpf() -> Optional[MetricGroup]: + ins =3D Event("instructions") + try: + s_ld =3D Event("MEM_INST_RETIRED.ALL_LOADS", "MEM_UOPS_RETIRED.ALL_LOA= DS") + s_nta =3D Event("SW_PREFETCH_ACCESS.NTA") + s_t0 =3D Event("SW_PREFETCH_ACCESS.T0") + s_t1 =3D Event("SW_PREFETCH_ACCESS.T1_T2") + s_w =3D Event("SW_PREFETCH_ACCESS.PREFETCHW") + except: + return None + + all_sw =3D s_nta + s_t0 + s_t1 + s_w + swp_r =3D d_ratio(all_sw, interval_sec) + ins_r =3D d_ratio(ins, all_sw) + ld_r =3D d_ratio(s_ld, all_sw) + + return MetricGroup("swpf", [ + MetricGroup("swpf_totals", [ + Metric("swpf_totals_exec", "Software prefetch instructions per s= econd", + swp_r, "swpf/s"), + Metric("swpf_totals_insn_per_pf", + "Average number of instructions between software prefetch= es", + ins_r, "insn/swpf"), + Metric("swpf_totals_loads_per_pf", + "Average number of loads between software prefetches", + ld_r, "loads/swpf"), + ]), + MetricGroup("swpf_bkdwn", [ + MetricGroup("swpf_bkdwn_nta", [ + Metric("swpf_bkdwn_nta_per_swpf", + "Software prefetch NTA instructions as a percent of a= ll prefetch instructions", + d_ratio(s_nta, all_sw), "100%"), + Metric("swpf_bkdwn_nta_rate", + "Software prefetch NTA instructions per second", + d_ratio(s_nta, interval_sec), "insn/s"), + ]), + MetricGroup("swpf_bkdwn_t0", [ + Metric("swpf_bkdwn_t0_per_swpf", + "Software prefetch T0 instructions as a percent of al= l prefetch instructions", + d_ratio(s_t0, all_sw), "100%"), + Metric("swpf_bkdwn_t0_rate", + "Software prefetch T0 instructions per second", + d_ratio(s_t0, interval_sec), "insn/s"), + ]), + MetricGroup("swpf_bkdwn_t1_t2", [ + Metric("swpf_bkdwn_t1_t2_per_swpf", + "Software prefetch T1 or T2 instructions as a percent= of all prefetch instructions", + d_ratio(s_t1, all_sw), "100%"), + Metric("swpf_bkdwn_t1_t2_rate", + "Software prefetch T1 or T2 instructions per second", + d_ratio(s_t1, interval_sec), "insn/s"), + ]), + MetricGroup("swpf_bkdwn_w", [ + Metric("swpf_bkdwn_w_per_swpf", + "Software prefetch W instructions as a percent of all= prefetch instructions", + d_ratio(s_w, all_sw), "100%"), + Metric("swpf_bkdwn_w_rate", + "Software prefetch W instructions per second", + d_ratio(s_w, interval_sec), "insn/s"), + ]), + ]), + ], description=3D"Software prefetch instruction breakdown") + + def main() -> None: global _args =20 @@ -288,6 +352,7 @@ def main() -> None: Smi(), Tsx(), IntelBr(), + IntelSwpf(), ]) =20 =20 --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 21:31:34 2024 Received: from mail-yb1-f202.google.com (mail-yb1-f202.google.com [209.85.219.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 977BB18455A for ; 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Thu, 26 Sep 2024 10:51:04 -0700 (PDT) Date: Thu, 26 Sep 2024 10:50:22 -0700 In-Reply-To: <20240926175035.408668-1-irogers@google.com> Message-Id: <20240926175035.408668-10-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240926175035.408668-1-irogers@google.com> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog Subject: [PATCH v4 09/22] perf jevents: Add ports metric group giving utilization on Intel From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The ports metric group contains a metric for each port giving its utilization as a ratio of cycles. The metrics are created by looking for UOPS_DISPATCHED.PORT events. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/intel_metrics.py | 33 ++++++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/tools/perf/pmu-events/intel_metrics.py b/tools/perf/pmu-events= /intel_metrics.py index f4707e964f75..3ef4eb868580 100755 --- a/tools/perf/pmu-events/intel_metrics.py +++ b/tools/perf/pmu-events/intel_metrics.py @@ -1,12 +1,13 @@ #!/usr/bin/env python3 # SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause) from metric import (d_ratio, has_event, max, CheckPmu, Event, JsonEncodeMe= tric, - JsonEncodeMetricGroupDescriptions, LoadEvents, Metric, - MetricGroup, MetricRef, Select) + JsonEncodeMetricGroupDescriptions, Literal, LoadEvents, + Metric, MetricGroup, MetricRef, Select) import argparse import json import math import os +import re from typing import Optional =20 # Global command line arguments. @@ -260,6 +261,33 @@ def IntelBr(): description=3D"breakdown of retired branch instructio= ns") =20 =20 +def IntelPorts() -> Optional[MetricGroup]: + pipeline_events =3D json.load(open(f"{_args.events_path}/x86/{_args.mode= l}/pipeline.json")) + + core_cycles =3D Event("CPU_CLK_UNHALTED.THREAD_P_ANY", + "CPU_CLK_UNHALTED.DISTRIBUTED", + "cycles") + # Number of CPU cycles scaled for SMT. + smt_cycles =3D Select(core_cycles / 2, Literal("#smt_on"), core_cycles) + + metrics =3D [] + for x in pipeline_events: + if "EventName" in x and re.search("^UOPS_DISPATCHED.PORT", x["EventNam= e"]): + name =3D x["EventName"] + port =3D re.search(r"(PORT_[0-9].*)", name).group(0).lower() + if name.endswith("_CORE"): + cyc =3D core_cycles + else: + cyc =3D smt_cycles + metrics.append(Metric(port, f"{port} utilization (higher is better)", + d_ratio(Event(name), cyc), "100%")) + if len(metrics) =3D=3D 0: + return None + + return MetricGroup("ports", metrics, "functional unit (port) utilization= -- " + "fraction of cycles each port is utilized (higher is = better)") + + def IntelSwpf() -> Optional[MetricGroup]: ins =3D Event("instructions") try: @@ -352,6 +380,7 @@ def main() -> None: Smi(), Tsx(), IntelBr(), + IntelPorts(), IntelSwpf(), ]) =20 --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 21:31:34 2024 Received: from mail-yw1-f202.google.com (mail-yw1-f202.google.com [209.85.128.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B820185B4B for ; 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Thu, 26 Sep 2024 10:51:06 -0700 (PDT) Date: Thu, 26 Sep 2024 10:50:23 -0700 In-Reply-To: <20240926175035.408668-1-irogers@google.com> Message-Id: <20240926175035.408668-11-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240926175035.408668-1-irogers@google.com> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog Subject: [PATCH v4 10/22] perf jevents: Add L2 metrics for Intel From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Give a breakdown of various L2 counters as metrics, including totals, reads, hardware prefetcher, RFO, code and evictions. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/intel_metrics.py | 158 +++++++++++++++++++++++++ 1 file changed, 158 insertions(+) diff --git a/tools/perf/pmu-events/intel_metrics.py b/tools/perf/pmu-events= /intel_metrics.py index 3ef4eb868580..4ddc68006b10 100755 --- a/tools/perf/pmu-events/intel_metrics.py +++ b/tools/perf/pmu-events/intel_metrics.py @@ -261,6 +261,163 @@ def IntelBr(): description=3D"breakdown of retired branch instructio= ns") =20 =20 +def IntelL2() -> Optional[MetricGroup]: + try: + DC_HIT =3D Event("L2_RQSTS.DEMAND_DATA_RD_HIT") + except: + return None + try: + DC_MISS =3D Event("L2_RQSTS.DEMAND_DATA_RD_MISS") + l2_dmnd_miss =3D DC_MISS + l2_dmnd_rd_all =3D DC_MISS + DC_HIT + except: + DC_ALL =3D Event("L2_RQSTS.ALL_DEMAND_DATA_RD") + l2_dmnd_miss =3D DC_ALL - DC_HIT + l2_dmnd_rd_all =3D DC_ALL + l2_dmnd_mrate =3D d_ratio(l2_dmnd_miss, interval_sec) + l2_dmnd_rrate =3D d_ratio(l2_dmnd_rd_all, interval_sec) + + DC_PFH =3D None + DC_PFM =3D None + l2_pf_all =3D None + l2_pf_mrate =3D None + l2_pf_rrate =3D None + try: + DC_PFH =3D Event("L2_RQSTS.PF_HIT") + DC_PFM =3D Event("L2_RQSTS.PF_MISS") + l2_pf_all =3D DC_PFH + DC_PFM + l2_pf_mrate =3D d_ratio(DC_PFM, interval_sec) + l2_pf_rrate =3D d_ratio(l2_pf_all, interval_sec) + except: + pass + + DC_RFOH =3D Event("L2_RQSTS.RFO_HIT") + DC_RFOM =3D Event("L2_RQSTS.RFO_MISS") + l2_rfo_all =3D DC_RFOH + DC_RFOM + l2_rfo_mrate =3D d_ratio(DC_RFOM, interval_sec) + l2_rfo_rrate =3D d_ratio(l2_rfo_all, interval_sec) + + DC_CH =3D Event("L2_RQSTS.CODE_RD_HIT") + DC_CM =3D Event("L2_RQSTS.CODE_RD_MISS") + DC_IN =3D Event("L2_LINES_IN.ALL") + DC_OUT_NS =3D None + DC_OUT_S =3D None + l2_lines_out =3D None + l2_out_rate =3D None + wbn =3D None + isd =3D None + try: + DC_OUT_NS =3D Event("L2_LINES_OUT.NON_SILENT", + "L2_LINES_OUT.DEMAND_DIRTY", + "L2_LINES_IN.S") + DC_OUT_S =3D Event("L2_LINES_OUT.SILENT", + "L2_LINES_OUT.DEMAND_CLEAN", + "L2_LINES_IN.I") + if DC_OUT_S.name =3D=3D "L2_LINES_OUT.SILENT" and ( + args.model.startswith("skylake") or + args.model =3D=3D "cascadelakex"): + DC_OUT_S.name =3D "L2_LINES_OUT.SILENT/any/" + # bring is back to per-CPU + l2_s =3D Select(DC_OUT_S / 2, Literal("#smt_on"), DC_OUT_S) + l2_ns =3D DC_OUT_NS + l2_lines_out =3D l2_s + l2_ns; + l2_out_rate =3D d_ratio(l2_lines_out, interval_sec); + nlr =3D max(l2_ns - DC_WB_U - DC_WB_D, 0) + wbn =3D d_ratio(nlr, interval_sec) + isd =3D d_ratio(l2_s, interval_sec) + except: + pass + DC_OUT_U =3D None + l2_pf_useless =3D None + l2_useless_rate =3D None + try: + DC_OUT_U =3D Event("L2_LINES_OUT.USELESS_HWPF") + l2_pf_useless =3D DC_OUT_U + l2_useless_rate =3D d_ratio(l2_pf_useless, interval_sec) + except: + pass + DC_WB_U =3D None + DC_WB_D =3D None + wbu =3D None + wbd =3D None + try: + DC_WB_U =3D Event("IDI_MISC.WB_UPGRADE") + DC_WB_D =3D Event("IDI_MISC.WB_DOWNGRADE") + wbu =3D d_ratio(DC_WB_U, interval_sec) + wbd =3D d_ratio(DC_WB_D, interval_sec) + except: + pass + + l2_lines_in =3D DC_IN + l2_code_all =3D DC_CH + DC_CM + l2_code_rate =3D d_ratio(l2_code_all, interval_sec) + l2_code_miss_rate =3D d_ratio(DC_CM, interval_sec) + l2_in_rate =3D d_ratio(l2_lines_in, interval_sec) + + return MetricGroup("l2", [ + MetricGroup("l2_totals", [ + Metric("l2_totals_in", "L2 cache total in per second", + l2_in_rate, "In/s"), + Metric("l2_totals_out", "L2 cache total out per second", + l2_out_rate, "Out/s") if l2_out_rate else None, + ]), + MetricGroup("l2_rd", [ + Metric("l2_rd_hits", "L2 cache data read hits", + d_ratio(DC_HIT, l2_dmnd_rd_all), "100%"), + Metric("l2_rd_hits", "L2 cache data read hits", + d_ratio(l2_dmnd_miss, l2_dmnd_rd_all), "100%"), + Metric("l2_rd_requests", "L2 cache data read requests per second", + l2_dmnd_rrate, "requests/s"), + Metric("l2_rd_misses", "L2 cache data read misses per second", + l2_dmnd_mrate, "misses/s"), + ]), + MetricGroup("l2_hwpf", [ + Metric("l2_hwpf_hits", "L2 cache hardware prefetcher hits", + d_ratio(DC_PFH, l2_pf_all), "100%"), + Metric("l2_hwpf_misses", "L2 cache hardware prefetcher misses", + d_ratio(DC_PFM, l2_pf_all), "100%"), + Metric("l2_hwpf_useless", "L2 cache hardware prefetcher useless pref= etches per second", + l2_useless_rate, "100%") if l2_useless_rate else None, + Metric("l2_hwpf_requests", "L2 cache hardware prefetcher requests pe= r second", + l2_pf_rrate, "100%"), + Metric("l2_hwpf_misses", "L2 cache hardware prefetcher misses per se= cond", + l2_pf_mrate, "100%"), + ]) if DC_PFH else None, + MetricGroup("l2_rfo", [ + Metric("l2_rfo_hits", "L2 cache request for ownership (RFO) hits", + d_ratio(DC_RFOH, l2_rfo_all), "100%"), + Metric("l2_rfo_misses", "L2 cache request for ownership (RFO) misses= ", + d_ratio(DC_RFOM, l2_rfo_all), "100%"), + Metric("l2_rfo_requests", "L2 cache request for ownership (RFO) requ= ests per second", + l2_rfo_rrate, "requests/s"), + Metric("l2_rfo_misses", "L2 cache request for ownership (RFO) misses= per second", + l2_rfo_mrate, "misses/s"), + ]), + MetricGroup("l2_code", [ + Metric("l2_code_hits", "L2 cache code hits", + d_ratio(DC_CH, l2_code_all), "100%"), + Metric("l2_code_misses", "L2 cache code misses", + d_ratio(DC_CM, l2_code_all), "100%"), + Metric("l2_code_requests", "L2 cache code requests per second", + l2_code_rate, "requests/s"), + Metric("l2_code_misses", "L2 cache code misses per second", + l2_code_miss_rate, "misses/s"), + ]), + MetricGroup("l2_evict", [ + MetricGroup("l2_evict_mef_lines", [ + Metric("l2_evict_mef_lines_l3_hot_lru", "L2 evictions M/E/F lines = L3 hot LRU per second", + wbu, "HotLRU/s") if wbu else None, + Metric("l2_evict_mef_lines_l3_norm_lru", "L2 evictions M/E/F lines= L3 normal LRU per second", + wbn, "NormLRU/s") if wbn else None, + Metric("l2_evict_mef_lines_dropped", "L2 evictions M/E/F lines dro= pped per second", + wbd, "dropped/s") if wbd else None, + Metric("l2_evict_is_lines_dropped", "L2 evictions I/S lines droppe= d per second", + isd, "dropped/s") if isd else None, + ]), + ]), + ], description =3D "L2 data cache analysis") + + def IntelPorts() -> Optional[MetricGroup]: pipeline_events =3D json.load(open(f"{_args.events_path}/x86/{_args.mode= l}/pipeline.json")) =20 @@ -380,6 +537,7 @@ def main() -> None: Smi(), Tsx(), IntelBr(), + IntelL2(), IntelPorts(), IntelSwpf(), ]) --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 21:31:34 2024 Received: from mail-yw1-f202.google.com (mail-yw1-f202.google.com [209.85.128.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69B201862BD for ; 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Thu, 26 Sep 2024 10:51:09 -0700 (PDT) Date: Thu, 26 Sep 2024 10:50:24 -0700 In-Reply-To: <20240926175035.408668-1-irogers@google.com> Message-Id: <20240926175035.408668-12-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240926175035.408668-1-irogers@google.com> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog Subject: [PATCH v4 11/22] perf jevents: Add load store breakdown metrics ldst for Intel From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Give breakdown of number of instructions. Use the counter mask (cmask) to show the number of cycles taken to retire the instructions. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/intel_metrics.py | 86 +++++++++++++++++++++++++- 1 file changed, 85 insertions(+), 1 deletion(-) diff --git a/tools/perf/pmu-events/intel_metrics.py b/tools/perf/pmu-events= /intel_metrics.py index 4ddc68006b10..d528b97e8822 100755 --- a/tools/perf/pmu-events/intel_metrics.py +++ b/tools/perf/pmu-events/intel_metrics.py @@ -2,7 +2,7 @@ # SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause) from metric import (d_ratio, has_event, max, CheckPmu, Event, JsonEncodeMe= tric, JsonEncodeMetricGroupDescriptions, Literal, LoadEvents, - Metric, MetricGroup, MetricRef, Select) + Metric, MetricConstraint, MetricGroup, MetricRef, Sele= ct) import argparse import json import math @@ -509,6 +509,89 @@ def IntelSwpf() -> Optional[MetricGroup]: ], description=3D"Software prefetch instruction breakdown") =20 =20 +def IntelLdSt() -> Optional[MetricGroup]: + if _args.model in [ + "bonnell", + "nehalemep", + "nehalemex", + "westmereep-dp", + "westmereep-sp", + "westmereex", + ]: + return None + LDST_LD =3D Event("MEM_INST_RETIRED.ALL_LOADS", "MEM_UOPS_RETIRED.ALL_LO= ADS") + LDST_ST =3D Event("MEM_INST_RETIRED.ALL_STORES", "MEM_UOPS_RETIRED.ALL_S= TORES") + LDST_LDC1 =3D Event(f"{LDST_LD.name}/cmask=3D1/") + LDST_STC1 =3D Event(f"{LDST_ST.name}/cmask=3D1/") + LDST_LDC2 =3D Event(f"{LDST_LD.name}/cmask=3D2/") + LDST_STC2 =3D Event(f"{LDST_ST.name}/cmask=3D2/") + LDST_LDC3 =3D Event(f"{LDST_LD.name}/cmask=3D3/") + LDST_STC3 =3D Event(f"{LDST_ST.name}/cmask=3D3/") + ins =3D Event("instructions") + LDST_CYC =3D Event("CPU_CLK_UNHALTED.THREAD", + "CPU_CLK_UNHALTED.CORE_P", + "CPU_CLK_UNHALTED.THREAD_P") + LDST_PRE =3D None + try: + LDST_PRE =3D Event("LOAD_HIT_PREFETCH.SWPF", "LOAD_HIT_PRE.SW_PF") + except: + pass + LDST_AT =3D None + try: + LDST_AT =3D Event("MEM_INST_RETIRED.LOCK_LOADS") + except: + pass + cyc =3D LDST_CYC + + ld_rate =3D d_ratio(LDST_LD, interval_sec) + st_rate =3D d_ratio(LDST_ST, interval_sec) + pf_rate =3D d_ratio(LDST_PRE, interval_sec) if LDST_PRE else None + at_rate =3D d_ratio(LDST_AT, interval_sec) if LDST_AT else None + + ldst_ret_constraint =3D MetricConstraint.GROUPED_EVENTS + if LDST_LD.name =3D=3D "MEM_UOPS_RETIRED.ALL_LOADS": + ldst_ret_constraint =3D MetricConstraint.NO_GROUP_EVENTS_NMI + + return MetricGroup("ldst", [ + MetricGroup("ldst_total", [ + Metric("ldst_total_loads", "Load/store instructions total loads", + ld_rate, "loads"), + Metric("ldst_total_stores", "Load/store instructions total store= s", + st_rate, "stores"), + ]), + MetricGroup("ldst_prcnt", [ + Metric("ldst_prcnt_loads", "Percent of all instructions that are= loads", + d_ratio(LDST_LD, ins), "100%"), + Metric("ldst_prcnt_stores", "Percent of all instructions that ar= e stores", + d_ratio(LDST_ST, ins), "100%"), + ]), + MetricGroup("ldst_ret_lds", [ + Metric("ldst_ret_lds_1", "Retired loads in 1 cycle", + d_ratio(max(LDST_LDC1 - LDST_LDC2, 0), cyc), "100%", + constraint =3D ldst_ret_constraint), + Metric("ldst_ret_lds_2", "Retired loads in 2 cycles", + d_ratio(max(LDST_LDC2 - LDST_LDC3, 0), cyc), "100%", + constraint =3D ldst_ret_constraint), + Metric("ldst_ret_lds_3", "Retired loads in 3 or more cycles", + d_ratio(LDST_LDC3, cyc), "100%"), + ]), + MetricGroup("ldst_ret_sts", [ + Metric("ldst_ret_sts_1", "Retired stores in 1 cycle", + d_ratio(max(LDST_STC1 - LDST_STC2, 0), cyc), "100%", + constraint =3D ldst_ret_constraint), + Metric("ldst_ret_sts_2", "Retired stores in 2 cycles", + d_ratio(max(LDST_STC2 - LDST_STC3, 0), cyc), "100%", + constraint =3D ldst_ret_constraint), + Metric("ldst_ret_sts_3", "Retired stores in 3 more cycles", + d_ratio(LDST_STC3, cyc), "100%"), + ]), + Metric("ldst_ld_hit_swpf", "Load hit software prefetches per second", + pf_rate, "swpf/s") if pf_rate else None, + Metric("ldst_atomic_lds", "Atomic loads per second", + at_rate, "loads/s") if at_rate else None, + ], description =3D "Breakdown of load/store instructions") + + def main() -> None: global _args =20 @@ -538,6 +621,7 @@ def main() -> None: Tsx(), IntelBr(), IntelL2(), + IntelLdSt(), IntelPorts(), IntelSwpf(), ]) --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 21:31:34 2024 Received: from mail-yb1-f202.google.com (mail-yb1-f202.google.com [209.85.219.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B323518660B for ; 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Thu, 26 Sep 2024 10:51:11 -0700 (PDT) Date: Thu, 26 Sep 2024 10:50:25 -0700 In-Reply-To: <20240926175035.408668-1-irogers@google.com> Message-Id: <20240926175035.408668-13-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240926175035.408668-1-irogers@google.com> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog Subject: [PATCH v4 12/22] perf jevents: Add ILP metrics for Intel From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use the counter mask (cmask) to see how many cycles an instruction takes to retire. Present as a set of ILP metrics. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/intel_metrics.py | 33 ++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/tools/perf/pmu-events/intel_metrics.py b/tools/perf/pmu-events= /intel_metrics.py index d528b97e8822..1d886e416e7f 100755 --- a/tools/perf/pmu-events/intel_metrics.py +++ b/tools/perf/pmu-events/intel_metrics.py @@ -261,6 +261,38 @@ def IntelBr(): description=3D"breakdown of retired branch instructio= ns") =20 =20 +def IntelIlp() -> MetricGroup: + tsc =3D Event("msr/tsc/") + c0 =3D Event("msr/mperf/") + low =3D tsc - c0 + inst_ret =3D Event("INST_RETIRED.ANY_P") + inst_ret_c =3D [Event(f"{inst_ret.name}/cmask=3D{x}/") for x in range(1,= 6)] + core_cycles =3D Event("CPU_CLK_UNHALTED.THREAD_P_ANY", + "CPU_CLK_UNHALTED.DISTRIBUTED", + "cycles") + ilp =3D [d_ratio(max(inst_ret_c[x] - inst_ret_c[x + 1], 0), core_cycles)= for x in range(0, 4)] + ilp.append(d_ratio(inst_ret_c[4], core_cycles)) + ilp0 =3D 1 + for x in ilp: + ilp0 -=3D x + return MetricGroup("ilp", [ + Metric("ilp_idle", "Lower power cycles as a percentage of all cycles= ", + d_ratio(low, tsc), "100%"), + Metric("ilp_inst_ret_0", "Instructions retired in 0 cycles as a perc= entage of all cycles", + ilp0, "100%"), + Metric("ilp_inst_ret_1", "Instructions retired in 1 cycles as a perc= entage of all cycles", + ilp[0], "100%"), + Metric("ilp_inst_ret_2", "Instructions retired in 2 cycles as a perc= entage of all cycles", + ilp[1], "100%"), + Metric("ilp_inst_ret_3", "Instructions retired in 3 cycles as a perc= entage of all cycles", + ilp[2], "100%"), + Metric("ilp_inst_ret_4", "Instructions retired in 4 cycles as a perc= entage of all cycles", + ilp[3], "100%"), + Metric("ilp_inst_ret_5", "Instructions retired in 5 or more cycles a= s a percentage of all cycles", + ilp[4], "100%"), + ]) + + def IntelL2() -> Optional[MetricGroup]: try: DC_HIT =3D Event("L2_RQSTS.DEMAND_DATA_RD_HIT") @@ -620,6 +652,7 @@ def main() -> None: Smi(), Tsx(), IntelBr(), + IntelIlp(), IntelL2(), IntelLdSt(), IntelPorts(), --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 21:31:34 2024 Received: from mail-yb1-f202.google.com (mail-yb1-f202.google.com [209.85.219.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A8C9186E58 for ; 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Thu, 26 Sep 2024 10:51:14 -0700 (PDT) Date: Thu, 26 Sep 2024 10:50:26 -0700 In-Reply-To: <20240926175035.408668-1-irogers@google.com> Message-Id: <20240926175035.408668-14-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240926175035.408668-1-irogers@google.com> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog Subject: [PATCH v4 13/22] perf jevents: Add context switch metrics for Intel From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Metrics break down context switches for different kinds of instruction. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/intel_metrics.py | 55 ++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/tools/perf/pmu-events/intel_metrics.py b/tools/perf/pmu-events= /intel_metrics.py index 1d886e416e7f..7cd933a28cfd 100755 --- a/tools/perf/pmu-events/intel_metrics.py +++ b/tools/perf/pmu-events/intel_metrics.py @@ -261,6 +261,60 @@ def IntelBr(): description=3D"breakdown of retired branch instructio= ns") =20 =20 +def IntelCtxSw() -> MetricGroup: + cs =3D Event("context\-switches") + metrics =3D [ + Metric("cs_rate", "Context switches per second", d_ratio(cs, interva= l_sec), "ctxsw/s") + ] + + ev =3D Event("instructions") + metrics.append(Metric("cs_instr", "Instructions per context switch", + d_ratio(ev, cs), "instr/cs")) + + ev =3D Event("cycles") + metrics.append(Metric("cs_cycles", "Cycles per context switch", + d_ratio(ev, cs), "cycles/cs")) + + try: + ev =3D Event("MEM_INST_RETIRED.ALL_LOADS", "MEM_UOPS_RETIRED.ALL_LOADS= ") + metrics.append(Metric("cs_loads", "Loads per context switch", + d_ratio(ev, cs), "loads/cs")) + except: + pass + + try: + ev =3D Event("MEM_INST_RETIRED.ALL_STORES", "MEM_UOPS_RETIRED.ALL_STOR= ES") + metrics.append(Metric("cs_stores", "Stores per context switch", + d_ratio(ev, cs), "stores/cs")) + except: + pass + + try: + ev =3D Event("BR_INST_RETIRED.NEAR_TAKEN", "BR_INST_RETIRED.TAKEN_JCC") + metrics.append(Metric("cs_br_taken", "Branches taken per context switc= h", + d_ratio(ev, cs), "br_taken/cs")) + except: + pass + + try: + l2_misses =3D (Event("L2_RQSTS.DEMAND_DATA_RD_MISS") + + Event("L2_RQSTS.RFO_MISS") + + Event("L2_RQSTS.CODE_RD_MISS")) + try: + l2_misses +=3D Event("L2_RQSTS.HWPF_MISS", "L2_RQSTS.L2_PF_MISS", "L= 2_RQSTS.PF_MISS") + except: + pass + + metrics.append(Metric("cs_l2_misses", "L2 misses per context switch", + d_ratio(l2_misses, cs), "l2_misses/cs")) + except: + pass + + return MetricGroup("cs", metrics, + description =3D ("Number of context switches per seco= nd, instructions " + "retired & core cycles between context= switches")) + + def IntelIlp() -> MetricGroup: tsc =3D Event("msr/tsc/") c0 =3D Event("msr/mperf/") @@ -652,6 +706,7 @@ def main() -> None: Smi(), Tsx(), IntelBr(), + IntelCtxSw(), IntelIlp(), IntelL2(), IntelLdSt(), --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 21:31:34 2024 Received: from mail-yb1-f202.google.com (mail-yb1-f202.google.com [209.85.219.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 735E216F839 for ; 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Thu, 26 Sep 2024 10:51:16 -0700 (PDT) Date: Thu, 26 Sep 2024 10:50:27 -0700 In-Reply-To: <20240926175035.408668-1-irogers@google.com> Message-Id: <20240926175035.408668-15-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240926175035.408668-1-irogers@google.com> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog Subject: [PATCH v4 14/22] perf jevents: Add FPU metrics for Intel From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Metrics break down of floating point operations. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/intel_metrics.py | 90 ++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/tools/perf/pmu-events/intel_metrics.py b/tools/perf/pmu-events= /intel_metrics.py index 7cd933a28cfd..dc14fff7abc3 100755 --- a/tools/perf/pmu-events/intel_metrics.py +++ b/tools/perf/pmu-events/intel_metrics.py @@ -315,6 +315,95 @@ def IntelCtxSw() -> MetricGroup: "retired & core cycles between context= switches")) =20 =20 +def IntelFpu() -> Optional[MetricGroup]: + cyc =3D Event("cycles") + try: + s_64 =3D Event("FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "SIMD_INST_RETIRED.SCALAR_SINGLE") + except: + return None + d_64 =3D Event("FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "SIMD_INST_RETIRED.SCALAR_DOUBLE") + s_128 =3D Event("FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "SIMD_INST_RETIRED.PACKED_SINGLE") + + flop =3D s_64 + d_64 + 4 * s_128 + + d_128 =3D None + s_256 =3D None + d_256 =3D None + s_512 =3D None + d_512 =3D None + try: + d_128 =3D Event("FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE") + flop +=3D 2 * d_128 + s_256 =3D Event("FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE") + flop +=3D 8 * s_256 + d_256 =3D Event("FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE") + flop +=3D 4 * d_256 + s_512 =3D Event("FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE") + flop +=3D 16 * s_512 + d_512 =3D Event("FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE") + flop +=3D 8 * d_512 + except: + pass + + f_assist =3D Event("ASSISTS.FP", "FP_ASSIST.ANY", "FP_ASSIST.S") + if f_assist in [ + "ASSISTS.FP", + "FP_ASSIST.S", + ]: + f_assist +=3D "/cmask=3D1/" + + flop_r =3D d_ratio(flop, interval_sec) + flop_c =3D d_ratio(flop, cyc) + nmi_constraint =3D MetricConstraint.GROUPED_EVENTS + if f_assist.name =3D=3D "ASSISTS.FP": # Icelake+ + nmi_constraint =3D MetricConstraint.NO_GROUP_EVENTS_NMI + def FpuMetrics(group: str, fl: Optional[Event], mult: int, desc: str) ->= Optional[MetricGroup]: + if not fl: + return None + + f =3D fl * mult + fl_r =3D d_ratio(f, interval_sec) + r_s =3D d_ratio(fl, interval_sec) + return MetricGroup(group, [ + Metric(f"{group}_of_total", desc + " floating point operations per= second", + d_ratio(f, flop), "100%"), + Metric(f"{group}_flops", desc + " floating point operations per se= cond", + fl_r, "flops/s"), + Metric(f"{group}_ops", desc + " operations per second", + r_s, "ops/s"), + ]) + + return MetricGroup("fpu", [ + MetricGroup("fpu_total", [ + Metric("fpu_total_flops", "Floating point operations per second", + flop_r, "flops/s"), + Metric("fpu_total_flopc", "Floating point operations per cycle", + flop_c, "flops/cycle", constraint=3Dnmi_constraint), + ]), + MetricGroup("fpu_64", [ + FpuMetrics("fpu_64_single", s_64, 1, "64-bit single"), + FpuMetrics("fpu_64_double", d_64, 1, "64-bit double"), + ]), + MetricGroup("fpu_128", [ + FpuMetrics("fpu_128_single", s_128, 4, "128-bit packed single"), + FpuMetrics("fpu_128_double", d_128, 2, "128-bit packed double"), + ]), + MetricGroup("fpu_256", [ + FpuMetrics("fpu_256_single", s_256, 8, "128-bit packed single"), + FpuMetrics("fpu_256_double", d_256, 4, "128-bit packed double"), + ]), + MetricGroup("fpu_512", [ + FpuMetrics("fpu_512_single", s_512, 16, "128-bit packed single"), + FpuMetrics("fpu_512_double", d_512, 8, "128-bit packed double"), + ]), + Metric("fpu_assists", "FP assists as a percentage of cycles", + d_ratio(f_assist, cyc), "100%"), + ]) + + def IntelIlp() -> MetricGroup: tsc =3D Event("msr/tsc/") c0 =3D Event("msr/mperf/") @@ -707,6 +796,7 @@ def main() -> None: Tsx(), IntelBr(), IntelCtxSw(), + IntelFpu(), IntelIlp(), IntelL2(), IntelLdSt(), --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 21:31:34 2024 Received: from mail-yb1-f201.google.com (mail-yb1-f201.google.com [209.85.219.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0FE3C187852 for ; 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Thu, 26 Sep 2024 10:51:19 -0700 (PDT) Date: Thu, 26 Sep 2024 10:50:28 -0700 In-Reply-To: <20240926175035.408668-1-irogers@google.com> Message-Id: <20240926175035.408668-16-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240926175035.408668-1-irogers@google.com> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog Subject: [PATCH v4 15/22] perf jevents: Add Miss Level Parallelism (MLP) metric for Intel From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Number of outstanding load misses per cycle. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/intel_metrics.py | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/tools/perf/pmu-events/intel_metrics.py b/tools/perf/pmu-events= /intel_metrics.py index dc14fff7abc3..8c6be9e1883f 100755 --- a/tools/perf/pmu-events/intel_metrics.py +++ b/tools/perf/pmu-events/intel_metrics.py @@ -593,6 +593,20 @@ def IntelL2() -> Optional[MetricGroup]: ], description =3D "L2 data cache analysis") =20 =20 +def IntelMlp() -> Optional[Metric]: + try: + l1d =3D Event("L1D_PEND_MISS.PENDING") + l1dc =3D Event("L1D_PEND_MISS.PENDING_CYCLES") + except: + return None + + l1dc =3D Select(l1dc / 2, Literal("#smt_on"), l1dc) + ml =3D d_ratio(l1d, l1dc) + return Metric("mlp", + "Miss level parallelism - number of outstanding load misse= s per cycle (higher is better)", + ml, "load_miss_pending/cycle") + + def IntelPorts() -> Optional[MetricGroup]: pipeline_events =3D json.load(open(f"{_args.events_path}/x86/{_args.mode= l}/pipeline.json")) =20 @@ -800,6 +814,7 @@ def main() -> None: IntelIlp(), IntelL2(), IntelLdSt(), + IntelMlp(), IntelPorts(), IntelSwpf(), ]) --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 21:31:34 2024 Received: from mail-yw1-f201.google.com (mail-yw1-f201.google.com [209.85.128.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A92018787C for ; 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Thu, 26 Sep 2024 10:51:21 -0700 (PDT) Date: Thu, 26 Sep 2024 10:50:29 -0700 In-Reply-To: <20240926175035.408668-1-irogers@google.com> Message-Id: <20240926175035.408668-17-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240926175035.408668-1-irogers@google.com> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog Subject: [PATCH v4 16/22] perf jevents: Add mem_bw metric for Intel From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Break down memory bandwidth using uncore counters. For many models this matches the memory_bandwidth_* metrics, but these metrics aren't made available on all models. Add support for free running counters. Query the event json when determining which what events/counters are available. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/intel_metrics.py | 62 ++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/tools/perf/pmu-events/intel_metrics.py b/tools/perf/pmu-events= /intel_metrics.py index 8c6be9e1883f..05e803286f29 100755 --- a/tools/perf/pmu-events/intel_metrics.py +++ b/tools/perf/pmu-events/intel_metrics.py @@ -781,6 +781,67 @@ def IntelLdSt() -> Optional[MetricGroup]: ], description =3D "Breakdown of load/store instructions") =20 =20 +def UncoreMemBw() -> Optional[MetricGroup]: + mem_events =3D [] + try: + mem_events =3D json.load(open(f"{os.path.dirname(os.path.realpath(__fi= le__))}" + f"/arch/x86/{args.model}/uncore-memory.jso= n")) + except: + pass + + ddr_rds =3D 0 + ddr_wrs =3D 0 + ddr_total =3D 0 + for x in mem_events: + if "EventName" in x: + name =3D x["EventName"] + if re.search("^UNC_MC[0-9]+_RDCAS_COUNT_FREERUN", name): + ddr_rds +=3D Event(name) + elif re.search("^UNC_MC[0-9]+_WRCAS_COUNT_FREERUN", name): + ddr_wrs +=3D Event(name) + #elif re.search("^UNC_MC[0-9]+_TOTAL_REQCOUNT_FREERUN", name): + # ddr_total +=3D Event(name) + + if ddr_rds =3D=3D 0: + try: + ddr_rds =3D Event("UNC_M_CAS_COUNT.RD") + ddr_wrs =3D Event("UNC_M_CAS_COUNT.WR") + except: + return None + + ddr_total =3D ddr_rds + ddr_wrs + + pmm_rds =3D 0 + pmm_wrs =3D 0 + try: + pmm_rds =3D Event("UNC_M_PMM_RPQ_INSERTS") + pmm_wrs =3D Event("UNC_M_PMM_WPQ_INSERTS") + except: + pass + + pmm_total =3D pmm_rds + pmm_wrs + + scale =3D 64 / 1_000_000 + return MetricGroup("mem_bw", [ + MetricGroup("mem_bw_ddr", [ + Metric("mem_bw_ddr_read", "DDR memory read bandwidth", + d_ratio(ddr_rds, interval_sec), f"{scale}MB/s"), + Metric("mem_bw_ddr_write", "DDR memory write bandwidth", + d_ratio(ddr_wrs, interval_sec), f"{scale}MB/s"), + Metric("mem_bw_ddr_total", "DDR memory write bandwidth", + d_ratio(ddr_total, interval_sec), f"{scale}MB/s"), + ], description =3D "DDR Memory Bandwidth"), + MetricGroup("mem_bw_pmm", [ + Metric("mem_bw_pmm_read", "PMM memory read bandwidth", + d_ratio(pmm_rds, interval_sec), f"{scale}MB/s"), + Metric("mem_bw_pmm_write", "PMM memory write bandwidth", + d_ratio(pmm_wrs, interval_sec), f"{scale}MB/s"), + Metric("mem_bw_pmm_total", "PMM memory write bandwidth", + d_ratio(pmm_total, interval_sec), f"{scale}MB/s"), + ], description =3D "PMM Memory Bandwidth") if pmm_rds !=3D 0 else No= ne, + ], description =3D "Memory Bandwidth") + + def main() -> None: global _args =20 @@ -817,6 +878,7 @@ def main() -> None: IntelMlp(), IntelPorts(), IntelSwpf(), + UncoreMemBw(), ]) =20 =20 --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 21:31:34 2024 Received: from mail-yw1-f201.google.com (mail-yw1-f201.google.com [209.85.128.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 008AC16131A for ; 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Thu, 26 Sep 2024 10:51:23 -0700 (PDT) Date: Thu, 26 Sep 2024 10:50:30 -0700 In-Reply-To: <20240926175035.408668-1-irogers@google.com> Message-Id: <20240926175035.408668-18-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240926175035.408668-1-irogers@google.com> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog Subject: [PATCH v4 17/22] perf jevents: Add local/remote "mem" breakdown metrics for Intel From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Breakdown local and remote memory bandwidth, read and writes. The implementation uses the HA and CHA PMUs present in server models broadwellde, broadwellx cascadelakex, emeraldrapids, haswellx, icelakex, ivytown, sapphirerapids and skylakex. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/intel_metrics.py | 27 ++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/tools/perf/pmu-events/intel_metrics.py b/tools/perf/pmu-events= /intel_metrics.py index 05e803286f29..62d504036ba0 100755 --- a/tools/perf/pmu-events/intel_metrics.py +++ b/tools/perf/pmu-events/intel_metrics.py @@ -781,6 +781,32 @@ def IntelLdSt() -> Optional[MetricGroup]: ], description =3D "Breakdown of load/store instructions") =20 =20 +def UncoreMem() -> Optional[MetricGroup]: + try: + loc_rds =3D Event("UNC_CHA_REQUESTS.READS_LOCAL", "UNC_H_REQUESTS.READ= S_LOCAL") + rem_rds =3D Event("UNC_CHA_REQUESTS.READS_REMOTE", "UNC_H_REQUESTS.REA= DS_REMOTE") + loc_wrs =3D Event("UNC_CHA_REQUESTS.WRITES_LOCAL", "UNC_H_REQUESTS.WRI= TES_LOCAL") + rem_wrs =3D Event("UNC_CHA_REQUESTS.WRITES_REMOTE", "UNC_H_REQUESTS.WR= ITES_REMOTE") + except: + return None + + scale =3D 64 / 1_000_000 + return MetricGroup("mem", [ + MetricGroup("mem_local", [ + Metric("mem_local_read", "Local memory read bandwidth not includ= ing directory updates", + d_ratio(loc_rds, interval_sec), f"{scale}MB/s"), + Metric("mem_local_write", "Local memory write bandwidth not incl= uding directory updates", + d_ratio(loc_wrs, interval_sec), f"{scale}MB/s"), + ]), + MetricGroup("mem_remote", [ + Metric("mem_remote_read", "Remote memory read bandwidth not incl= uding directory updates", + d_ratio(rem_rds, interval_sec), f"{scale}MB/s"), + Metric("mem_remote_write", "Remote memory write bandwidth not in= cluding directory updates", + d_ratio(rem_wrs, interval_sec), f"{scale}MB/s"), + ]), + ], description =3D "Memory Bandwidth breakdown local vs. remote (remote = requests in). directory updates not included") + + def UncoreMemBw() -> Optional[MetricGroup]: mem_events =3D [] try: @@ -878,6 +904,7 @@ def main() -> None: IntelMlp(), IntelPorts(), IntelSwpf(), + UncoreMem(), UncoreMemBw(), ]) =20 --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 21:31:34 2024 Received: from mail-yb1-f201.google.com (mail-yb1-f201.google.com [209.85.219.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7EB2018859A for ; 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Thu, 26 Sep 2024 10:51:26 -0700 (PDT) Date: Thu, 26 Sep 2024 10:50:31 -0700 In-Reply-To: <20240926175035.408668-1-irogers@google.com> Message-Id: <20240926175035.408668-19-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240926175035.408668-1-irogers@google.com> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog Subject: [PATCH v4 18/22] perf jevents: Add dir breakdown metrics for Intel From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Breakdown directory hit, misses and requests. The implementation uses the M2M and CHA PMUs present in server models broadwellde, broadwellx cascadelakex, emeraldrapids, icelakex, sapphirerapids and skylakex. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/intel_metrics.py | 36 ++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/tools/perf/pmu-events/intel_metrics.py b/tools/perf/pmu-events= /intel_metrics.py index 62d504036ba0..77ac048c5451 100755 --- a/tools/perf/pmu-events/intel_metrics.py +++ b/tools/perf/pmu-events/intel_metrics.py @@ -781,6 +781,41 @@ def IntelLdSt() -> Optional[MetricGroup]: ], description =3D "Breakdown of load/store instructions") =20 =20 +def UncoreDir() -> Optional[MetricGroup]: + try: + m2m_upd =3D Event("UNC_M2M_DIRECTORY_UPDATE.ANY") + m2m_hits =3D Event("UNC_M2M_DIRECTORY_HIT.DIRTY_I") + # Turn the umask into a ANY rather than DIRTY_I filter. + m2m_hits.name +=3D "/umask=3D0xFF,name=3DUNC_M2M_DIRECTORY_HIT.ANY/" + m2m_miss =3D Event("UNC_M2M_DIRECTORY_MISS.DIRTY_I") + # Turn the umask into a ANY rather than DIRTY_I filter. + m2m_miss.name +=3D "/umask=3D0xFF,name=3DUNC_M2M_DIRECTORY_MISS.ANY/" + cha_upd =3D Event("UNC_CHA_DIR_UPDATE.HA") + # Turn the umask into a ANY rather than HA filter. + cha_upd.name +=3D "/umask=3D3,name=3DUNC_CHA_DIR_UPDATE.ANY/" + except: + return None + + m2m_total =3D m2m_hits + m2m_miss + upd =3D m2m_upd + cha_upd # in cache lines + upd_r =3D upd / interval_sec + look_r =3D m2m_total / interval_sec + + scale =3D 64 / 1_000_000 # Cache lines to MB + return MetricGroup("dir", [ + Metric("dir_lookup_rate", "", + d_ratio(m2m_total, interval_sec), "requests/s"), + Metric("dir_lookup_hits", "", + d_ratio(m2m_hits, m2m_total), "100%"), + Metric("dir_lookup_misses", "", + d_ratio(m2m_miss, m2m_total), "100%"), + Metric("dir_update_requests", "", + d_ratio(m2m_upd + cha_upd, interval_sec), "requests/s"), + Metric("dir_update_bw", "", + d_ratio(m2m_upd + cha_upd, interval_sec), f"{scale}MB/s"), + ]) + + def UncoreMem() -> Optional[MetricGroup]: try: loc_rds =3D Event("UNC_CHA_REQUESTS.READS_LOCAL", "UNC_H_REQUESTS.READ= S_LOCAL") @@ -904,6 +939,7 @@ def main() -> None: IntelMlp(), IntelPorts(), IntelSwpf(), + UncoreDir(), UncoreMem(), UncoreMemBw(), ]) --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 21:31:34 2024 Received: from mail-yw1-f201.google.com (mail-yw1-f201.google.com [209.85.128.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 003FA1885B8 for ; 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Thu, 26 Sep 2024 10:51:29 -0700 (PDT) Date: Thu, 26 Sep 2024 10:50:32 -0700 In-Reply-To: <20240926175035.408668-1-irogers@google.com> Message-Id: <20240926175035.408668-20-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240926175035.408668-1-irogers@google.com> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog Subject: [PATCH v4 19/22] perf jevents: Add C-State metrics from the PCU PMU for Intel From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use occupancy events fixed in: https://lore.kernel.org/lkml/20240226201517.3540187-1-irogers@google.com/ Metrics are at the socket level referring to cores, not hyperthreads. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/intel_metrics.py | 27 ++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/tools/perf/pmu-events/intel_metrics.py b/tools/perf/pmu-events= /intel_metrics.py index 77ac048c5451..5668128273b3 100755 --- a/tools/perf/pmu-events/intel_metrics.py +++ b/tools/perf/pmu-events/intel_metrics.py @@ -781,6 +781,32 @@ def IntelLdSt() -> Optional[MetricGroup]: ], description =3D "Breakdown of load/store instructions") =20 =20 +def UncoreCState() -> Optional[MetricGroup]: + try: + pcu_ticks =3D Event("UNC_P_CLOCKTICKS") + c0 =3D Event("UNC_P_POWER_STATE_OCCUPANCY.CORES_C0") + c3 =3D Event("UNC_P_POWER_STATE_OCCUPANCY.CORES_C3") + c6 =3D Event("UNC_P_POWER_STATE_OCCUPANCY.CORES_C6") + except: + return None + + num_cores =3D Literal("#num_cores") / Literal("#num_packages") + + max_cycles =3D pcu_ticks * num_cores; + total_cycles =3D c0 + c3 + c6 + + # remove fused-off cores which show up in C6/C7. + c6 =3D Select(max(c6 - (total_cycles - max_cycles), 0), + total_cycles > max_cycles, + c6) + + return MetricGroup("cstate", [ + Metric("cstate_c0", "C-State cores in C0/C1", d_ratio(c0, pcu_ticks)= , "cores"), + Metric("cstate_c3", "C-State cores in C3", d_ratio(c3, pcu_ticks), "= cores"), + Metric("cstate_c6", "C-State cores in C6/C7", d_ratio(c6, pcu_ticks)= , "cores"), + ]) + + def UncoreDir() -> Optional[MetricGroup]: try: m2m_upd =3D Event("UNC_M2M_DIRECTORY_UPDATE.ANY") @@ -939,6 +965,7 @@ def main() -> None: IntelMlp(), IntelPorts(), IntelSwpf(), + UncoreCState(), UncoreDir(), UncoreMem(), UncoreMemBw(), --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 21:31:34 2024 Received: from mail-yb1-f202.google.com (mail-yb1-f202.google.com [209.85.219.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3883618871D for ; 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Thu, 26 Sep 2024 10:51:31 -0700 (PDT) Date: Thu, 26 Sep 2024 10:50:33 -0700 In-Reply-To: <20240926175035.408668-1-irogers@google.com> Message-Id: <20240926175035.408668-21-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240926175035.408668-1-irogers@google.com> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog Subject: [PATCH v4 20/22] perf jevents: Add local/remote miss latency metrics for Intel From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Derive from CBOX/CHA occupancy and inserts the average latency as is provided in Intel's uncore performance monitoring reference. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/intel_metrics.py | 68 ++++++++++++++++++++++++-- 1 file changed, 65 insertions(+), 3 deletions(-) diff --git a/tools/perf/pmu-events/intel_metrics.py b/tools/perf/pmu-events= /intel_metrics.py index 5668128273b3..ec15653e2cb6 100755 --- a/tools/perf/pmu-events/intel_metrics.py +++ b/tools/perf/pmu-events/intel_metrics.py @@ -1,8 +1,9 @@ #!/usr/bin/env python3 # SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause) -from metric import (d_ratio, has_event, max, CheckPmu, Event, JsonEncodeMe= tric, - JsonEncodeMetricGroupDescriptions, Literal, LoadEvents, - Metric, MetricConstraint, MetricGroup, MetricRef, Sele= ct) +from metric import (d_ratio, has_event, max, source_count, CheckPmu, Event, + JsonEncodeMetric, JsonEncodeMetricGroupDescriptions, + Literal, LoadEvents, Metric, MetricConstraint, MetricG= roup, + MetricRef, Select) import argparse import json import math @@ -593,6 +594,66 @@ def IntelL2() -> Optional[MetricGroup]: ], description =3D "L2 data cache analysis") =20 =20 +def IntelMissLat() -> Optional[MetricGroup]: + try: + ticks =3D Event("UNC_CHA_CLOCKTICKS", "UNC_C_CLOCKTICKS") + data_rd_loc_occ =3D Event("UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL", + "UNC_CHA_TOR_OCCUPANCY.IA_MISS", + "UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE", + "UNC_C_TOR_OCCUPANCY.MISS_OPCODE") + data_rd_loc_ins =3D Event("UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL", + "UNC_CHA_TOR_INSERTS.IA_MISS", + "UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE", + "UNC_C_TOR_INSERTS.MISS_OPCODE") + data_rd_rem_occ =3D Event("UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE", + "UNC_CHA_TOR_OCCUPANCY.IA_MISS", + "UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE", + "UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE") + data_rd_rem_ins =3D Event("UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE", + "UNC_CHA_TOR_INSERTS.IA_MISS", + "UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE", + "UNC_C_TOR_INSERTS.NID_MISS_OPCODE") + except: + return None + + if (data_rd_loc_occ.name =3D=3D "UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE" = or + data_rd_loc_occ.name =3D=3D "UNC_C_TOR_OCCUPANCY.MISS_OPCODE"): + data_rd =3D 0x182 + for e in [data_rd_loc_occ, data_rd_loc_ins, data_rd_rem_occ, data_rd_r= em_ins]: + e.name +=3D f"/filter_opc=3D{hex(data_rd)}/" + elif data_rd_loc_occ.name =3D=3D "UNC_CHA_TOR_OCCUPANCY.IA_MISS": + # Demand Data Read - Full cache-line read requests from core for + # lines to be cached in S or E, typically for data + demand_data_rd =3D 0x202 + # LLC Prefetch Data - Uncore will first look up the line in the + # LLC; for a cache hit, the LRU will be updated, on a miss, the + # DRd will be initiated + llc_prefetch_data =3D 0x25a + local_filter =3D (f"/filter_opc0=3D{hex(demand_data_rd)}," + f"filter_opc1=3D{hex(llc_prefetch_data)}," + "filter_loc,filter_nm,filter_not_nm/") + remote_filter =3D (f"/filter_opc0=3D{hex(demand_data_rd)}," + f"filter_opc1=3D{hex(llc_prefetch_data)}," + "filter_rem,filter_nm,filter_not_nm/") + for e in [data_rd_loc_occ, data_rd_loc_ins]: + e.name +=3D local_filter + for e in [data_rd_rem_occ, data_rd_rem_ins]: + e.name +=3D remote_filter + else: + assert data_rd_loc_occ.name =3D=3D "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_= LOCAL", data_rd_loc_occ + + ticks_per_cha =3D ticks / source_count(data_rd_loc_ins) + loc_lat =3D interval_sec * 1e9 * data_rd_loc_occ / (ticks_per_cha * data= _rd_loc_ins) + ticks_per_cha =3D ticks / source_count(data_rd_rem_ins) + rem_lat =3D interval_sec * 1e9 * data_rd_rem_occ / (ticks_per_cha * data= _rd_rem_ins) + return MetricGroup("miss_lat", [ + Metric("miss_lat_loc", "Local to a socket miss latency in nanosecond= s", + loc_lat, "ns"), + Metric("miss_lat_rem", "Remote to a socket miss latency in nanosecon= ds", + rem_lat, "ns"), + ]) + + def IntelMlp() -> Optional[Metric]: try: l1d =3D Event("L1D_PEND_MISS.PENDING") @@ -962,6 +1023,7 @@ def main() -> None: IntelIlp(), IntelL2(), IntelLdSt(), + IntelMissLat(), IntelMlp(), IntelPorts(), IntelSwpf(), --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 21:31:34 2024 Received: from mail-yw1-f202.google.com (mail-yw1-f202.google.com [209.85.128.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9361318872D for ; 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Thu, 26 Sep 2024 10:51:33 -0700 (PDT) Date: Thu, 26 Sep 2024 10:50:34 -0700 In-Reply-To: <20240926175035.408668-1-irogers@google.com> Message-Id: <20240926175035.408668-22-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240926175035.408668-1-irogers@google.com> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog Subject: [PATCH v4 21/22] perf jevents: Add upi_bw metric for Intel From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Break down UPI read and write bandwidth using uncore_upi counters. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/intel_metrics.py | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/tools/perf/pmu-events/intel_metrics.py b/tools/perf/pmu-events= /intel_metrics.py index ec15653e2cb6..8e1c0bc17b8a 100755 --- a/tools/perf/pmu-events/intel_metrics.py +++ b/tools/perf/pmu-events/intel_metrics.py @@ -990,6 +990,27 @@ def UncoreMemBw() -> Optional[MetricGroup]: ], description =3D "Memory Bandwidth") =20 =20 +def UncoreUpiBw() -> Optional[MetricGroup]: + try: + upi_rds =3D Event("UNC_UPI_RxL_FLITS.ALL_DATA") + upi_wrs =3D Event("UNC_UPI_TxL_FLITS.ALL_DATA") + except: + return None + + upi_total =3D upi_rds + upi_wrs + + # From "Uncore Performance Monitoring": When measuring the amount of + # bandwidth consumed by transmission of the data (i.e. NOT including + # the header), it should be .ALL_DATA / 9 * 64B. + scale =3D (64 / 9) / 1_000_000 + return MetricGroup("upi_bw", [ + Metric("upi_bw_read", "UPI read bandwidth", + d_ratio(upi_rds, interval_sec), f"{scale}MB/s"), + Metric("upi_bw_write", "DDR memory write bandwidth", + d_ratio(upi_wrs, interval_sec), f"{scale}MB/s"), + ], description =3D "UPI Bandwidth") + + def main() -> None: global _args =20 @@ -1031,6 +1052,7 @@ def main() -> None: UncoreDir(), UncoreMem(), UncoreMemBw(), + UncoreUpiBw(), ]) =20 =20 --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 21:31:34 2024 Received: from mail-yw1-f202.google.com (mail-yw1-f202.google.com [209.85.128.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C7E5188913 for ; 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Thu, 26 Sep 2024 10:51:35 -0700 (PDT) Date: Thu, 26 Sep 2024 10:50:35 -0700 In-Reply-To: <20240926175035.408668-1-irogers@google.com> Message-Id: <20240926175035.408668-23-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240926175035.408668-1-irogers@google.com> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog Subject: [PATCH v4 22/22] perf jevents: Add mesh bandwidth saturation metric for Intel From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Memory bandwidth saturation from CBOX/CHA events present in broadwellde, broadwellx, cascadelakex, haswellx, icelakex, skylakex and snowridgex. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/intel_metrics.py | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/tools/perf/pmu-events/intel_metrics.py b/tools/perf/pmu-events= /intel_metrics.py index 8e1c0bc17b8a..a3a317d13841 100755 --- a/tools/perf/pmu-events/intel_metrics.py +++ b/tools/perf/pmu-events/intel_metrics.py @@ -990,6 +990,22 @@ def UncoreMemBw() -> Optional[MetricGroup]: ], description =3D "Memory Bandwidth") =20 =20 +def UncoreMemSat() -> Optional[Metric]: + try: + clocks =3D Event("UNC_CHA_CLOCKTICKS", "UNC_C_CLOCKTICKS") + sat =3D Event("UNC_CHA_DISTRESS_ASSERTED.VERT", "UNC_CHA_FAST_ASSERTED= .VERT", + "UNC_C_FAST_ASSERTED") + except: + return None + + desc =3D ("Mesh Bandwidth saturation (% CBOX cycles with FAST signal ass= erted, " + "include QPI bandwidth saturation), lower is better") + if "UNC_CHA_" in sat.name: + desc =3D ("Mesh Bandwidth saturation (% CHA cycles with FAST signal as= serted, " + "include UPI bandwidth saturation), lower is better") + return Metric("mem_sat", desc, d_ratio(sat, clocks), "100%") + + def UncoreUpiBw() -> Optional[MetricGroup]: try: upi_rds =3D Event("UNC_UPI_RxL_FLITS.ALL_DATA") @@ -1052,6 +1068,7 @@ def main() -> None: UncoreDir(), UncoreMem(), UncoreMemBw(), + UncoreMemSat(), UncoreUpiBw(), ]) =20 --=20 2.46.1.824.gd892dcdcdd-goog