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Signed-off-by: Ian Rogers --- tools/perf/pmu-events/amd_metrics.py | 31 +++++++++++++++++++++++++--- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git a/tools/perf/pmu-events/amd_metrics.py b/tools/perf/pmu-events/a= md_metrics.py index 4f728e7aae4a..fd420466b999 100755 --- a/tools/perf/pmu-events/amd_metrics.py +++ b/tools/perf/pmu-events/amd_metrics.py @@ -1,14 +1,37 @@ #!/usr/bin/env python3 # SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause) -from metric import (JsonEncodeMetric, JsonEncodeMetricGroupDescriptions, L= oadEvents, - MetricGroup) +from metric import (d_ratio, has_event, Event, JsonEncodeMetric, JsonEncod= eMetricGroupDescriptions, + LoadEvents, Metric, MetricGroup, Select) import argparse import json +import math import os =20 # Global command line arguments. _args =3D None =20 +interval_sec =3D Event("duration_time") + +def Rapl() -> MetricGroup: + """Processor socket power consumption estimate. + + Use events from the running average power limit (RAPL) driver. + """ + # Watts =3D joules/second + # Currently only energy-pkg is supported by AMD: + # https://lore.kernel.org/lkml/20220105185659.643355-1-eranian@google.co= m/ + pkg =3D Event("power/energy\-pkg/") + cond_pkg =3D Select(pkg, has_event(pkg), math.nan) + scale =3D 2.3283064365386962890625e-10 + metrics =3D [ + Metric("cpu_power_pkg", "", + d_ratio(cond_pkg * scale, interval_sec), "Watts"), + ] + + return MetricGroup("cpu_power", metrics, + description=3D"Processor socket power consumption est= imates") + + def main() -> None: global _args =20 @@ -31,7 +54,9 @@ def main() -> None: directory =3D f"{_args.events_path}/x86/{_args.model}/" LoadEvents(directory) =20 - all_metrics =3D MetricGroup("",[]) + all_metrics =3D MetricGroup("", [ + Rapl(), + ]) =20 if _args.metricgroups: print(JsonEncodeMetricGroupDescriptions(all_metrics)) --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 22:34:04 2024 Received: from mail-yb1-f202.google.com (mail-yb1-f202.google.com [209.85.219.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4616D158210 for ; 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Thu, 26 Sep 2024 10:41:13 -0700 (PDT) Date: Thu, 26 Sep 2024 10:40:51 -0700 In-Reply-To: <20240926174101.406874-1-irogers@google.com> Message-Id: <20240926174101.406874-3-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240926174101.406874-1-irogers@google.com> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog Subject: [PATCH v4 02/12] perf jevents: Add idle metric for AMD zen models From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , John Garry , Jing Zhang , Sandipan Das , Benjamin Gray , Xu Yang , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Compute using the msr PMU the percentage of wallclock cycles where the CPUs are in a low power state. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/amd_metrics.py | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/tools/perf/pmu-events/amd_metrics.py b/tools/perf/pmu-events/a= md_metrics.py index fd420466b999..e069b95d6470 100755 --- a/tools/perf/pmu-events/amd_metrics.py +++ b/tools/perf/pmu-events/amd_metrics.py @@ -1,7 +1,8 @@ #!/usr/bin/env python3 # SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause) -from metric import (d_ratio, has_event, Event, JsonEncodeMetric, JsonEncod= eMetricGroupDescriptions, - LoadEvents, Metric, MetricGroup, Select) +from metric import (d_ratio, has_event, max, Event, JsonEncodeMetric, + JsonEncodeMetricGroupDescriptions, LoadEvents, Metric, + MetricGroup, Select) import argparse import json import math @@ -12,6 +13,16 @@ _args =3D None =20 interval_sec =3D Event("duration_time") =20 +def Idle() -> Metric: + cyc =3D Event("msr/mperf/") + tsc =3D Event("msr/tsc/") + low =3D max(tsc - cyc, 0) + return Metric( + "idle", + "Percentage of total wallclock cycles where CPUs are in low power st= ate (C1 or deeper sleep state)", + d_ratio(low, tsc), "100%") + + def Rapl() -> MetricGroup: """Processor socket power consumption estimate. =20 @@ -55,6 +66,7 @@ def main() -> None: LoadEvents(directory) =20 all_metrics =3D MetricGroup("", [ + Idle(), Rapl(), ]) =20 --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 22:34:04 2024 Received: from mail-yb1-f201.google.com (mail-yb1-f201.google.com [209.85.219.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6CCB165EF5 for ; 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Thu, 26 Sep 2024 10:41:15 -0700 (PDT) Date: Thu, 26 Sep 2024 10:40:52 -0700 In-Reply-To: <20240926174101.406874-1-irogers@google.com> Message-Id: <20240926174101.406874-4-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240926174101.406874-1-irogers@google.com> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog Subject: [PATCH v4 03/12] perf jevents: Add upc metric for uops per cycle for AMD From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , John Garry , Jing Zhang , Sandipan Das , Benjamin Gray , Xu Yang , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The metric adjusts for whether or not SMT is on. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/amd_metrics.py | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/tools/perf/pmu-events/amd_metrics.py b/tools/perf/pmu-events/a= md_metrics.py index e069b95d6470..c64470d4822e 100755 --- a/tools/perf/pmu-events/amd_metrics.py +++ b/tools/perf/pmu-events/amd_metrics.py @@ -1,8 +1,8 @@ #!/usr/bin/env python3 # SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause) from metric import (d_ratio, has_event, max, Event, JsonEncodeMetric, - JsonEncodeMetricGroupDescriptions, LoadEvents, Metric, - MetricGroup, Select) + JsonEncodeMetricGroupDescriptions, Literal, LoadEvents, + Metric, MetricGroup, Select) import argparse import json import math @@ -10,8 +10,17 @@ import os =20 # Global command line arguments. _args =3D None - +_zen_model: int =3D 1 interval_sec =3D Event("duration_time") +cycles =3D Event("cycles") +# Number of CPU cycles scaled for SMT. +smt_cycles =3D Select(cycles / 2, Literal("#smt_on"), cycles) + +def AmdUpc() -> Metric: + ops =3D Event("ex_ret_ops", "ex_ret_cops") + upc =3D d_ratio(ops, smt_cycles) + return Metric("upc", "Micro-ops retired per core cycle (higher is better= )", + upc, "uops/cycle") =20 def Idle() -> Metric: cyc =3D Event("msr/mperf/") @@ -45,6 +54,7 @@ def Rapl() -> MetricGroup: =20 def main() -> None: global _args + global _zen_model =20 def dir_path(path: str) -> str: """Validate path is a directory for argparse.""" @@ -65,7 +75,10 @@ def main() -> None: directory =3D f"{_args.events_path}/x86/{_args.model}/" LoadEvents(directory) =20 + _zen_model =3D int(_args.model[6:]) + all_metrics =3D MetricGroup("", [ + AmdUpc(), Idle(), Rapl(), ]) --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 22:34:04 2024 Received: from mail-yw1-f202.google.com (mail-yw1-f202.google.com [209.85.128.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3CF0165EFA for ; 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Thu, 26 Sep 2024 10:41:17 -0700 (PDT) Date: Thu, 26 Sep 2024 10:40:53 -0700 In-Reply-To: <20240926174101.406874-1-irogers@google.com> Message-Id: <20240926174101.406874-5-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240926174101.406874-1-irogers@google.com> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog Subject: [PATCH v4 04/12] perf jevents: Add br metric group for branch statistics on AMD From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , John Garry , Jing Zhang , Sandipan Das , Benjamin Gray , Xu Yang , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The br metric group for branches itself comprises metric groups for total, taken, conditional, fused and far metric groups using json events. The lack of conditional events on anything but zen2 means this category is lacking on zen1, zen3 and zen4. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/amd_metrics.py | 105 +++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) diff --git a/tools/perf/pmu-events/amd_metrics.py b/tools/perf/pmu-events/a= md_metrics.py index c64470d4822e..90545d4862a6 100755 --- a/tools/perf/pmu-events/amd_metrics.py +++ b/tools/perf/pmu-events/amd_metrics.py @@ -7,15 +7,119 @@ import argparse import json import math import os +from typing import Optional =20 # Global command line arguments. _args =3D None _zen_model: int =3D 1 interval_sec =3D Event("duration_time") +ins =3D Event("instructions") cycles =3D Event("cycles") # Number of CPU cycles scaled for SMT. smt_cycles =3D Select(cycles / 2, Literal("#smt_on"), cycles) =20 +def AmdBr(): + def Total() -> MetricGroup: + br =3D Event("ex_ret_brn") + br_m_all =3D Event("ex_ret_brn_misp") + br_clr =3D Event("ex_ret_msprd_brnch_instr_dir_msmtch", "ex_ret_brn_re= sync") + + br_r =3D d_ratio(br, interval_sec) + ins_r =3D d_ratio(ins, br) + misp_r =3D d_ratio(br_m_all, br) + clr_r =3D d_ratio(br_clr, interval_sec) + + return MetricGroup("br_total", [ + Metric("br_total_retired", + "The number of branch instructions retired per second.", br= _r, + "insn/s"), + Metric( + "br_total_mispred", + "The number of branch instructions retired, of any type, that = were " + "not correctly predicted as a percentage of all branch instruc= ions.", + misp_r, "100%"), + Metric("br_total_insn_between_branches", + "The number of instructions divided by the number of branch= es.", + ins_r, "insn"), + Metric("br_total_insn_fe_resteers", + "The number of resync branches per second.", clr_r, "req/s") + ]) + + def Taken() -> MetricGroup: + br =3D Event("ex_ret_brn_tkn") + br_m_tk =3D Event("ex_ret_brn_tkn_misp") + br_r =3D d_ratio(br, interval_sec) + ins_r =3D d_ratio(ins, br) + misp_r =3D d_ratio(br_m_tk, br) + return MetricGroup("br_taken", [ + Metric("br_taken_retired", + "The number of taken branches that were retired per second.= ", + br_r, "insn/s"), + Metric( + "br_taken_mispred", + "The number of retired taken branch instructions that were " + "mispredicted as a percentage of all taken branches.", misp_r, + "100%"), + Metric( + "br_taken_insn_between_branches", + "The number of instructions divided by the number of taken bra= nches.", + ins_r, "insn"), + ]) + + def Conditional() -> Optional[MetricGroup]: + global _zen_model + br =3D Event("ex_ret_cond") + br_r =3D d_ratio(br, interval_sec) + ins_r =3D d_ratio(ins, br) + + metrics =3D [ + Metric("br_cond_retired", "Retired conditional branch instructions= .", + br_r, "insn/s"), + Metric("br_cond_insn_between_branches", + "The number of instructions divided by the number of condit= ional " + "branches.", ins_r, "insn"), + ] + if _zen_model =3D=3D 2: + br_m_cond =3D Event("ex_ret_cond_misp") + misp_r =3D d_ratio(br_m_cond, br) + metrics +=3D [ + Metric("br_cond_mispred", + "Retired conditional branch instructions mispredicted as = a " + "percentage of all conditional branches.", misp_r, "100%"= ), + ] + + return MetricGroup("br_cond", metrics) + + def Fused() -> MetricGroup: + br =3D Event("ex_ret_fused_instr", "ex_ret_fus_brnch_inst") + br_r =3D d_ratio(br, interval_sec) + ins_r =3D d_ratio(ins, br) + return MetricGroup("br_cond", [ + Metric("br_fused_retired", + "Retired fused branch instructions per second.", br_r, "ins= n/s"), + Metric( + "br_fused_insn_between_branches", + "The number of instructions divided by the number of fused " + "branches.", ins_r, "insn"), + ]) + + def Far() -> MetricGroup: + br =3D Event("ex_ret_brn_far") + br_r =3D d_ratio(br, interval_sec) + ins_r =3D d_ratio(ins, br) + return MetricGroup("br_far", [ + Metric("br_far_retired", "Retired far control transfers per second= .", + br_r, "insn/s"), + Metric( + "br_far_insn_between_branches", + "The number of instructions divided by the number of far branc= hes.", + ins_r, "insn"), + ]) + + return MetricGroup("br", [Total(), Taken(), Conditional(), Fused(), Far(= )], + description=3D"breakdown of retired branch instructio= ns") + + def AmdUpc() -> Metric: ops =3D Event("ex_ret_ops", "ex_ret_cops") upc =3D d_ratio(ops, smt_cycles) @@ -78,6 +182,7 @@ def main() -> None: _zen_model =3D int(_args.model[6:]) =20 all_metrics =3D MetricGroup("", [ + AmdBr(), AmdUpc(), Idle(), Rapl(), --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 22:34:04 2024 Received: from mail-yw1-f202.google.com (mail-yw1-f202.google.com [209.85.128.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E52CB157E61 for ; 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Thu, 26 Sep 2024 10:41:19 -0700 (PDT) Date: Thu, 26 Sep 2024 10:40:54 -0700 In-Reply-To: <20240926174101.406874-1-irogers@google.com> Message-Id: <20240926174101.406874-6-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240926174101.406874-1-irogers@google.com> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog Subject: [PATCH v4 05/12] perf jevents: Add software prefetch (swpf) metric group for AMD From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , John Garry , Jing Zhang , Sandipan Das , Benjamin Gray , Xu Yang , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add metrics that give the utility of software prefetches on zen2, zen3 and zen4. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/amd_metrics.py | 96 ++++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/tools/perf/pmu-events/amd_metrics.py b/tools/perf/pmu-events/a= md_metrics.py index 90545d4862a6..05a16e748d2e 100755 --- a/tools/perf/pmu-events/amd_metrics.py +++ b/tools/perf/pmu-events/amd_metrics.py @@ -120,6 +120,101 @@ def AmdBr(): description=3D"breakdown of retired branch instructio= ns") =20 =20 +def AmdSwpf() -> Optional[MetricGroup]: + """Returns a MetricGroup representing AMD software prefetch metrics.""" + global _zen_model + if _zen_model <=3D 1: + return None + + swp_ld =3D Event("ls_dispatch.ld_dispatch") + swp_t0 =3D Event("ls_pref_instr_disp.prefetch") + swp_w =3D Event("ls_pref_instr_disp.prefetch_w") # Missing on Zen1 + swp_nt =3D Event("ls_pref_instr_disp.prefetch_nta") + swp_mab =3D Event("ls_inef_sw_pref.mab_mch_cnt") + swp_l2 =3D Event("ls_sw_pf_dc_fills.local_l2", + "ls_sw_pf_dc_fills.lcl_l2", + "ls_sw_pf_dc_fill.ls_mabresp_lcl_l2") + swp_lc =3D Event("ls_sw_pf_dc_fills.local_ccx", + "ls_sw_pf_dc_fills.int_cache", + "ls_sw_pf_dc_fill.ls_mabresp_lcl_cache") + swp_lm =3D Event("ls_sw_pf_dc_fills.dram_io_near", + "ls_sw_pf_dc_fills.mem_io_local", + "ls_sw_pf_dc_fill.ls_mabresp_lcl_dram") + swp_rc =3D Event("ls_sw_pf_dc_fills.far_cache", + "ls_sw_pf_dc_fills.ext_cache_remote", + "ls_sw_pf_dc_fill.ls_mabresp_rmt_cache") + swp_rm =3D Event("ls_sw_pf_dc_fills.dram_io_far", + "ls_sw_pf_dc_fills.mem_io_remote", + "ls_sw_pf_dc_fill.ls_mabresp_rmt_dram") + + # All the swpf that were satisfied beyond L1D are good. + all_pf =3D swp_t0 + swp_w + swp_nt + good_pf =3D swp_l2 + swp_lc + swp_lm + swp_rc + swp_rm + bad_pf =3D max(all_pf - good_pf, 0) + + loc_pf =3D swp_l2 + swp_lc + swp_lm + rem_pf =3D swp_rc + swp_rm + + req_pend =3D max(0, bad_pf - swp_mab) + + r1 =3D d_ratio(ins, all_pf) + r2 =3D d_ratio(swp_ld, all_pf) + r3 =3D d_ratio(swp_t0, interval_sec) + r4 =3D d_ratio(swp_w, interval_sec) + r5 =3D d_ratio(swp_nt, interval_sec) + overview =3D MetricGroup("swpf_overview", [ + Metric("swpf_ov_insn_bt_swpf", "Insn between SWPF", r1, "insns"), + Metric("swpf_ov_loads_bt_swpf", "Loads between SWPF", r2, "loads"), + Metric("swpf_ov_rate_prefetch_t0_t1_t2", "Rate prefetch TO_T1_T2", r= 3, + "insns/sec"), + Metric("swpf_ov_rate_prefetch_w", "Rate prefetch W", r4, "insns/sec"= ), + Metric("swpf_ov_rate_preftech_nta", "Rate prefetch NTA", r5, "insns/= sec"), + ]) + + r1 =3D d_ratio(swp_mab, all_pf) + r2 =3D d_ratio(req_pend, all_pf) + usefulness_bad =3D MetricGroup("swpf_usefulness_bad", [ + Metric("swpf_use_bad_hit_l1", "Usefulness bad hit L1", r1, "100%"), + Metric("swpf_use_bad_req_pend", "Usefulness bad req pending", r2, "1= 00%"), + ]) + + r1 =3D d_ratio(good_pf, all_pf) + usefulness_good =3D MetricGroup("swpf_usefulness_good", [ + Metric("swpf_use_good_other_src", "Usefulness good other src", r1, + "100%"), + ]) + + usefulness =3D MetricGroup("swpf_usefulness", [ + usefulness_bad, + usefulness_good, + ]) + + r1 =3D d_ratio(swp_l2, good_pf) + r2 =3D d_ratio(swp_lc, good_pf) + r3 =3D d_ratio(swp_lm, good_pf) + data_src_local =3D MetricGroup("swpf_data_src_local", [ + Metric("swpf_data_src_local_l2", "Data source local l2", r1, "100%"), + Metric("swpf_data_src_local_ccx_l3_loc_ccx", + "Data source local ccx l3 loc ccx", r2, "100%"), + Metric("swpf_data_src_local_memory_or_io", + "Data source local memory or IO", r3, "100%"), + ]) + + r1 =3D d_ratio(swp_rc, good_pf) + r2 =3D d_ratio(swp_rm, good_pf) + data_src_remote =3D MetricGroup("swpf_data_src_remote", [ + Metric("swpf_data_src_remote_cache", "Data source remote cache", r1, + "100%"), + Metric("swpf_data_src_remote_memory_or_io", + "Data source remote memory or IO", r2, "100%"), + ]) + + data_src =3D MetricGroup("swpf_data_src", [data_src_local, data_src_remo= te]) + + return MetricGroup("swpf", [overview, usefulness, data_src], + description=3D"Software prefetch breakdown (CCX L3 = =3D L3 of current thread, Loc CCX =3D CCX cache on some socket)") + + def AmdUpc() -> Metric: ops =3D Event("ex_ret_ops", "ex_ret_cops") upc =3D d_ratio(ops, smt_cycles) @@ -183,6 +278,7 @@ def main() -> None: =20 all_metrics =3D MetricGroup("", [ AmdBr(), + AmdSwpf(), AmdUpc(), Idle(), Rapl(), --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 22:34:04 2024 Received: from mail-yw1-f202.google.com (mail-yw1-f202.google.com [209.85.128.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59469176FB8 for ; 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Thu, 26 Sep 2024 10:41:22 -0700 (PDT) Date: Thu, 26 Sep 2024 10:40:55 -0700 In-Reply-To: <20240926174101.406874-1-irogers@google.com> Message-Id: <20240926174101.406874-7-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240926174101.406874-1-irogers@google.com> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog Subject: [PATCH v4 06/12] perf jevents: Add hardware prefetch (hwpf) metric group for AMD From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , John Garry , Jing Zhang , Sandipan Das , Benjamin Gray , Xu Yang , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add metrics that give the utility of hardware prefetches on zen2, zen3 and zen4. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/amd_metrics.py | 62 ++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/tools/perf/pmu-events/amd_metrics.py b/tools/perf/pmu-events/a= md_metrics.py index 05a16e748d2e..2d1fc8411d61 100755 --- a/tools/perf/pmu-events/amd_metrics.py +++ b/tools/perf/pmu-events/amd_metrics.py @@ -120,6 +120,67 @@ def AmdBr(): description=3D"breakdown of retired branch instructio= ns") =20 =20 +def AmdHwpf(): + """Returns a MetricGroup representing AMD hardware prefetch metrics.""" + global _zen_model + if _zen_model <=3D 1: + return None + + hwp_ld =3D Event("ls_dispatch.ld_dispatch") + hwp_l2 =3D Event("ls_hw_pf_dc_fills.local_l2", + "ls_hw_pf_dc_fills.lcl_l2", + "ls_hw_pf_dc_fill.ls_mabresp_lcl_l2") + hwp_lc =3D Event("ls_hw_pf_dc_fills.local_ccx", + "ls_hw_pf_dc_fills.int_cache", + "ls_hw_pf_dc_fill.ls_mabresp_lcl_cache") + hwp_lm =3D Event("ls_hw_pf_dc_fills.dram_io_near", + "ls_hw_pf_dc_fills.mem_io_local", + "ls_hw_pf_dc_fill.ls_mabresp_lcl_dram") + hwp_rc =3D Event("ls_hw_pf_dc_fills.far_cache", + "ls_hw_pf_dc_fills.ext_cache_remote", + "ls_hw_pf_dc_fill.ls_mabresp_rmt_cache") + hwp_rm =3D Event("ls_hw_pf_dc_fills.dram_io_far", + "ls_hw_pf_dc_fills.mem_io_remote", + "ls_hw_pf_dc_fill.ls_mabresp_rmt_dram") + + loc_pf =3D hwp_l2 + hwp_lc + hwp_lm + rem_pf =3D hwp_rc + hwp_rm + all_pf =3D loc_pf + rem_pf + + r1 =3D d_ratio(ins, all_pf) + r2 =3D d_ratio(hwp_ld, all_pf) + r3 =3D d_ratio(all_pf, interval_sec) + + overview =3D MetricGroup("hwpf_overview", [ + Metric("hwpf_ov_insn_bt_hwpf", "Insn between HWPF", r1, "insns"), + Metric("hwpf_ov_loads_bt_hwpf", "Loads between HWPF", r2, "loads"), + Metric("hwpf_ov_rate", "HWPF per second", r3, "hwpf/s"), + ]) + r1 =3D d_ratio(hwp_l2, all_pf) + r2 =3D d_ratio(hwp_lc, all_pf) + r3 =3D d_ratio(hwp_lm, all_pf) + data_src_local =3D MetricGroup("hwpf_data_src_local", [ + Metric("hwpf_data_src_local_l2", "Data source local l2", r1, "100%"), + Metric("hwpf_data_src_local_ccx_l3_loc_ccx", + "Data source local ccx l3 loc ccx", r2, "100%"), + Metric("hwpf_data_src_local_memory_or_io", + "Data source local memory or IO", r3, "100%"), + ]) + + r1 =3D d_ratio(hwp_rc, all_pf) + r2 =3D d_ratio(hwp_rm, all_pf) + data_src_remote =3D MetricGroup("hwpf_data_src_remote", [ + Metric("hwpf_data_src_remote_cache", "Data source remote cache", r1, + "100%"), + Metric("hwpf_data_src_remote_memory_or_io", + "Data source remote memory or IO", r2, "100%"), + ]) + + data_src =3D MetricGroup("hwpf_data_src", [data_src_local, data_src_remo= te]) + return MetricGroup("hwpf", [overview, data_src], + description=3D"Hardware prefetch breakdown (CCX L3 = =3D L3 of current thread, Loc CCX =3D CCX cache on some socket)") + + def AmdSwpf() -> Optional[MetricGroup]: """Returns a MetricGroup representing AMD software prefetch metrics.""" global _zen_model @@ -278,6 +339,7 @@ def main() -> None: =20 all_metrics =3D MetricGroup("", [ AmdBr(), + AmdHwpf(), AmdSwpf(), AmdUpc(), Idle(), --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 22:34:04 2024 Received: from mail-yb1-f201.google.com (mail-yb1-f201.google.com [209.85.219.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D517F17C985 for ; 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Thu, 26 Sep 2024 10:41:24 -0700 (PDT) Date: Thu, 26 Sep 2024 10:40:56 -0700 In-Reply-To: <20240926174101.406874-1-irogers@google.com> Message-Id: <20240926174101.406874-8-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240926174101.406874-1-irogers@google.com> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog Subject: [PATCH v4 07/12] perf jevents: Add itlb metric group for AMD From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , John Garry , Jing Zhang , Sandipan Das , Benjamin Gray , Xu Yang , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add metrics that give an overview and details of the l1 itlb (zen1, zen2, zen3) and l2 itlb (all zens). Signed-off-by: Ian Rogers --- tools/perf/pmu-events/amd_metrics.py | 48 ++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/tools/perf/pmu-events/amd_metrics.py b/tools/perf/pmu-events/a= md_metrics.py index 2d1fc8411d61..bfed478f508b 100755 --- a/tools/perf/pmu-events/amd_metrics.py +++ b/tools/perf/pmu-events/amd_metrics.py @@ -120,6 +120,53 @@ def AmdBr(): description=3D"breakdown of retired branch instructio= ns") =20 =20 +def AmdItlb(): + global _zen_model + l2h =3D Event("bp_l1_tlb_miss_l2_tlb_hit", "bp_l1_tlb_miss_l2_hit") + l2m =3D Event("l2_itlb_misses") + l2r =3D l2h + l2m + + itlb_l1_mg =3D None + l1m =3D l2r + if _zen_model <=3D 3: + l1r =3D Event("ic_fw32") + l1h =3D max(l1r - l1m, 0) + itlb_l1_mg =3D MetricGroup("itlb_l1", [ + Metric("itlb_l1_hits", + "L1 ITLB hits as a perecentage of L1 ITLB accesses.", + d_ratio(l1h, l1h + l1m), "100%"), + Metric("itlb_l1_miss", + "L1 ITLB misses as a perecentage of L1 ITLB accesses.", + d_ratio(l1m, l1h + l1m), "100%"), + Metric("itlb_l1_reqs", + "The number of 32B fetch windows transferred from IC pipe t= o DE " + "instruction decoder per second.", d_ratio(l1r, interval_se= c), + "windows/sec"), + ]) + + return MetricGroup("itlb", [ + MetricGroup("itlb_ov", [ + Metric("itlb_ov_insn_bt_l1_miss", + "Number of instructions between l1 misses", d_ratio( + ins, l1m), "insns"), + Metric("itlb_ov_insn_bt_l2_miss", + "Number of instructions between l2 misses", d_ratio( + ins, l2m), "insns"), + ]), + itlb_l1_mg, + MetricGroup("itlb_l2", [ + Metric("itlb_l2_hits", + "L2 ITLB hits as a percentage of all L2 ITLB accesses.", + d_ratio(l2h, l2r), "100%"), + Metric("itlb_l2_miss", + "L2 ITLB misses as a percentage of all L2 ITLB accesses.", + d_ratio(l2m, l2r), "100%"), + Metric("itlb_l2_reqs", "ITLB accesses per second.", + d_ratio(l2r, interval_sec), "accesses/sec"), + ]), + ], description=3D"Instruction TLB breakdown") + + def AmdHwpf(): """Returns a MetricGroup representing AMD hardware prefetch metrics.""" global _zen_model @@ -339,6 +386,7 @@ def main() -> None: =20 all_metrics =3D MetricGroup("", [ AmdBr(), + AmdItlb(), AmdHwpf(), AmdSwpf(), AmdUpc(), --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 22:34:04 2024 Received: from mail-yb1-f202.google.com (mail-yb1-f202.google.com [209.85.219.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 493F617DE16 for ; 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Thu, 26 Sep 2024 10:41:27 -0700 (PDT) Date: Thu, 26 Sep 2024 10:40:57 -0700 In-Reply-To: <20240926174101.406874-1-irogers@google.com> Message-Id: <20240926174101.406874-9-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240926174101.406874-1-irogers@google.com> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog Subject: [PATCH v4 08/12] perf jevents: Add dtlb metric group for AMD From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , John Garry , Jing Zhang , Sandipan Das , Benjamin Gray , Xu Yang , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add metrics that give an overview and details of the dtlb (zen1, zen2, zen3). Signed-off-by: Ian Rogers --- tools/perf/pmu-events/amd_metrics.py | 109 +++++++++++++++++++++++++++ 1 file changed, 109 insertions(+) diff --git a/tools/perf/pmu-events/amd_metrics.py b/tools/perf/pmu-events/a= md_metrics.py index bfed478f508b..7fd2139766f9 100755 --- a/tools/perf/pmu-events/amd_metrics.py +++ b/tools/perf/pmu-events/amd_metrics.py @@ -120,6 +120,114 @@ def AmdBr(): description=3D"breakdown of retired branch instructio= ns") =20 =20 +def AmdDtlb() -> Optional[MetricGroup]: + global _zen_model + if _zen_model >=3D 4: + return None + + d_dat =3D Event("ls_dc_accesses") if _zen_model <=3D 3 else None + d_h4k =3D Event("ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit") + d_hcoal =3D Event("ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit") if _= zen_model >=3D 2 else 0 + d_h2m =3D Event("ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit") + d_h1g =3D Event("ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit") + + d_m4k =3D Event("ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss") + d_mcoal =3D Event("ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss") if = _zen_model >=3D 2 else 0 + d_m2m =3D Event("ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss") + d_m1g =3D Event("ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss") + + d_w0 =3D Event("ls_tablewalker.dc_type0") if _zen_model <=3D 3 else None + d_w1 =3D Event("ls_tablewalker.dc_type1") if _zen_model <=3D 3 else None + walks =3D d_w0 + d_w1 + walks_r =3D d_ratio(walks, interval_sec) + ins_w =3D d_ratio(ins, walks) + l1 =3D d_dat + l1_r =3D d_ratio(l1, interval_sec) + l2_hits =3D d_h4k + d_hcoal + d_h2m + d_h1g + l2_miss =3D d_m4k + d_mcoal + d_m2m + d_m1g + l2_r =3D d_ratio(l2_hits + l2_miss, interval_sec) + l1_miss =3D l2_hits + l2_miss + walks + l1_hits =3D max(l1 - l1_miss, 0) + ins_l =3D d_ratio(ins, l1_miss) + + return MetricGroup("dtlb", [ + MetricGroup("dtlb_ov", [ + Metric("dtlb_ov_insn_bt_l1_miss", + "DTLB overview: instructions between l1 misses.", ins_l, + "insns"), + Metric("dtlb_ov_insn_bt_walks", + "DTLB overview: instructions between dtlb page table walk= s.", + ins_w, "insns"), + ]), + MetricGroup("dtlb_l1", [ + Metric("dtlb_l1_hits", + "DTLB L1 hits as percentage of all DTLB L1 accesses.", + d_ratio(l1_hits, l1), "100%"), + Metric("dtlb_l1_miss", + "DTLB L1 misses as percentage of all DTLB L1 accesses.", + d_ratio(l1_miss, l1), "100%"), + Metric("dtlb_l1_reqs", "DTLB L1 accesses per second.", l1_r, + "insns/s"), + ]), + MetricGroup("dtlb_l2", [ + Metric("dtlb_l2_hits", + "DTLB L2 hits as percentage of all DTLB L2 accesses.", + d_ratio(l2_hits, l2_hits + l2_miss), "100%"), + Metric("dtlb_l2_miss", + "DTLB L2 misses as percentage of all DTLB L2 accesses.", + d_ratio(l2_miss, l2_hits + l2_miss), "100%"), + Metric("dtlb_l2_reqs", "DTLB L2 accesses per second.", l2_r, + "insns/s"), + MetricGroup("dtlb_l2_4kb", [ + Metric( + "dtlb_l2_4kb_hits", + "DTLB L2 4kb page size hits as percentage of all DTLB L2= 4kb " + "accesses.", d_ratio(d_h4k, d_h4k + d_m4k), "100%"), + Metric( + "dtlb_l2_4kb_miss", + "DTLB L2 4kb page size misses as percentage of all DTLB = L2 4kb" + "accesses.", d_ratio(d_m4k, d_h4k + d_m4k), "100%") + ]), + MetricGroup("dtlb_l2_coalesced", [ + Metric( + "dtlb_l2_coal_hits", + "DTLB L2 coalesced page (16kb) hits as percentage of all= DTLB " + "L2 coalesced accesses.", d_ratio(d_hcoal, + d_hcoal + d_mcoal), "1= 00%"), + Metric( + "dtlb_l2_coal_miss", + "DTLB L2 coalesced page (16kb) misses as percentage of a= ll " + "DTLB L2 coalesced accesses.", + d_ratio(d_mcoal, d_hcoal + d_mcoal), "100%") + ]), + MetricGroup("dtlb_l2_2mb", [ + Metric( + "dtlb_l2_2mb_hits", + "DTLB L2 2mb page size hits as percentage of all DTLB L2= 2mb " + "accesses.", d_ratio(d_h2m, d_h2m + d_m2m), "100%"), + Metric( + "dtlb_l2_2mb_miss", + "DTLB L2 2mb page size misses as percentage of all DTLB = L2 " + "accesses.", d_ratio(d_m2m, d_h2m + d_m2m), "100%") + ]), + MetricGroup("dtlb_l2_1g", [ + Metric( + "dtlb_l2_1g_hits", + "DTLB L2 1gb page size hits as percentage of all DTLB L2= 1gb " + "accesses.", d_ratio(d_h1g, d_h1g + d_m1g), "100%"), + Metric( + "dtlb_l2_1g_miss", + "DTLB L2 1gb page size misses as percentage of all DTLB = L2 " + "1gb accesses.", d_ratio(d_m1g, d_h1g + d_m1g), "100%") + ]), + ]), + MetricGroup("dtlb_walks", [ + Metric("dtlb_walks_reqs", "DTLB page table walks per second.", + walks_r, "walks/s"), + ]), + ], description=3D"Data TLB metrics") + + def AmdItlb(): global _zen_model l2h =3D Event("bp_l1_tlb_miss_l2_tlb_hit", "bp_l1_tlb_miss_l2_hit") @@ -386,6 +494,7 @@ def main() -> None: =20 all_metrics =3D MetricGroup("", [ AmdBr(), + AmdDtlb(), AmdItlb(), AmdHwpf(), AmdSwpf(), --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 22:34:04 2024 Received: from mail-yb1-f202.google.com (mail-yb1-f202.google.com [209.85.219.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D2F751607AA for ; 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Thu, 26 Sep 2024 10:41:29 -0700 (PDT) Date: Thu, 26 Sep 2024 10:40:58 -0700 In-Reply-To: <20240926174101.406874-1-irogers@google.com> Message-Id: <20240926174101.406874-10-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240926174101.406874-1-irogers@google.com> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog Subject: [PATCH v4 09/12] perf jevents: Add uncore l3 metric group for AMD From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , John Garry , Jing Zhang , Sandipan Das , Benjamin Gray , Xu Yang , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Metrics use the amd_l3 PMU for access/miss/hit information. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/amd_metrics.py | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/tools/perf/pmu-events/amd_metrics.py b/tools/perf/pmu-events/a= md_metrics.py index 7fd2139766f9..af99da14d946 100755 --- a/tools/perf/pmu-events/amd_metrics.py +++ b/tools/perf/pmu-events/amd_metrics.py @@ -466,6 +466,22 @@ def Rapl() -> MetricGroup: return MetricGroup("cpu_power", metrics, description=3D"Processor socket power consumption est= imates") =20 +def UncoreL3(): + acc =3D Event("l3_lookup_state.all_coherent_accesses_to_l3", + "l3_lookup_state.all_l3_req_typs") + miss =3D Event("l3_lookup_state.l3_miss", + "l3_comb_clstr_state.request_miss") + acc =3D max(acc, miss) + hits =3D acc - miss + + return MetricGroup("l3", [ + Metric("l3_accesses", "L3 victim cache accesses", + d_ratio(acc, interval_sec), "accesses/sec"), + Metric("l3_hits", "L3 victim cache hit rate", d_ratio(hits, acc), "1= 00%"), + Metric("l3_miss", "L3 victim cache miss rate", d_ratio(miss, acc), + "100%"), + ], description=3D"L3 cache breakdown per CCX") + =20 def main() -> None: global _args @@ -501,6 +517,7 @@ def main() -> None: AmdUpc(), Idle(), Rapl(), + UncoreL3(), ]) =20 if _args.metricgroups: --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 22:34:04 2024 Received: from mail-yw1-f201.google.com (mail-yw1-f201.google.com [209.85.128.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7EA3B184536 for ; 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Thu, 26 Sep 2024 10:41:32 -0700 (PDT) Date: Thu, 26 Sep 2024 10:40:59 -0700 In-Reply-To: <20240926174101.406874-1-irogers@google.com> Message-Id: <20240926174101.406874-11-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240926174101.406874-1-irogers@google.com> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog Subject: [PATCH v4 10/12] perf jevents: Add load store breakdown metrics ldst for AMD From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , John Garry , Jing Zhang , Sandipan Das , Benjamin Gray , Xu Yang , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Give breakdown of number of instructions. Use the counter mask (cmask) to show the number of cycles taken to retire the instructions. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/amd_metrics.py | 75 ++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/tools/perf/pmu-events/amd_metrics.py b/tools/perf/pmu-events/a= md_metrics.py index af99da14d946..3f77d1bbf1c9 100755 --- a/tools/perf/pmu-events/amd_metrics.py +++ b/tools/perf/pmu-events/amd_metrics.py @@ -275,6 +275,80 @@ def AmdItlb(): ], description=3D"Instruction TLB breakdown") =20 =20 +def AmdLdSt() -> MetricGroup: + ldst_ld =3D Event("ls_dispatch.ld_dispatch") + ldst_st =3D Event("ls_dispatch.store_dispatch") + ldst_ldc1 =3D Event(f"{ldst_ld}/cmask=3D1/") + ldst_stc1 =3D Event(f"{ldst_st}/cmask=3D1/") + ldst_ldc2 =3D Event(f"{ldst_ld}/cmask=3D2/") + ldst_stc2 =3D Event(f"{ldst_st}/cmask=3D2/") + ldst_ldc3 =3D Event(f"{ldst_ld}/cmask=3D3/") + ldst_stc3 =3D Event(f"{ldst_st}/cmask=3D3/") + ldst_cyc =3D Event("ls_not_halted_cyc") + + ld_rate =3D d_ratio(ldst_ld, interval_sec) + st_rate =3D d_ratio(ldst_st, interval_sec) + + ld_v1 =3D max(ldst_ldc1 - ldst_ldc2, 0) + ld_v2 =3D max(ldst_ldc2 - ldst_ldc3, 0) + ld_v3 =3D ldst_ldc3 + + st_v1 =3D max(ldst_stc1 - ldst_stc2, 0) + st_v2 =3D max(ldst_stc2 - ldst_stc3, 0) + st_v3 =3D ldst_stc3 + + return MetricGroup("ldst", [ + MetricGroup("ldst_total", [ + Metric("ldst_total_ld", "Number of loads dispatched per second.", + ld_rate, "insns/sec"), + Metric("ldst_total_st", "Number of stores dispatched per second.= ", + st_rate, "insns/sec"), + ]), + MetricGroup("ldst_percent_insn", [ + Metric("ldst_percent_insn_ld", + "Load instructions as a percentage of all instructions.", + d_ratio(ldst_ld, ins), "100%"), + Metric("ldst_percent_insn_st", + "Store instructions as a percentage of all instructions.", + d_ratio(ldst_st, ins), "100%"), + ]), + MetricGroup("ldst_ret_loads_per_cycle", [ + Metric( + "ldst_ret_loads_per_cycle_1", + "Load instructions retiring in 1 cycle as a percentage of al= l " + "unhalted cycles.", d_ratio(ld_v1, ldst_cyc), "100%"), + Metric( + "ldst_ret_loads_per_cycle_2", + "Load instructions retiring in 2 cycles as a percentage of a= ll " + "unhalted cycles.", d_ratio(ld_v2, ldst_cyc), "100%"), + Metric( + "ldst_ret_loads_per_cycle_3", + "Load instructions retiring in 3 or more cycles as a percent= age" + "of all unhalted cycles.", d_ratio(ld_v3, ldst_cyc), "100%"), + ]), + MetricGroup("ldst_ret_stores_per_cycle", [ + Metric( + "ldst_ret_stores_per_cycle_1", + "Store instructions retiring in 1 cycle as a percentage of a= ll " + "unhalted cycles.", d_ratio(st_v1, ldst_cyc), "100%"), + Metric( + "ldst_ret_stores_per_cycle_2", + "Store instructions retiring in 2 cycles as a percentage of = all " + "unhalted cycles.", d_ratio(st_v2, ldst_cyc), "100%"), + Metric( + "ldst_ret_stores_per_cycle_3", + "Store instructions retiring in 3 or more cycles as a percen= tage" + "of all unhalted cycles.", d_ratio(st_v3, ldst_cyc), "100%"), + ]), + MetricGroup("ldst_insn_bt", [ + Metric("ldst_insn_bt_ld", "Number of instructions between loads.= ", + d_ratio(ins, ldst_ld), "insns"), + Metric("ldst_insn_bt_st", "Number of instructions between stores= .", + d_ratio(ins, ldst_st), "insns"), + ]) + ], description=3D"Breakdown of load/store instructions") + + def AmdHwpf(): """Returns a MetricGroup representing AMD hardware prefetch metrics.""" global _zen_model @@ -512,6 +586,7 @@ def main() -> None: AmdBr(), AmdDtlb(), AmdItlb(), + AmdLdSt(), AmdHwpf(), AmdSwpf(), AmdUpc(), --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 22:34:04 2024 Received: from mail-yw1-f201.google.com (mail-yw1-f201.google.com [209.85.128.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE310185925 for ; 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Thu, 26 Sep 2024 10:41:34 -0700 (PDT) Date: Thu, 26 Sep 2024 10:41:00 -0700 In-Reply-To: <20240926174101.406874-1-irogers@google.com> Message-Id: <20240926174101.406874-12-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240926174101.406874-1-irogers@google.com> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog Subject: [PATCH v4 11/12] perf jevents: Add ILP metrics for AMD From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , John Garry , Jing Zhang , Sandipan Das , Benjamin Gray , Xu Yang , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use the counter mask (cmask) to see how many cycles an instruction takes to retire. Present as a set of ILP metrics. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/amd_metrics.py | 30 ++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/tools/perf/pmu-events/amd_metrics.py b/tools/perf/pmu-events/a= md_metrics.py index 3f77d1bbf1c9..157fa4fa3d62 100755 --- a/tools/perf/pmu-events/amd_metrics.py +++ b/tools/perf/pmu-events/amd_metrics.py @@ -120,6 +120,35 @@ def AmdBr(): description=3D"breakdown of retired branch instructio= ns") =20 =20 +def AmdIlp() -> MetricGroup: + tsc =3D Event("msr/tsc/") + c0 =3D Event("msr/mperf/") + low =3D tsc - c0 + inst_ret =3D Event("ex_ret_instr") + inst_ret_c =3D [Event(f"{inst_ret.name}/cmask=3D{x}/") for x in range(= 1, 6)] + ilp =3D [d_ratio(max(inst_ret_c[x] - inst_ret_c[x + 1], 0), cycles) fo= r x in range(0, 4)] + ilp.append(d_ratio(inst_ret_c[4], cycles)) + ilp0 =3D 1 + for x in ilp: + ilp0 -=3D x + return MetricGroup("ilp", [ + Metric("ilp_idle", "Lower power cycles as a percentage of all cycl= es", + d_ratio(low, tsc), "100%"), + Metric("ilp_inst_ret_0", "Instructions retired in 0 cycles as a pe= rcentage of all cycles", + ilp0, "100%"), + Metric("ilp_inst_ret_1", "Instructions retired in 1 cycles as a pe= rcentage of all cycles", + ilp[0], "100%"), + Metric("ilp_inst_ret_2", "Instructions retired in 2 cycles as a pe= rcentage of all cycles", + ilp[1], "100%"), + Metric("ilp_inst_ret_3", "Instructions retired in 3 cycles as a pe= rcentage of all cycles", + ilp[2], "100%"), + Metric("ilp_inst_ret_4", "Instructions retired in 4 cycles as a pe= rcentage of all cycles", + ilp[3], "100%"), + Metric("ilp_inst_ret_5", "Instructions retired in 5 or more cycles= as a percentage of all cycles", + ilp[4], "100%"), + ]) + + def AmdDtlb() -> Optional[MetricGroup]: global _zen_model if _zen_model >=3D 4: @@ -584,6 +613,7 @@ def main() -> None: =20 all_metrics =3D MetricGroup("", [ AmdBr(), + AmdIlp(), AmdDtlb(), AmdItlb(), AmdLdSt(), --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 22:34:04 2024 Received: from mail-yb1-f202.google.com (mail-yb1-f202.google.com [209.85.219.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 61CCA185B63 for ; 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Thu, 26 Sep 2024 10:41:37 -0700 (PDT) Date: Thu, 26 Sep 2024 10:41:01 -0700 In-Reply-To: <20240926174101.406874-1-irogers@google.com> Message-Id: <20240926174101.406874-13-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240926174101.406874-1-irogers@google.com> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog Subject: [PATCH v4 12/12] perf jevents: Add context switch metrics for AMD From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , John Garry , Jing Zhang , Sandipan Das , Benjamin Gray , Xu Yang , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Metrics break down context switches for different kinds of instruction. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/amd_metrics.py | 32 ++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/tools/perf/pmu-events/amd_metrics.py b/tools/perf/pmu-events/a= md_metrics.py index 157fa4fa3d62..422b119553ff 100755 --- a/tools/perf/pmu-events/amd_metrics.py +++ b/tools/perf/pmu-events/amd_metrics.py @@ -120,6 +120,37 @@ def AmdBr(): description=3D"breakdown of retired branch instructio= ns") =20 =20 +def AmdCtxSw() -> MetricGroup: + cs =3D Event("context\-switches") + metrics =3D [ + Metric("cs_rate", "Context switches per second", d_ratio(cs, interva= l_sec), "ctxsw/s") + ] + + ev =3D Event("instructions") + metrics.append(Metric("cs_instr", "Instructions per context switch", + d_ratio(ev, cs), "instr/cs")) + + ev =3D Event("cycles") + metrics.append(Metric("cs_cycles", "Cycles per context switch", + d_ratio(ev, cs), "cycles/cs")) + + ev =3D Event("ls_dispatch.ld_dispatch") + metrics.append(Metric("cs_loads", "Loads per context switch", + d_ratio(ev, cs), "loads/cs")) + + ev =3D Event("ls_dispatch.store_dispatch") + metrics.append(Metric("cs_stores", "Stores per context switch", + d_ratio(ev, cs), "stores/cs")) + + ev =3D Event("ex_ret_brn_tkn") + metrics.append(Metric("cs_br_taken", "Branches taken per context switch", + d_ratio(ev, cs), "br_taken/cs")) + + return MetricGroup("cs", metrics, + description =3D ("Number of context switches per seco= nd, instructions " + "retired & core cycles between context= switches")) + + def AmdIlp() -> MetricGroup: tsc =3D Event("msr/tsc/") c0 =3D Event("msr/mperf/") @@ -613,6 +644,7 @@ def main() -> None: =20 all_metrics =3D MetricGroup("", [ AmdBr(), + AmdCtxSw(), AmdIlp(), AmdDtlb(), AmdItlb(), --=20 2.46.1.824.gd892dcdcdd-goog