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charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20240926145343epcas5p2bef73ed8d3e36e95c05bd8d96a2e5de8 References: <20240926145132.1763-1-v.pavani@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Fix checkpatch errors from clock drivers. ERROR: space prohibited before that ',' ERROR: space required after that ',' Signed-off-by: Varada Pavani --- drivers/clk/samsung/clk-exynos3250.c | 2 +- drivers/clk/samsung/clk-exynos5260.c | 4 ++-- drivers/clk/samsung/clk-exynos5420.c | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk= -exynos3250.c index cd4fec323a42..aec4d18c1f9e 100644 --- a/drivers/clk/samsung/clk-exynos3250.c +++ b/drivers/clk/samsung/clk-exynos3250.c @@ -260,7 +260,7 @@ static const struct samsung_mux_clock mux_clks[] __init= const =3D { =20 /* SRC_TOP0 */ MUX(CLK_MOUT_EBI, "mout_ebi", mout_ebi_p, SRC_TOP0, 28, 1), - MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_div_mpll_pre_p,SRC_TOP0, 24= , 1), + MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_div_mpll_pre_p, SRC_TOP0, 2= 4, 1), MUX(CLK_MOUT_ACLK_160, "mout_aclk_160", group_div_mpll_pre_p, SRC_TOP0, 2= 0, 1), MUX(CLK_MOUT_ACLK_100, "mout_aclk_100", group_div_mpll_pre_p, SRC_TOP0, 1= 6, 1), MUX(CLK_MOUT_ACLK_266_1, "mout_aclk_266_1", mout_aclk_266_1_p, SRC_TOP0, = 14, 1), diff --git a/drivers/clk/samsung/clk-exynos5260.c b/drivers/clk/samsung/clk= -exynos5260.c index 16da6ef5ca0c..fd0520d204dc 100644 --- a/drivers/clk/samsung/clk-exynos5260.c +++ b/drivers/clk/samsung/clk-exynos5260.c @@ -1458,7 +1458,7 @@ static const struct samsung_fixed_rate_clock fixed_ra= te_clks[] __initconst =3D { FRATE(PHYCLK_HDMI_LINK_O_TMDS_CLKHI, "phyclk_hdmi_link_o_tmds_clkhi", NULL, 0, 125000000), FRATE(PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS, - "phyclk_mipi_dphy_4l_m_txbyte_clkhs" , NULL, + "phyclk_mipi_dphy_4l_m_txbyte_clkhs", NULL, 0, 187500000), FRATE(PHYCLK_DPTX_PHY_O_REF_CLK_24M, "phyclk_dptx_phy_o_ref_clk_24m", NULL, 0, 24000000), @@ -1629,7 +1629,7 @@ static const struct samsung_mux_clock top_mux_clks[] = __initconst =3D { mout_isp1_media_400_p, MUX_SEL_TOP_ISP10, 4, 1), MUX(TOP_MOUT_ACLK_ISP1_400, "mout_aclk_isp1_400", mout_aclk_isp1_400_p, - MUX_SEL_TOP_ISP10, 8 , 1), + MUX_SEL_TOP_ISP10, 8, 1), MUX(TOP_MOUT_ISP1_MEDIA_266, "mout_isp1_media_266", mout_isp1_media_266_p, MUX_SEL_TOP_ISP10, 16, 1), diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk= -exynos5420.c index a4864ea0d0d2..333c52fda17f 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -295,8 +295,8 @@ static const struct samsung_clk_reg_dump exynos5420_set= _clksrc[] =3D { /* list of all parent clocks */ PNAME(mout_mspll_cpu_p) =3D {"mout_sclk_cpll", "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll"}; -PNAME(mout_cpu_p) =3D {"mout_apll" , "mout_mspll_cpu"}; -PNAME(mout_kfc_p) =3D {"mout_kpll" , "mout_mspll_kfc"}; +PNAME(mout_cpu_p) =3D {"mout_apll", "mout_mspll_cpu"}; +PNAME(mout_kfc_p) =3D {"mout_kpll", "mout_mspll_kfc"}; PNAME(mout_apll_p) =3D {"fin_pll", "fout_apll"}; PNAME(mout_bpll_p) =3D {"fin_pll", "fout_bpll"}; PNAME(mout_cpll_p) =3D {"fin_pll", "fout_cpll"}; --=20 2.17.1