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Wysocki" Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, NXP S32 Linux Team , Christophe Lizzi , Alberto Ruiz , Enric Balletbo , Andrei Stefanescu , Krzysztof Kozlowski Subject: [PATCH v4 1/4] drivers: provide devm_platform_get_and_ioremap_resource_byname() Date: Thu, 26 Sep 2024 17:31:18 +0300 Message-ID: <20240926143122.1385658-2-andrei.stefanescu@oss.nxp.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240926143122.1385658-1-andrei.stefanescu@oss.nxp.com> References: <20240926143122.1385658-1-andrei.stefanescu@oss.nxp.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: AM0PR02CA0101.eurprd02.prod.outlook.com (2603:10a6:208:154::42) To AM9PR04MB8487.eurprd04.prod.outlook.com (2603:10a6:20b:41a::6) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM9PR04MB8487:EE_|GV1PR04MB10485:EE_ X-MS-Office365-Filtering-Correlation-Id: b47601cf-143f-4d45-3fa9-08dcde37f4e7 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|7416014|1800799024|376014|52116014|38350700014; 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charset="utf-8" Similar to commit 890cc39a879906b63912482dfc41944579df2dc6 ("drivers: provide devm_platform_get_and_ioremap_resource()") add a wrapper for "platform_get_resource_byname" and "devm_ioremap_resource". This new wrapper also returns the resource, if any, via a pointer. Suggested-by: Krzysztof Kozlowski Reviewed-by: Matthias Brugger Signed-off-by: Andrei Stefanescu --- drivers/base/platform.c | 27 +++++++++++++++++++++++++++ include/linux/platform_device.h | 13 +++++++++++++ 2 files changed, 40 insertions(+) diff --git a/drivers/base/platform.c b/drivers/base/platform.c index 4c3ee6521ba5..da6827f9462a 100644 --- a/drivers/base/platform.c +++ b/drivers/base/platform.c @@ -108,6 +108,33 @@ devm_platform_get_and_ioremap_resource(struct platform= _device *pdev, } EXPORT_SYMBOL_GPL(devm_platform_get_and_ioremap_resource); =20 +/** + * devm_platform_get_and_ioremap_resource_byname - call devm_ioremap_resou= rce() + * for a platform device and get + * a resource by its name + * + * @pdev: platform device to use both for memory resource lookup as well as + * resource management + * @name: resource name + * @res: optional output parameter to store a pointer to the obtained reso= urce. + * + * Return: a pointer to the remapped memory or an ERR_PTR() encoded error = code + * on failure. + */ +void __iomem * +devm_platform_get_and_ioremap_resource_byname(struct platform_device *pdev, + const char *name, + struct resource **res) +{ + struct resource *r; + + r =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, name); + if (res) + *res =3D r; + return devm_ioremap_resource(&pdev->dev, r); +} +EXPORT_SYMBOL_GPL(devm_platform_get_and_ioremap_resource_byname); + /** * devm_platform_ioremap_resource - call devm_ioremap_resource() for a pla= tform * device diff --git a/include/linux/platform_device.h b/include/linux/platform_devic= e.h index d422db6eec63..ab7f33f3c426 100644 --- a/include/linux/platform_device.h +++ b/include/linux/platform_device.h @@ -68,6 +68,12 @@ platform_find_device_by_driver(struct device *start, extern void __iomem * devm_platform_get_and_ioremap_resource(struct platform_device *pdev, unsigned int index, struct resource **res); + +extern void __iomem * +devm_platform_get_and_ioremap_resource_byname(struct platform_device *pdev, + const char *name, + struct resource **res); + extern void __iomem * devm_platform_ioremap_resource(struct platform_device *pdev, unsigned int index); @@ -83,6 +89,13 @@ devm_platform_get_and_ioremap_resource(struct platform_d= evice *pdev, return ERR_PTR(-EINVAL); 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charset="utf-8" Add support for the GPIO driver of the NXP S32G2/S32G3 SoCs. Signed-off-by: Phu Luu An Signed-off-by: Larisa Grigore Signed-off-by: Ghennadi Procopciuc Signed-off-by: Andrei Stefanescu --- .../bindings/gpio/nxp,s32g2-siul2-gpio.yaml | 110 ++++++++++++++++++ 1 file changed, 110 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/nxp,s32g2-siul2-= gpio.yaml diff --git a/Documentation/devicetree/bindings/gpio/nxp,s32g2-siul2-gpio.ya= ml b/Documentation/devicetree/bindings/gpio/nxp,s32g2-siul2-gpio.yaml new file mode 100644 index 000000000000..4556505ee9c9 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/nxp,s32g2-siul2-gpio.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +# Copyright 2024 NXP +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/nxp,s32g2-siul2-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP S32G2 SIUL2 GPIO controller + +maintainers: + - Ghennadi Procopciuc + - Larisa Grigore + - Andrei Stefanescu + +description: + Support for the SIUL2 GPIOs found on the S32G2 and S32G3 + chips. It includes an IRQ controller for all pins which have + an EIRQ associated. + +properties: + compatible: + oneOf: + - const: nxp,s32g2-siul2-gpio + - items: + - const: nxp,s32g3-siul2-gpio + - const: nxp,s32g2-siul2-gpio + + reg: + items: + - description: PGPDO (output value) registers for SIUL2_0 + - description: PGPDO (output value) registers for SIUL2_1 + - description: PGPDI (input value) registers for SIUL2_0 + - description: PGPDI (input value) registers for SIUL2_1 + - description: EIRQ (interrupt) configuration registers from SIUL2_1 + - description: EIRQ IMCR registers for interrupt muxing between pads + + reg-names: + items: + - const: opads0 + - const: opads1 + - const: ipads0 + - const: ipads1 + - const: eirqs + - const: eirq-imcrs + + gpio-controller: true + + '#gpio-cells': + const: 2 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + gpio-ranges: + minItems: 2 + maxItems: 2 + + gpio-reserved-ranges: + minItems: 2 + +patternProperties: + "-hog(-[0-9]+)?$": + required: + - gpio-hog + +required: + - compatible + - reg + - reg-names + - gpio-controller + - "#gpio-cells" + - gpio-ranges + - gpio-reserved-ranges + - interrupts + - interrupt-controller + - "#interrupt-cells" + +additionalProperties: false + +examples: + - | + #include + #include + + gpio@4009d700 { + compatible =3D "nxp,s32g2-siul2-gpio"; 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Thu, 26 Sep 2024 14:31:54 +0000 Received: from AM9PR04MB8487.eurprd04.prod.outlook.com ([fe80::6d7a:8d2:f020:455]) by AM9PR04MB8487.eurprd04.prod.outlook.com ([fe80::6d7a:8d2:f020:455%5]) with mapi id 15.20.7962.022; Thu, 26 Sep 2024 14:31:54 +0000 From: Andrei Stefanescu To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chester Lin , Matthias Brugger , Greg Kroah-Hartman , "Rafael J. Wysocki" Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, NXP S32 Linux Team , Christophe Lizzi , Alberto Ruiz , Enric Balletbo , Andrei Stefanescu Subject: [PATCH v4 3/4] gpio: siul2-s32g2: add NXP S32G2/S32G3 SoCs support Date: Thu, 26 Sep 2024 17:31:20 +0300 Message-ID: <20240926143122.1385658-4-andrei.stefanescu@oss.nxp.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240926143122.1385658-1-andrei.stefanescu@oss.nxp.com> References: <20240926143122.1385658-1-andrei.stefanescu@oss.nxp.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: AM0PR02CA0101.eurprd02.prod.outlook.com (2603:10a6:208:154::42) To AM9PR04MB8487.eurprd04.prod.outlook.com (2603:10a6:20b:41a::6) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM9PR04MB8487:EE_|GV1PR04MB10485:EE_ X-MS-Office365-Filtering-Correlation-Id: b0e7123e-929a-4f40-5a4f-08dcde37f79d X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|7416014|1800799024|376014|52116014|38350700014; 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This driver uses the SIUL2 (System Integration Unit Lite2) hardware module. There are two SIUL2 hardware modules present, SIUL2_0(controlling GPIOs 0-101) and SIUL2_1 for the rest. The GPIOs are not fully contiguous, there are some gaps: - GPIO102 up to GPIO111(inclusive) are invalid - GPIO123 up to GPIO143(inclusive) are invalid Some GPIOs are input only(i.e. GPI182) though this restriction is not yet enforced in code. This patch adds basic GPIO functionality(no interrupts, no suspend/resume functions). Signed-off-by: Ghennadi Procopciuc Signed-off-by: Larisa Grigore Signed-off-by: Phu Luu An Signed-off-by: Andrei Stefanescu --- drivers/gpio/Kconfig | 10 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-siul2-s32g2.c | 576 ++++++++++++++++++++++++++++++++ 3 files changed, 587 insertions(+) create mode 100644 drivers/gpio/gpio-siul2-s32g2.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index d93cd4f722b4..ae6aa6f64db3 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -643,6 +643,16 @@ config GPIO_SIOX Say yes here to support SIOX I/O devices. These are units connected via a SIOX bus and have a number of fixed-direction I/O lines. =20 +config GPIO_SIUL2_S32G2 + tristate "GPIO driver for S32G2/S32G3" + depends on ARCH_S32 || COMPILE_TEST + depends on OF_GPIO + select REGMAP_MMIO + help + This enables support for the SIUL2 GPIOs found on the S32G2/S32G3 + chips. Say yes here to enable the SIUL2 to be used as an GPIO + controller for S32G2/S32G3 platforms. + config GPIO_SNPS_CREG bool "Synopsys GPIO via CREG (Control REGisters) driver" depends on ARC || COMPILE_TEST diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 1429e8c0229b..8d5f35689fed 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -150,6 +150,7 @@ obj-$(CONFIG_GPIO_SCH) +=3D gpio-sch.o obj-$(CONFIG_GPIO_SIFIVE) +=3D gpio-sifive.o obj-$(CONFIG_GPIO_SIM) +=3D gpio-sim.o obj-$(CONFIG_GPIO_SIOX) +=3D gpio-siox.o +obj-$(CONFIG_GPIO_SIUL2_S32G2) +=3D gpio-siul2-s32g2.o obj-$(CONFIG_GPIO_SL28CPLD) +=3D gpio-sl28cpld.o obj-$(CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER) +=3D gpio-sloppy-logic-analyzer.o obj-$(CONFIG_GPIO_SODAVILLE) +=3D gpio-sodaville.o diff --git a/drivers/gpio/gpio-siul2-s32g2.c b/drivers/gpio/gpio-siul2-s32g= 2.c new file mode 100644 index 000000000000..d9c04aacb3cc --- /dev/null +++ b/drivers/gpio/gpio-siul2-s32g2.c @@ -0,0 +1,576 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * SIUL2 GPIO support. + * + * Copyright (c) 2016 Freescale Semiconductor, Inc. + * Copyright 2018-2024 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* PGPDOs are 16bit registers that come in big endian + * order if they are grouped in pairs of two. + * + * For example, the order is PGPDO1, PGPDO0, PGPDO3, PGPDO2... + */ +#define SIUL2_PGPDO(N) (((N) ^ 1) * 2) +#define S32G2_SIUL2_NUM 2 +#define S32G2_PADS_DTS_TAG_LEN 7 + +#define SIUL2_GPIO_16_PAD_SIZE 16 + +/** + * struct siul2_device_data - platform data attached to the compatible. + * @pad_access: access table for I/O pads, consists of S32G2_SIUL2_NUM tab= les. + * @reset_cnt: reset the pin name counter to zero when switching to SIUL2_= 1. + */ +struct siul2_device_data { + const struct regmap_access_table **pad_access; + const bool reset_cnt; +}; + +/** + * struct siul2_desc - describes a SIUL2 hw module. + * @pad_access: array of valid I/O pads. + * @opadmap: the regmap of the Parallel GPIO Pad Data Out Register. + * @ipadmap: the regmap of the Parallel GPIO Pad Data In Register. + * @gpio_base: the first GPIO pin. + * @gpio_num: the number of GPIO pins. + */ +struct siul2_desc { + const struct regmap_access_table *pad_access; + struct regmap *opadmap; + struct regmap *ipadmap; + u32 gpio_base; + u32 gpio_num; +}; + +/** + * struct siul2_gpio_dev - describes a group of GPIO pins. + * @platdata: the platform data. + * @siul2: SIUL2_0 and SIUL2_1 modules information. + * @pin_dir_bitmap: the bitmap with pin directions. + * @gc: the GPIO chip. + * @lock: mutual access to bitmaps. + */ +struct siul2_gpio_dev { + const struct siul2_device_data *platdata; + struct siul2_desc siul2[S32G2_SIUL2_NUM]; + unsigned long *pin_dir_bitmap; + struct gpio_chip gc; + raw_spinlock_t lock; +}; + +static const struct regmap_range s32g2_siul20_pad_yes_ranges[] =3D { + regmap_reg_range(SIUL2_PGPDO(0), SIUL2_PGPDO(0)), + regmap_reg_range(SIUL2_PGPDO(1), SIUL2_PGPDO(1)), + regmap_reg_range(SIUL2_PGPDO(2), SIUL2_PGPDO(2)), + regmap_reg_range(SIUL2_PGPDO(3), SIUL2_PGPDO(3)), + regmap_reg_range(SIUL2_PGPDO(4), SIUL2_PGPDO(4)), + regmap_reg_range(SIUL2_PGPDO(5), SIUL2_PGPDO(5)), + regmap_reg_range(SIUL2_PGPDO(6), SIUL2_PGPDO(6)), +}; + +static const struct regmap_access_table s32g2_siul20_pad_access_table =3D { + .yes_ranges =3D s32g2_siul20_pad_yes_ranges, + .n_yes_ranges =3D ARRAY_SIZE(s32g2_siul20_pad_yes_ranges), +}; + +static const struct regmap_range s32g2_siul21_pad_yes_ranges[] =3D { + regmap_reg_range(SIUL2_PGPDO(7), SIUL2_PGPDO(7)), + regmap_reg_range(SIUL2_PGPDO(9), SIUL2_PGPDO(9)), + regmap_reg_range(SIUL2_PGPDO(10), SIUL2_PGPDO(10)), + regmap_reg_range(SIUL2_PGPDO(11), SIUL2_PGPDO(11)), +}; + +static const struct regmap_access_table s32g2_siul21_pad_access_table =3D { + .yes_ranges =3D s32g2_siul21_pad_yes_ranges, + .n_yes_ranges =3D ARRAY_SIZE(s32g2_siul21_pad_yes_ranges), +}; + +static const struct regmap_access_table *s32g2_pad_access_table[] =3D { + &s32g2_siul20_pad_access_table, + &s32g2_siul21_pad_access_table +}; + +static_assert(ARRAY_SIZE(s32g2_pad_access_table) =3D=3D S32G2_SIUL2_NUM); + +static const struct siul2_device_data s32g2_device_data =3D { + .pad_access =3D s32g2_pad_access_table, + .reset_cnt =3D true, +}; + +static int siul2_get_gpio_pinspec(struct platform_device *pdev, + struct of_phandle_args *pinspec, + unsigned int range_index) +{ + struct device_node *np =3D pdev->dev.of_node; + + return of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, + range_index, pinspec); +} + +static struct regmap *siul2_offset_to_regmap(struct siul2_gpio_dev *dev, + unsigned int offset, + bool input) +{ + struct siul2_desc *siul2; + size_t i; + + for (i =3D 0; i < ARRAY_SIZE(dev->siul2); i++) { + siul2 =3D &dev->siul2[i]; + if (offset >=3D siul2->gpio_base && + offset - siul2->gpio_base < siul2->gpio_num) + return input ? siul2->ipadmap : siul2->opadmap; + } + + return NULL; +} + +static void siul2_gpio_set_direction(struct siul2_gpio_dev *dev, + unsigned int gpio, int dir) +{ + guard(raw_spinlock_irqsave)(&dev->lock); + + if (dir =3D=3D GPIO_LINE_DIRECTION_IN) + __clear_bit(gpio, dev->pin_dir_bitmap); + else + __set_bit(gpio, dev->pin_dir_bitmap); +} + +static int siul2_get_direction(struct siul2_gpio_dev *dev, + unsigned int gpio) +{ + return test_bit(gpio, dev->pin_dir_bitmap) ? GPIO_LINE_DIRECTION_OUT : + GPIO_LINE_DIRECTION_IN; +} + +static struct siul2_gpio_dev *to_siul2_gpio_dev(struct gpio_chip *chip) +{ + return container_of(chip, struct siul2_gpio_dev, gc); +} + +static int siul2_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio) +{ + struct siul2_gpio_dev *gpio_dev; + int ret =3D 0; + + ret =3D pinctrl_gpio_direction_input(chip, gpio); + if (ret) + return ret; + + gpio_dev =3D to_siul2_gpio_dev(chip); + siul2_gpio_set_direction(gpio_dev, gpio, GPIO_LINE_DIRECTION_IN); + + return 0; +} + +static int siul2_gpio_get_dir(struct gpio_chip *chip, unsigned int gpio) +{ + return siul2_get_direction(to_siul2_gpio_dev(chip), gpio); +} + +static unsigned int siul2_pin2pad(unsigned int pin) +{ + return pin / SIUL2_GPIO_16_PAD_SIZE; +} + +static u16 siul2_pin2mask(unsigned int pin) +{ + /** + * From Reference manual : + * PGPDOx[PPDOy] =3D GPDO(x =C3=97 16) + (15 - y)[PDO_(x =C3=97 16) + (15= - y)] + */ + return BIT(SIUL2_GPIO_16_PAD_SIZE - 1 - pin % SIUL2_GPIO_16_PAD_SIZE); +} + +static void siul2_gpio_set_val(struct gpio_chip *chip, unsigned int offset, + int value) +{ + struct siul2_gpio_dev *gpio_dev =3D to_siul2_gpio_dev(chip); + unsigned int pad, reg_offset; + struct regmap *regmap; + u16 mask; + + mask =3D siul2_pin2mask(offset); + pad =3D siul2_pin2pad(offset); + + reg_offset =3D SIUL2_PGPDO(pad); + regmap =3D siul2_offset_to_regmap(gpio_dev, offset, false); + if (!regmap) + return; + + value =3D value ? mask : 0; + + regmap_update_bits(regmap, reg_offset, mask, value); +} + +static int siul2_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio, + int val) +{ + struct siul2_gpio_dev *gpio_dev; + int ret =3D 0; + + gpio_dev =3D to_siul2_gpio_dev(chip); + siul2_gpio_set_val(chip, gpio, val); + + ret =3D pinctrl_gpio_direction_output(chip, gpio); + if (ret) + return ret; + + siul2_gpio_set_direction(gpio_dev, gpio, GPIO_LINE_DIRECTION_OUT); + + return 0; +} + +static void siul2_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) +{ + struct siul2_gpio_dev *gpio_dev =3D to_siul2_gpio_dev(chip); + + if (!gpio_dev) + return; + + if (siul2_get_direction(gpio_dev, offset) =3D=3D GPIO_LINE_DIRECTION_IN) + return; + + siul2_gpio_set_val(chip, offset, value); +} + +static int siul2_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct siul2_gpio_dev *gpio_dev =3D to_siul2_gpio_dev(chip); + unsigned int mask, pad, reg_offset, data =3D 0; + struct regmap *regmap; + + mask =3D siul2_pin2mask(offset); + pad =3D siul2_pin2pad(offset); + + reg_offset =3D SIUL2_PGPDO(pad); + regmap =3D siul2_offset_to_regmap(gpio_dev, offset, true); + if (!regmap) + return -EINVAL; + + regmap_read(regmap, reg_offset, &data); + + return !!(data & mask); +} + +static const struct regmap_config siul2_regmap_conf =3D { + .val_bits =3D 32, + .reg_bits =3D 32, + .reg_stride =3D 4, + .cache_type =3D REGCACHE_FLAT, +}; + +static struct regmap *common_regmap_init(struct platform_device *pdev, + struct regmap_config *conf, + const char *name) +{ + struct device *dev =3D &pdev->dev; + struct resource *res; + resource_size_t size; + void __iomem *base; + + base =3D devm_platform_get_and_ioremap_resource_byname(pdev, name, &res); + if (IS_ERR(base)) { + dev_err(&pdev->dev, "Failed to get MEM resource: %s\n", name); + return ERR_PTR(-EINVAL); + } + + size =3D resource_size(res); + conf->val_bits =3D conf->reg_stride * 8; + conf->max_register =3D size - conf->reg_stride; + conf->name =3D name; + conf->use_raw_spinlock =3D true; + + if (conf->cache_type !=3D REGCACHE_NONE) + conf->num_reg_defaults_raw =3D do_div(size, conf->reg_stride); + + return devm_regmap_init_mmio(dev, base, conf); +} + +static bool not_writable(__always_unused struct device *dev, + __always_unused unsigned int reg) +{ + return false; +} + +static struct regmap *init_padregmap(struct platform_device *pdev, + struct siul2_gpio_dev *gpio_dev, + int selector, bool input) +{ + const struct siul2_device_data *platdata =3D gpio_dev->platdata; + struct regmap_config regmap_conf =3D siul2_regmap_conf; + char dts_tag[S32G2_PADS_DTS_TAG_LEN]; + int err; + + regmap_conf.reg_stride =3D 2; + + if (selector !=3D 0 && selector !=3D 1) + return ERR_PTR(-EINVAL); + + regmap_conf.rd_table =3D platdata->pad_access[selector]; + + err =3D snprintf(dts_tag, ARRAY_SIZE(dts_tag), "%cpads%d", + input ? 'i' : 'o', selector); + if (err < 0) + return ERR_PTR(-EINVAL); + + if (input) { + regmap_conf.writeable_reg =3D not_writable; + regmap_conf.cache_type =3D REGCACHE_NONE; + } else { + regmap_conf.wr_table =3D platdata->pad_access[selector]; + } + + return common_regmap_init(pdev, ®map_conf, dts_tag); +} + +static int siul2_gpio_pads_init(struct platform_device *pdev, + struct siul2_gpio_dev *gpio_dev) +{ + struct device *dev =3D &pdev->dev; + size_t i; + + for (i =3D 0; i < ARRAY_SIZE(gpio_dev->siul2); i++) { + gpio_dev->siul2[i].opadmap =3D init_padregmap(pdev, gpio_dev, i, + false); + if (IS_ERR(gpio_dev->siul2[i].opadmap)) { + dev_err(dev, + "Failed to initialize opad2%zu regmap config\n", + i); + return PTR_ERR(gpio_dev->siul2[i].opadmap); + } + + gpio_dev->siul2[i].ipadmap =3D init_padregmap(pdev, gpio_dev, i, + true); + if (IS_ERR(gpio_dev->siul2[i].ipadmap)) { + dev_err(dev, + "Failed to initialize ipad2%zu regmap config\n", + i); + return PTR_ERR(gpio_dev->siul2[i].ipadmap); + } + } + + return 0; +} + +static int siul2_gen_names(struct device *dev, unsigned int cnt, char **na= mes, + char *ch_index, unsigned int *num_index) +{ + unsigned int i; + + for (i =3D 0; i < cnt; i++) { + if (i !=3D 0 && !(*num_index % 16)) + (*ch_index)++; + + names[i] =3D devm_kasprintf(dev, GFP_KERNEL, "P%c_%02d", + *ch_index, 0xFU & (*num_index)++); + if (!names[i]) + return -ENOMEM; + } + + return 0; +} + +static int siul2_gpio_remove_reserved_names(struct device *dev, + struct siul2_gpio_dev *gpio_dev, + char **names) +{ + struct device_node *np =3D dev->of_node; + int num_ranges, i, j, ret; + u32 base_gpio, num_gpio; + + /* Parse the gpio-reserved-ranges to know which GPIOs to exclude. */ + + num_ranges =3D of_property_count_u32_elems(dev->of_node, + "gpio-reserved-ranges"); + + /* The "gpio-reserved-ranges" is optional. */ + if (num_ranges < 0) + return 0; + num_ranges /=3D 2; + + for (i =3D 0; i < num_ranges; i++) { + ret =3D of_property_read_u32_index(np, "gpio-reserved-ranges", + i * 2, &base_gpio); + if (ret) { + dev_err(dev, "Could not parse the start GPIO: %d\n", + ret); + return ret; + } + + ret =3D of_property_read_u32_index(np, "gpio-reserved-ranges", + i * 2 + 1, &num_gpio); + if (ret) { + dev_err(dev, "Could not parse num. GPIOs: %d\n", ret); + return ret; + } + + if (base_gpio + num_gpio > gpio_dev->gc.ngpio) { + dev_err(dev, "Reserved GPIOs outside of GPIO range\n"); + return -EINVAL; + } + + /* Remove names set for reserved GPIOs. */ + for (j =3D base_gpio; j < base_gpio + num_gpio; j++) { + devm_kfree(dev, names[j]); + names[j] =3D NULL; + } + } + + return 0; +} + +static int siul2_gpio_populate_names(struct device *dev, + struct siul2_gpio_dev *gpio_dev) +{ + unsigned int num_index =3D 0; + char ch_index =3D 'A'; + char **names; + int i, ret; + + names =3D devm_kcalloc(dev, gpio_dev->gc.ngpio, sizeof(*names), + GFP_KERNEL); + if (!names) + return -ENOMEM; + + for (i =3D 0; i < S32G2_SIUL2_NUM; i++) { + ret =3D siul2_gen_names(dev, gpio_dev->siul2[i].gpio_num, + names + gpio_dev->siul2[i].gpio_base, + &ch_index, &num_index); + if (ret) { + dev_err(dev, "Could not set names for SIUL2_%d GPIOs\n", + i); + return ret; + } + + if (gpio_dev->platdata->reset_cnt) + num_index =3D 0; + + ch_index++; + } + + ret =3D siul2_gpio_remove_reserved_names(dev, gpio_dev, names); + if (ret) + return ret; + + gpio_dev->gc.names =3D (const char *const *)names; + + return 0; +} + +static int siul2_gpio_probe(struct platform_device *pdev) +{ + struct siul2_gpio_dev *gpio_dev; + struct device *dev =3D &pdev->dev; + struct of_phandle_args pinspec; + size_t i, bitmap_size; + struct gpio_chip *gc; + int ret =3D 0; + + gpio_dev =3D devm_kzalloc(dev, sizeof(*gpio_dev), GFP_KERNEL); + if (!gpio_dev) + return -ENOMEM; + + gpio_dev->platdata =3D &s32g2_device_data; + + for (i =3D 0; i < S32G2_SIUL2_NUM; i++) + gpio_dev->siul2[i].pad_access =3D + gpio_dev->platdata->pad_access[i]; + + ret =3D siul2_gpio_pads_init(pdev, gpio_dev); + if (ret) + return ret; + + gc =3D &gpio_dev->gc; + + platform_set_drvdata(pdev, gpio_dev); + + raw_spin_lock_init(&gpio_dev->lock); + + for (i =3D 0; i < ARRAY_SIZE(gpio_dev->siul2); i++) { + ret =3D siul2_get_gpio_pinspec(pdev, &pinspec, i); + if (ret) { + dev_err(dev, + "unable to get pinspec %zu from device tree\n", + i); + return -EINVAL; + } + + of_node_put(pinspec.np); + + if (pinspec.args_count !=3D 3) { + dev_err(dev, "Invalid pinspec count: %d\n", + pinspec.args_count); + return -EINVAL; + } + + gpio_dev->siul2[i].gpio_base =3D pinspec.args[1]; + gpio_dev->siul2[i].gpio_num =3D pinspec.args[2]; + } + + gc->base =3D -1; + + /* In some cases, there is a gap between the SIUL GPIOs. */ + gc->ngpio =3D gpio_dev->siul2[S32G2_SIUL2_NUM - 1].gpio_base + + gpio_dev->siul2[S32G2_SIUL2_NUM - 1].gpio_num; + + ret =3D siul2_gpio_populate_names(&pdev->dev, gpio_dev); + if (ret) + return ret; + + bitmap_size =3D BITS_TO_LONGS(gc->ngpio) * + sizeof(*gpio_dev->pin_dir_bitmap); + gpio_dev->pin_dir_bitmap =3D devm_kzalloc(dev, bitmap_size, GFP_KERNEL); + if (!gpio_dev->pin_dir_bitmap) + return -ENOMEM; + + gc->parent =3D dev; + gc->label =3D dev_name(dev); + + gc->set =3D siul2_gpio_set; + gc->get =3D siul2_gpio_get; + gc->set_config =3D gpiochip_generic_config; + gc->request =3D gpiochip_generic_request; + gc->free =3D gpiochip_generic_free; + gc->direction_output =3D siul2_gpio_dir_out; + gc->direction_input =3D siul2_gpio_dir_in; + gc->get_direction =3D siul2_gpio_get_dir; + gc->owner =3D THIS_MODULE; + + ret =3D devm_gpiochip_add_data(dev, gc, gpio_dev); + if (ret) + return dev_err_probe(dev, ret, "unable to add gpiochip\n"); + + return 0; +} + +static const struct of_device_id siul2_gpio_dt_ids[] =3D { + { .compatible =3D "nxp,s32g2-siul2-gpio" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, siul2_gpio_dt_ids); + +static struct platform_driver siul2_gpio_driver =3D { + .driver =3D { + .name =3D "s32g2-siul2-gpio", + .of_match_table =3D siul2_gpio_dt_ids, + }, + .probe =3D siul2_gpio_probe, +}; + +module_platform_driver(siul2_gpio_driver); + +MODULE_AUTHOR("NXP"); +MODULE_DESCRIPTION("NXP SIUL2 GPIO"); +MODULE_LICENSE("GPL"); --=20 2.45.2 From nobody Thu Nov 28 22:38:23 2024 Received: from EUR02-DB5-obe.outbound.protection.outlook.com (mail-db5eur02on2083.outbound.protection.outlook.com [40.107.249.83]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F5A51531C2; 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charset="utf-8" Add myself as a maintainer for the S32G2 SIUL2 GPIO driver and the NXP S32 mailing list for reviews. Signed-off-by: Andrei Stefanescu --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 7bfef98226d9..1201f284b0b5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2763,7 +2763,9 @@ R: Ghennadi Procopciuc L: NXP S32 Linux Team L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained +F: Documentation/devicetree/bindings/gpio/nxp,s32g2-siul2-gpio.yaml F: arch/arm64/boot/dts/freescale/s32g*.dts* +F: drivers/gpio/gpio-siul2-s32g2.c F: drivers/pinctrl/nxp/ =20 ARM/Orion SoC/Technologic Systems TS-78xx platform support --=20 2.45.2