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[211.75.127.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20af17e2db1sm39450795ad.178.2024.09.26.07.25.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Sep 2024 07:25:17 -0700 (PDT) Received: from hqs-appsw-a2o.mp600.macronix.com (linux-patcher [172.17.236.67]) by twhmp6px (Postfix) with ESMTPS id 44A7A80529; Thu, 26 Sep 2024 22:33:05 +0800 (CST) From: AlvinZhou To: linux-mtd@lists.infradead.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, tudor.ambarus@linaro.org, pratyush@kernel.org, mwalle@kernel.org, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, broonie@kernel.org Cc: chengminglin@mxic.com.tw, leoyu@mxic.com.tw, AlvinZhou , JaimeLiao Subject: [PATCH v10 5/6] spi: mxic: Add support for swapping byte Date: Thu, 26 Sep 2024 22:19:55 +0800 Message-Id: <20240926141956.2386374-6-alvinzhou.tw@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240926141956.2386374-1-alvinzhou.tw@gmail.com> References: <20240926141956.2386374-1-alvinzhou.tw@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: AlvinZhou Some SPI-NOR flash swap the bytes on a 16-bit boundary when configured in Octal DTR mode. It means data format D0 D1 D2 D3 would be swapped to D1 D0 D3 D2. So that whether controller support swapping bytes should be checked before enable Octal DTR mode. Add swap byte support on a 16-bit boundary when configured in Octal DTR mode for Macronix xSPI host controller driver. According dtr_swab in operation to enable/disable Macronix xSPI host controller swap byte feature. To make sure swap byte feature is working well, program data in 1S-1S-1S mode then read back and compare read data in 8D-8D-8D mode. This feature have been validated on byte-swap flash and non-byte-swap flash. Macronix xSPI host controller bit "HC_CFG_DATA_PASS" determine the byte swap feature disabled/enabled and swap byte feature is working on 8D-8D-8D mode only. Suggested-by: Michael Walle Signed-off-by: JaimeLiao Signed-off-by: AlvinZhou Acked-by: Mark Brown --- drivers/spi/spi-mxic.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c index 6156d691630a..a669ffa27b65 100644 --- a/drivers/spi/spi-mxic.c +++ b/drivers/spi/spi-mxic.c @@ -294,7 +294,8 @@ static void mxic_spi_hw_init(struct mxic_spi *mxic) mxic->regs + HC_CFG); } =20 -static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi, u32 flags) +static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi, u32 flags, + bool swap16) { int nio =3D 1; =20 @@ -305,6 +306,11 @@ static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi= , u32 flags) else if (spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL)) nio =3D 2; =20 + if (swap16) + flags &=3D ~HC_CFG_DATA_PASS; + else + flags |=3D HC_CFG_DATA_PASS; + return flags | HC_CFG_NIO(nio) | HC_CFG_TYPE(spi_get_chipselect(spi, 0), HC_CFG_TYPE_SPI_NOR) | HC_CFG_SLV_ACT(spi_get_chipselect(spi, 0)) | HC_CFG_IDLE_SIO_LVL(1= ); @@ -397,7 +403,8 @@ static ssize_t mxic_spi_mem_dirmap_read(struct spi_mem_= dirmap_desc *desc, if (WARN_ON(offs + desc->info.offset + len > U32_MAX)) return -EINVAL; =20 - writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0), mxic->regs + HC_CFG); + writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0, desc->info.op_tmpl.data.sw= ap16), + mxic->regs + HC_CFG); =20 writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len), mxic->regs + LRD_CFG); @@ -441,7 +448,8 @@ static ssize_t mxic_spi_mem_dirmap_write(struct spi_mem= _dirmap_desc *desc, if (WARN_ON(offs + desc->info.offset + len > U32_MAX)) return -EINVAL; =20 - writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0), mxic->regs + HC_CFG); + writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0, desc->info.op_tmpl.data.sw= ap16), + mxic->regs + HC_CFG); =20 writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len), mxic->regs + LWR_CFG); @@ -518,7 +526,7 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem, if (ret) return ret; =20 - writel(mxic_spi_prep_hc_cfg(mem->spi, HC_CFG_MAN_CS_EN), + writel(mxic_spi_prep_hc_cfg(mem->spi, HC_CFG_MAN_CS_EN, op->data.swap16), mxic->regs + HC_CFG); =20 writel(HC_EN_BIT, mxic->regs + HC_EN); @@ -573,6 +581,7 @@ static const struct spi_controller_mem_ops mxic_spi_mem= _ops =3D { static const struct spi_controller_mem_caps mxic_spi_mem_caps =3D { .dtr =3D true, .ecc =3D true, + .swap16 =3D true, }; =20 static void mxic_spi_set_cs(struct spi_device *spi, bool lvl) --=20 2.25.1