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[92.42.140.82]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9392f5417csm347680966b.74.2024.09.26.06.21.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Sep 2024 06:21:55 -0700 (PDT) From: Jakob Unterwurzacher X-Google-Original-From: Jakob Unterwurzacher To: quentin.schulz@cherry.de Cc: heiko@sntech.de, jakobunt@gmail.com, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Jakob Unterwurzacher Subject: [PATCH v2] arm64: dts: rockchip: add attiny_rst_gate to Ringneck Date: Thu, 26 Sep 2024 15:20:30 +0200 Message-Id: <20240926132028.21910-1-jakob.unterwurzacher@cherry.de> X-Mailer: git-send-email 2.39.2 In-Reply-To: <69f79284-b52e-496e-a286-d7e5ce3d90ce@cherry.de> References: <69f79284-b52e-496e-a286-d7e5ce3d90ce@cherry.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Ringneck v1.4 can contain (placement option) an on-board ATtiny microcontroller instead of an STM32. In normal operation, this is transparent to the software, as both microcontrollers emulate the same ICs (amc6821 and isl1208). For flashing the ATtiny, the SWITCH_REG1 regulator of the board's PMIC is used to enable the ATtiny UPDI debug interface. If the STM32 is placed, or = if we are running on an older Ringneck revision, SWITCH_REG1 is not connected and has no effect. Add attiny-updi-gate-regulator so userspace can control it via sysfs (needs CONFIG_REGULATOR_USERSPACE_CONSUMER): echo enabled > /sys/devices/platform/attiny-updi-gate-regulator/state Signed-off-by: Jakob Unterwurzacher Tested-by: Quentin Schulz Reviewed-by: Quentin Schulz --- v2: remove vcc8-supply arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi b/arch/arm64/b= oot/dts/rockchip/px30-ringneck.dtsi index bb1aea82e666e..216a6b6a6ee74 100644 --- a/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi @@ -15,6 +15,12 @@ aliases { rtc1 =3D &rk809; }; =20 + /* allows userspace to control the gate of the ATtiny UPDI pass FET via s= ysfs */ + attiny-updi-gate-regulator { + compatible =3D "regulator-output"; + vout-supply =3D <&vg_attiny_updi>; + }; + emmc_pwrseq: emmc-pwrseq { compatible =3D "mmc-pwrseq-emmc"; pinctrl-0 =3D <&emmc_reset>; @@ -281,6 +287,11 @@ regulator-state-mem { regulator-suspend-microvolt =3D <1800000>; }; }; + + /* supplies the gate of the ATtiny UPDI pass FET */ + vg_attiny_updi: SWITCH_REG1 { + regulator-name =3D "vg_attiny_updi"; + }; }; }; }; --=20 2.39.2