From nobody Fri Nov 29 02:49:27 2024 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCDFB1AB518; Thu, 26 Sep 2024 08:35:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727339753; cv=none; b=MXBbX8h7cbYxa85EM7juV7z76qLwYxmnfRgGUwYAREmulHdRQbBaZVDB3KrrPvxdVsO7UYHX8eHNycUFnhgckOdi5DqwhBEodM/GZ8NoOgKPqoAFXQEqu98ABJTAn77yvFFAKmxKfJcTzJh0e7X9HXEyMCgW07yDUu03m3Y9Yqs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727339753; c=relaxed/simple; bh=FzZjOPw1BD3qZNC2dIsjDN3y56BlWcGXa6l+cJcylGs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=DDFAryRAK1ZDyhM3ACZDa6lUtKIlTPXukGun7eTg7GWSO6RYaPQlaiJebwzOsaXHLQzVIJsVMc2hpyOi+l1MQz41gn6TvRpIMQMinwBzALY7nOP57jAaNpaEZRnReOO8VRjYJXJt3+/+mTsJr0/2wIM/AdJPGpjK7K/340se65M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=F5vIzCt7; arc=none smtp.client-ip=198.47.23.249 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="F5vIzCt7" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 48Q8Zjwa042637; Thu, 26 Sep 2024 03:35:45 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1727339745; bh=28nm6GciXd1Z/cAECj7/YWo0gE1W8fU4bL/W7b+3Ja8=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=F5vIzCt7I1FGgSBu8XNT7M6TA0LNaqIWR36W3zYv5PnYFX3QNp8T4FkBpsWB7WDmF aH/BEE99mmGXzjDYbqqYqt1+3Q/LvxNkiLorOLqnUm+gn/1xmOArMW4q1r+X/3bAGU DnFWzgCLZBcCH8qi9wgq/PzDJDjykyLvX1Ts3oLU= Received: from DLEE111.ent.ti.com (dlee111.ent.ti.com [157.170.170.22]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 48Q8Zjlw006494 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 26 Sep 2024 03:35:45 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 26 Sep 2024 03:35:45 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 26 Sep 2024 03:35:45 -0500 Received: from [127.0.1.1] (lcpd911.dhcp.ti.com [172.24.227.226]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 48Q8ZPK7064456; Thu, 26 Sep 2024 03:35:41 -0500 From: Dhruva Gole Date: Thu, 26 Sep 2024 14:04:54 +0530 Subject: [PATCH v7 3/6] arm64: dts: ti: k3-am62p: add opp frequencies Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240926-ti-cpufreq-fixes-v5-v7-3-3c94c398fe8f@ti.com> References: <20240926-ti-cpufreq-fixes-v5-v7-0-3c94c398fe8f@ti.com> In-Reply-To: <20240926-ti-cpufreq-fixes-v5-v7-0-3c94c398fe8f@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar CC: , , , , Andrew Davis , Bryan Brattlof , Vishal Mahaveer , Kevin Hilman , Markus Schneider-Pargmann , Dhruva Gole X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727339725; l=3849; i=d-gole@ti.com; s=20240919; h=from:subject:message-id; bh=/9L7M8ngafoj6TyntikdD62vQqSW7r8Y6HKG3GFLThQ=; b=senvzoeRsbOU4dlsfUqmyX9VdfStA/QRd/QWBoP4Q0VzYU5zj91DWuECK1h6aZkiY1pePfb8v 8rKg7s9qPwEBuUgY7BFSATSBx8oFw/zP0l+oQuKEIBYKabeomtzvYO4 X-Developer-Key: i=d-gole@ti.com; a=ed25519; pk=k8NnY4RbxVqeqGsYfTHeVn4hPOHkjg7Mii0Ixs4rghM= X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea From: Bryan Brattlof One power management technique available to the Cortex-A53s is their ability to dynamically scale their frequency across the device's Operating Performance Points (OPP) The OPPs available for the Cortex-A53s on the AM62Px can vary based on the silicon variant used. The SoC variant is encoded into the WKUP_MMR0_WKUP0_CTRL_MMR0_JTAG_USER_ID register which is used to limit the OPP entries the SoC supports. A table of all these variants can be found in its data sheet[0] for the AM62Px processor family. Add the OPP table into the SoC's fdti file along with the syscon node to describe the WKUP_MMR0_WKUP0_CTRL_MMR0_JTAG_USER_ID register to detect the SoC variant. [0] https://www.ti.com/lit/ds/symlink/am62p-q1.pdf Signed-off-by: Bryan Brattlof --- .../boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi | 5 +++ arch/arm64/boot/dts/ti/k3-am62p5.dtsi | 47 ++++++++++++++++++= ++++ 2 files changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi b/arc= h/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi index 315d0092e73664416998cb34d9b9f5fa70a311c2..6f32135f00a551cfea4cc896fc0= 3147271eab9b7 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi @@ -20,6 +20,11 @@ chipid: chipid@14 { bootph-all; }; =20 + opp_efuse_table: syscon@18 { + compatible =3D "ti,am62-opp-efuse-table", "syscon"; + reg =3D <0x18 0x4>; + }; + cpsw_mac_syscon: ethernet-mac-syscon@200 { compatible =3D "ti,am62p-cpsw-mac-efuse", "syscon"; reg =3D <0x200 0x8>; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5.dtsi b/arch/arm64/boot/dts/ti= /k3-am62p5.dtsi index 41f479dca455567c91bbb3a0b75d13810ea11157..140587d02e88e9d391c41001643= ec715d41bf262 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi @@ -47,6 +47,7 @@ cpu0: cpu@0 { d-cache-line-size =3D <64>; d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; + operating-points-v2 =3D <&a53_opp_table>; clocks =3D <&k3_clks 135 0>; }; =20 @@ -62,6 +63,7 @@ cpu1: cpu@1 { d-cache-line-size =3D <64>; d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; + operating-points-v2 =3D <&a53_opp_table>; clocks =3D <&k3_clks 136 0>; }; =20 @@ -77,6 +79,7 @@ cpu2: cpu@2 { d-cache-line-size =3D <64>; d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; + operating-points-v2 =3D <&a53_opp_table>; clocks =3D <&k3_clks 137 0>; }; =20 @@ -92,10 +95,54 @@ cpu3: cpu@3 { d-cache-line-size =3D <64>; d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; + operating-points-v2 =3D <&a53_opp_table>; clocks =3D <&k3_clks 138 0>; }; }; =20 + a53_opp_table: opp-table { + compatible =3D "operating-points-v2-ti-cpu"; + opp-shared; + syscon =3D <&opp_efuse_table>; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + opp-supported-hw =3D <0x01 0x0007>; + clock-latency-ns =3D <6000000>; + }; + + opp-400000000 { + opp-hz =3D /bits/ 64 <400000000>; + opp-supported-hw =3D <0x01 0x0007>; + clock-latency-ns =3D <6000000>; + }; + + opp-600000000 { + opp-hz =3D /bits/ 64 <600000000>; + opp-supported-hw =3D <0x01 0x0007>; + clock-latency-ns =3D <6000000>; + }; + + opp-800000000 { + opp-hz =3D /bits/ 64 <800000000>; + opp-supported-hw =3D <0x01 0x0007>; + clock-latency-ns =3D <6000000>; + }; + + opp-1000000000 { + opp-hz =3D /bits/ 64 <1000000000>; + opp-supported-hw =3D <0x01 0x0006>; + clock-latency-ns =3D <6000000>; + }; + + opp-1250000000 { + opp-hz =3D /bits/ 64 <1250000000>; + opp-supported-hw =3D <0x01 0x0004>; + clock-latency-ns =3D <6000000>; + opp-suspend; + }; + }; + l2_0: l2-cache0 { compatible =3D "cache"; cache-unified; --=20 2.34.1