From nobody Fri Nov 29 01:42:09 2024 Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD5B4171088 for ; Thu, 26 Sep 2024 18:16:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727374582; cv=none; b=H6xPqL0IQy6y7TfDlOcZKu1CYljLpL5a2AWzOzYXs9/TSNZVC73Ob2+LfVCzd2+rvjXiKm6CiW7MQ5iD7rgfHkhX/3UFefTfKavKT7atI63gwpdcnRpFJuqp2bLy+nltndiahIOdLb0XN59qVORJPSuOG2EGmy4JMyFeczvPYaw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727374582; c=relaxed/simple; bh=ImRa5HZ/x4KQUqqFJmDli5ALtSNsvZRYylbSivEgxME=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nDueWmWQS3GQVGXsnKm97dgrWESDXWfY/ujQEJvx1OnhWj1RpjbYzDqcN74afLRsmiocLb2s/Ikdf+Ggy4NrxaDjHU+5kk5O88KVO/M8XpPNWPHS27Jj1sZ7/Zcf04X0VTgrU3KONOnhrPaBsp5t4olkbU5i1KxMHsTkYSd7oTU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=tenstorrent.com; spf=pass smtp.mailfrom=tenstorrent.com; dkim=pass (2048-bit key) header.d=tenstorrent.com header.i=@tenstorrent.com header.b=YXA+l92a; arc=none smtp.client-ip=209.85.214.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=tenstorrent.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tenstorrent.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tenstorrent.com header.i=@tenstorrent.com header.b="YXA+l92a" Received: by mail-pl1-f169.google.com with SMTP id d9443c01a7336-2054feabfc3so12131455ad.1 for ; Thu, 26 Sep 2024 11:16:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tenstorrent.com; s=google; t=1727374580; x=1727979380; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=wkeCrPOlIseD/aizBlxYXizOEF/56/liiT5yf4vBIaE=; b=YXA+l92a8HDEYTDJAweLZH3BTKO0M8WDMZ2L6Ev5gGfA5No5EInWmT8GdfiuFijhdM 1rI/TuDWJSDH2hjHfamrvwF7DnD5C68qawpk8wX8TLgfhD31bYapfv5SySOqj2FrDFBD OfFxXKUtruHv/aM6qBa7KKaXCFr1vBZxmDfrgEHPKZPcFTUHNedPClnHwgRByyvP4luK vU328YQqRYrVi9Gn2odsKkCoeX9MOjDc1Ee9O/opcEqByI78iRQ9k0MaoB2LQRluo6Zu 2NKVcclohv3Da+BPNhhWi1JAiFQ2gxvUKgnaR1WucoQ5ogpT4qxTUjO5xt6HoMP4UNDU V8MQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727374580; x=1727979380; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wkeCrPOlIseD/aizBlxYXizOEF/56/liiT5yf4vBIaE=; b=UMdUL53t2qjJ1oR5BuYhHSw4yjBvlf5S6A+v8svLAU905Y/dkaXNEG6IW7enjHSRid j2XcIam60gISZXaX2xD9iITDwMpNFtjdBiMBwCsVzBZzc0XQ9hrFAegyuH0VgqZ+LP9d 0C5x5sWbvxKiUlaqxFs1nf7+otVcB634yYRj2bPK+lDkNQGDWsgC5YMFO2FrbKIa+ice PVL2QlEn/zzxx6WI7ut7k1e5EmJHJkpsQZKoJD3C6ZdqNcrI4Iwz1tkv1IlkkSpNn+6/ 4X1nOscE2Voo6iHqQI62GTO/ZFKj/bFvtGPv9w6Z0iQEuB+hWpSlHCL+Xkfo9PmwChzA PLAQ== X-Forwarded-Encrypted: i=1; AJvYcCV/I+8BPsza+qg9aMyAPCcD5/NCbvNlnvt3QjBeGEmTwqT0ZE6L82fVFowkj4XhExsFsG/+HVSC4Fuk/N8=@vger.kernel.org X-Gm-Message-State: AOJu0Yx4ceBb2xRtVHOrl4GuqRC0tLe8vX8jHSmxJM9slJ8EW4OWVmDh ouj1FcRShZ7P7s3HKW9eeqs+n5EnQZcLmD1zWV7+d55qPx/k/bKupePfkV+RAOU= X-Google-Smtp-Source: AGHT+IFIkdMbL4iTLZ8Ge0B/Bj8QKJ6lxuYgKzXHGXi++Ym9a+btPTNSE4YhA8c6GtM6W4wSqRxGuA== X-Received: by 2002:a17:902:d4d0:b0:201:f6e8:637f with SMTP id d9443c01a7336-20b367ca7e1mr8264905ad.11.1727374580222; Thu, 26 Sep 2024 11:16:20 -0700 (PDT) Received: from [127.0.1.1] (71-34-69-82.ptld.qwest.net. [71.34.69.82]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20b37d5ef5dsm1454145ad.32.2024.09.26.11.16.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Sep 2024 11:16:20 -0700 (PDT) From: Drew Fustini Date: Thu, 26 Sep 2024 11:15:52 -0700 Subject: [PATCH v2 3/3] riscv: dts: thead: Add TH1520 ethernet nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240926-th1520-dwmac-v2-3-f34f28ad1dc9@tenstorrent.com> References: <20240926-th1520-dwmac-v2-0-f34f28ad1dc9@tenstorrent.com> In-Reply-To: <20240926-th1520-dwmac-v2-0-f34f28ad1dc9@tenstorrent.com> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Jisheng Zhang , Maxime Coquelin , Emil Renner Berthing , Drew Fustini , Guo Ren , Fu Wei , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Drew Fustini Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org X-Mailer: b4 0.14.1 From: Emil Renner Berthing Signed-off-by: Emil Renner Berthing [drew: change apb registers from syscon to second reg of gmac node] [drew: add phy reset delay properties for beaglev ahead] Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 91 ++++++++++++++ .../boot/dts/thead/th1520-lichee-module-4a.dtsi | 135 +++++++++++++++++= ++++ arch/riscv/boot/dts/thead/th1520.dtsi | 50 ++++++++ 3 files changed, 276 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/risc= v/boot/dts/thead/th1520-beaglev-ahead.dts index 5a5888f4eda6..ddcee6298939 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -15,6 +15,7 @@ / { compatible =3D "beagle,beaglev-ahead", "thead,th1520"; =20 aliases { + ethernet0 =3D &gmac0; gpio0 =3D &gpio0; gpio1 =3D &gpio1; gpio2 =3D &gpio2; @@ -108,6 +109,25 @@ &sdio0 { status =3D "okay"; }; =20 +&gmac0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gmac0_pins>; + phy-handle =3D <&phy0>; + phy-mode =3D "rgmii-id"; + status =3D "okay"; +}; + +&mdio0 { + phy0: ethernet-phy@1 { + reg =3D <1>; + interrupt-parent =3D <&gpio3>; + interrupts =3D <22 IRQ_TYPE_LEVEL_LOW>; + reset-gpios =3D <&gpio3 21 GPIO_ACTIVE_LOW>; + reset-delay-us =3D <10000>; + reset-post-delay-us =3D <50000>; + }; +}; + &padctrl_aosys { led_pins: led-0 { led-pins { @@ -127,6 +147,77 @@ led-pins { }; =20 &padctrl0_apsys { + gmac0_pins: gmac0-0 { + tx-pins { + pins =3D "GMAC0_TX_CLK", + "GMAC0_TXEN", + "GMAC0_TXD0", + "GMAC0_TXD1", + "GMAC0_TXD2", + "GMAC0_TXD3"; + function =3D "gmac0"; + bias-disable; + drive-strength =3D <25>; + input-disable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + + rx-pins { + pins =3D "GMAC0_RX_CLK", + "GMAC0_RXDV", + "GMAC0_RXD0", + "GMAC0_RXD1", + "GMAC0_RXD2", + "GMAC0_RXD3"; + function =3D "gmac0"; + bias-disable; + drive-strength =3D <1>; + input-enable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + + mdc-pins { + pins =3D "GMAC0_MDC"; + function =3D "gmac0"; + bias-disable; + drive-strength =3D <13>; + input-disable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + + mdio-pins { + pins =3D "GMAC0_MDIO"; + function =3D "gmac0"; + bias-disable; + drive-strength =3D <13>; + input-enable; + input-schmitt-enable; + slew-rate =3D <0>; + }; + + phy-reset-pins { + pins =3D "GMAC0_COL"; /* GPIO3_21 */ + bias-disable; + drive-strength =3D <3>; + input-disable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + + phy-interrupt-pins { + pins =3D "GMAC0_CRS"; /* GPIO3_22 */ + function =3D "gpio"; + bias-pull-up; + drive-strength =3D <1>; + input-enable; + input-schmitt-enable; + slew-rate =3D <0>; + }; + }; + uart0_pins: uart0-0 { tx-pins { pins =3D "UART0_TXD"; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/= riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi index ca84bc2039ef..d9d2e1f4dc68 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -11,6 +11,11 @@ / { model =3D "Sipeed Lichee Module 4A"; compatible =3D "sipeed,lichee-module-4a", "thead,th1520"; =20 + aliases { + ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; + }; + memory@0 { device_type =3D "memory"; reg =3D <0x0 0x00000000 0x2 0x00000000>; @@ -25,6 +30,16 @@ &osc_32k { clock-frequency =3D <32768>; }; =20 +&dmac0 { + status =3D "okay"; +}; + +&aogpio { + gpio-line-names =3D "", "", "", + "GPIO00", + "GPIO04"; +}; + &aonsys_clk { clock-frequency =3D <73728000>; }; @@ -55,6 +70,22 @@ &sdio0 { status =3D "okay"; }; =20 +&gmac0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gmac0_pins>, <&mdio0_pins>; + phy-handle =3D <&phy0>; + phy-mode =3D "rgmii-id"; + status =3D "okay"; +}; + +&gmac1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gmac1_pins>; + phy-handle =3D <&phy1>; + phy-mode =3D "rgmii-id"; + status =3D "okay"; +}; + &gpio0 { gpio-line-names =3D "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", @@ -87,3 +118,107 @@ &gpio3 { "GPIO09", "GPIO10"; }; + +&mdio0 { + phy0: ethernet-phy@1 { + reg =3D <1>; + }; + + phy1: ethernet-phy@2 { + reg =3D <2>; + }; +}; + +&padctrl0_apsys { + gmac0_pins: gmac0-0 { + tx-pins { + pins =3D "GMAC0_TX_CLK", + "GMAC0_TXEN", + "GMAC0_TXD0", + "GMAC0_TXD1", + "GMAC0_TXD2", + "GMAC0_TXD3"; + function =3D "gmac0"; + bias-disable; + drive-strength =3D <25>; + input-disable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + + rx-pins { + pins =3D "GMAC0_RX_CLK", + "GMAC0_RXDV", + "GMAC0_RXD0", + "GMAC0_RXD1", + "GMAC0_RXD2", + "GMAC0_RXD3"; + function =3D "gmac0"; + bias-disable; + drive-strength =3D <1>; + input-enable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + }; + + gmac1_pins: gmac1-0 { + tx-pins { + pins =3D "GPIO2_18", /* GMAC1_TX_CLK */ + "GPIO2_20", /* GMAC1_TXEN */ + "GPIO2_21", /* GMAC1_TXD0 */ + "GPIO2_22", /* GMAC1_TXD1 */ + "GPIO2_23", /* GMAC1_TXD2 */ + "GPIO2_24"; /* GMAC1_TXD3 */ + function =3D "gmac1"; + bias-disable; + drive-strength =3D <25>; + input-disable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + + rx-pins { + pins =3D "GPIO2_19", /* GMAC1_RX_CLK */ + "GPIO2_25", /* GMAC1_RXDV */ + "GPIO2_30", /* GMAC1_RXD0 */ + "GPIO2_31", /* GMAC1_RXD1 */ + "GPIO3_0", /* GMAC1_RXD2 */ + "GPIO3_1"; /* GMAC1_RXD3 */ + function =3D "gmac1"; + bias-disable; + drive-strength =3D <1>; + input-enable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + }; + + mdio0_pins: mdio0-0 { + mdc-pins { + pins =3D "GMAC0_MDC"; + function =3D "gmac0"; + bias-disable; + drive-strength =3D <13>; + input-disable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + + mdio-pins { + pins =3D "GMAC0_MDIO"; + function =3D "gmac0"; + bias-disable; + drive-strength =3D <13>; + input-enable; + input-schmitt-enable; + slew-rate =3D <0>; + }; + }; +}; + +&sdio0 { + bus-width =3D <4>; + max-frequency =3D <198000000>; + status =3D "okay"; +}; diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index 517a9e2e93a3..f51cc0c465ee 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -222,6 +222,12 @@ aonsys_clk: aonsys-clk { #clock-cells =3D <0>; }; =20 + stmmac_axi_config: stmmac-axi-config { + snps,wr_osr_lmt =3D <15>; + snps,rd_osr_lmt =3D <15>; + snps,blen =3D <0 0 64 32 0 0 0>; + }; + soc { compatible =3D "simple-bus"; interrupt-parent =3D <&plic>; @@ -273,6 +279,50 @@ uart0: serial@ffe7014000 { status =3D "disabled"; }; =20 + gmac1: ethernet@ffe7060000 { + compatible =3D "thead,th1520-gmac", "snps,dwmac-3.70a"; + reg =3D <0xff 0xe7060000 0x0 0x2000>, <0xff 0xec004000 0x0 0x1000>; + reg-names =3D "dwmac", "apb"; + interrupts =3D <67 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "macirq"; + clocks =3D <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC_AXI>; + clock-names =3D "stmmaceth", "pclk"; + snps,pbl =3D <32>; + snps,fixed-burst; + snps,multicast-filter-bins =3D <64>; + snps,perfect-filter-entries =3D <32>; + snps,axi-config =3D <&stmmac_axi_config>; + status =3D "disabled"; + + mdio1: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + gmac0: ethernet@ffe7070000 { + compatible =3D "thead,th1520-gmac", "snps,dwmac-3.70a"; + reg =3D <0xff 0xe7070000 0x0 0x2000>, <0xff 0xec003000 0x0 0x1000>; + reg-names =3D "dwmac", "apb"; + interrupts =3D <66 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "macirq"; + clocks =3D <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC_AXI>; + clock-names =3D "stmmaceth", "pclk"; + snps,pbl =3D <32>; + snps,fixed-burst; + snps,multicast-filter-bins =3D <64>; + snps,perfect-filter-entries =3D <32>; + snps,axi-config =3D <&stmmac_axi_config>; + status =3D "disabled"; + + mdio0: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + emmc: mmc@ffe7080000 { compatible =3D "thead,th1520-dwcmshc"; reg =3D <0xff 0xe7080000 0x0 0x10000>; --=20 2.34.1