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[212.216.221.196]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a93c297b7d6sm38862166b.162.2024.09.26.14.17.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Sep 2024 14:17:06 -0700 (PDT) From: Antonino Maniscalco Date: Thu, 26 Sep 2024 23:16:49 +0200 Subject: [PATCH v6 07/11] drm/msm/a6xx: Use posamble to reset counters on preemption Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240926-preemption-a750-t-v6-7-7b6e1ef3648f@gmail.com> References: <20240926-preemption-a750-t-v6-0-7b6e1ef3648f@gmail.com> In-Reply-To: <20240926-preemption-a750-t-v6-0-7b6e1ef3648f@gmail.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Jonathan Corbet Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Antonino Maniscalco , Akhil P Oommen , Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727385413; l=6700; i=antomani103@gmail.com; s=20240815; h=from:subject:message-id; bh=3lkRPE9IG6LdIb0AbxM5VciIHuTa1FZhL5VBzl24384=; b=jMrueTOAuigP1cmVIcs9TKlNQdh0mxPAB9AATRunmnuZu3wxIjvsNpbOygQXF3Wv9+vyw2kZw LNtWILE0Kj3Aw3g6aiixN4l31252jTdbyMNSn3h6uSEC+EpOn8s6lus X-Developer-Key: i=antomani103@gmail.com; a=ed25519; pk=0zicFb38tVla+iHRo4kWpOMsmtUrpGBEa7LkFF81lyY= Use the postamble to reset perf counters when switching between rings, except when sysprof is enabled, analogously to how they are reset between submissions when switching pagetables. Reviewed-by: Akhil P Oommen Tested-by: Neil Armstrong # on SM8650-QRD Tested-by: Neil Armstrong # on SM8550-QRD Tested-by: Neil Armstrong # on SM8450-HDK Signed-off-by: Antonino Maniscalco --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 +++++++ drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 6 ++++ drivers/gpu/drm/msm/adreno/a6xx_preempt.c | 57 +++++++++++++++++++++++++++= ++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 7 ++-- 4 files changed, 80 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 355a3e210335d60a5bed0ee287912271c353402a..736f475d696f1133c9e55d16aa8= 0e73fd46cb835 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -358,6 +358,8 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm= _gem_submit *submit) static void a6xx_emit_set_pseudo_reg(struct msm_ringbuffer *ring, struct a6xx_gpu *a6xx_gpu, struct msm_gpu_submitqueue *queue) { + u64 preempt_postamble; + OUT_PKT7(ring, CP_SET_PSEUDO_REG, 12); =20 OUT_RING(ring, SMMU_INFO); @@ -381,6 +383,16 @@ static void a6xx_emit_set_pseudo_reg(struct msm_ringbu= ffer *ring, /* seems OK to set to 0 to disable it */ OUT_RING(ring, 0); OUT_RING(ring, 0); + + /* Emit postamble to clear perfcounters */ + preempt_postamble =3D a6xx_gpu->preempt_postamble_iova; + + OUT_PKT7(ring, CP_SET_AMBLE, 3); + OUT_RING(ring, lower_32_bits(preempt_postamble)); + OUT_RING(ring, upper_32_bits(preempt_postamble)); + OUT_RING(ring, CP_SET_AMBLE_2_DWORDS( + a6xx_gpu->preempt_postamble_len) | + CP_SET_AMBLE_2_TYPE(KMD_AMBLE_TYPE)); } =20 static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.h index 7fc994121676844cc53438fb47756e7caf5eee03..ae13892c87e397f5cdea6785fb7= d5c17b7a93690 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -71,6 +71,12 @@ struct a6xx_gpu { bool uses_gmem; bool skip_save_restore; =20 + struct drm_gem_object *preempt_postamble_bo; + void *preempt_postamble_ptr; + uint64_t preempt_postamble_iova; + uint64_t preempt_postamble_len; + bool postamble_enabled; + struct a6xx_gmu gmu; =20 struct drm_gem_object *shadow_bo; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_preempt.c b/drivers/gpu/drm/ms= m/adreno/a6xx_preempt.c index 38d68b341d99e9f4c39213d968de6b1e168c9786..cf75f612edc15374f3d8238e3dc= 0297532569607 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_preempt.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_preempt.c @@ -97,6 +97,43 @@ static void a6xx_preempt_timer(struct timer_list *t) kthread_queue_work(gpu->worker, &gpu->recover_work); } =20 +static void preempt_prepare_postamble(struct a6xx_gpu *a6xx_gpu) +{ + u32 *postamble =3D a6xx_gpu->preempt_postamble_ptr; + u32 count =3D 0; + + postamble[count++] =3D PKT7(CP_REG_RMW, 3); + postamble[count++] =3D REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD; + postamble[count++] =3D 0; + postamble[count++] =3D 1; + + postamble[count++] =3D PKT7(CP_WAIT_REG_MEM, 6); + postamble[count++] =3D CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ); + postamble[count++] =3D CP_WAIT_REG_MEM_1_POLL_ADDR_LO( + REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS); + postamble[count++] =3D CP_WAIT_REG_MEM_2_POLL_ADDR_HI(0); + postamble[count++] =3D CP_WAIT_REG_MEM_3_REF(0x1); + postamble[count++] =3D CP_WAIT_REG_MEM_4_MASK(0x1); + postamble[count++] =3D CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(0); + + a6xx_gpu->preempt_postamble_len =3D count; + + a6xx_gpu->postamble_enabled =3D true; +} + +static void preempt_disable_postamble(struct a6xx_gpu *a6xx_gpu) +{ + u32 *postamble =3D a6xx_gpu->preempt_postamble_ptr; + + /* + * Disable the postamble by replacing the first packet header with a NOP + * that covers the whole buffer. + */ + *postamble =3D PKT7(CP_NOP, (a6xx_gpu->preempt_postamble_len - 1)); + + a6xx_gpu->postamble_enabled =3D false; +} + void a6xx_preempt_irq(struct msm_gpu *gpu) { uint32_t status; @@ -187,6 +224,7 @@ void a6xx_preempt_trigger(struct msm_gpu *gpu) unsigned long flags; struct msm_ringbuffer *ring; unsigned int cntl; + bool sysprof; =20 if (gpu->nr_rings =3D=3D 1) return; @@ -272,6 +310,15 @@ void a6xx_preempt_trigger(struct msm_gpu *gpu) /* Start a timer to catch a stuck preemption */ mod_timer(&a6xx_gpu->preempt_timer, jiffies + msecs_to_jiffies(10000)); =20 + /* Enable or disable postamble as needed */ + sysprof =3D refcount_read(&a6xx_gpu->base.base.sysprof_active) > 1; + + if (!sysprof && !a6xx_gpu->postamble_enabled) + preempt_prepare_postamble(a6xx_gpu); + + if (sysprof && a6xx_gpu->postamble_enabled) + preempt_disable_postamble(a6xx_gpu); + /* Set the preemption state to triggered */ set_preempt_state(a6xx_gpu, PREEMPT_TRIGGERED); =20 @@ -359,6 +406,16 @@ void a6xx_preempt_init(struct msm_gpu *gpu) a6xx_gpu->uses_gmem =3D 1; a6xx_gpu->skip_save_restore =3D 1; =20 + a6xx_gpu->preempt_postamble_ptr =3D msm_gem_kernel_new(gpu->dev, + PAGE_SIZE, MSM_BO_WC | MSM_BO_MAP_PRIV, + gpu->aspace, &a6xx_gpu->preempt_postamble_bo, + &a6xx_gpu->preempt_postamble_iova); + + preempt_prepare_postamble(a6xx_gpu); + + if (IS_ERR(a6xx_gpu->preempt_postamble_ptr)) + goto fail; + timer_setup(&a6xx_gpu->preempt_timer, a6xx_preempt_timer, 0); =20 return; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index 6b1888280a83e6288c4b071733d5d6097afe3a99..87098567483b69c21025b80f356= e0a68f0e7f172 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -610,12 +610,15 @@ OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regind= x, uint16_t cnt) OUT_RING(ring, PKT4(regindx, cnt)); } =20 +#define PKT7(opcode, cnt) \ + (CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) | \ + ((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23)) + static inline void OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt) { adreno_wait_ring(ring, cnt + 1); - OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) | - ((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23)); + OUT_RING(ring, PKT7(opcode, cnt)); } =20 struct msm_gpu *a2xx_gpu_init(struct drm_device *dev); --=20 2.46.1