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This is required for hardware like i.MX8QXP to configure the PCIe controller ATU and eliminate the need for workaround address fixups in drivers. Currently, many drivers use hardcoded CPU addresses for fixups, but this information is already described in the Device Tree. With correct hardware descriptions, such fixups can be removed. =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=90 =E2=94=8C=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=90 =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 =E2=94= =82 =E2=94=82 IA: 0x8ff0_0000 =E2=94=82 =E2=94=82 =E2=94=82 CPU =E2=94=9C=E2=94=80=E2=94=80=E2=94=80=E2=96=BA=E2=94=82 BUS = =E2=94=9C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=90 =E2=94=82 PCI =E2=94=82 =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=98 =E2=94= =82 =E2=94=82 IA: 0x8ff8_0000 =E2=94=82 =E2=94=82 =E2= =94=82 CPU Addr =E2=94=82 Fabric =E2=94=9C=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=90 =E2=94=82 =E2=94=82 Controller =E2=94=82 0x7000_0000 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 = =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 = =E2=94=82 =E2=94=82 PCI Addr =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=94= =E2=94=80=E2=94=80=E2=96=BA CfgSpace =E2=94=80=E2=94=BC=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=96=BA =E2=94=82 =E2=94=9C=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 =E2=94=82 =E2= =94=82 =E2=94=82 0 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 = =E2=94=82 =E2=94=82 =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=98 =E2=94=82 =E2=94=94=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=96=BA IOSpace =E2=94=80= =E2=94=BC=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=96=BA =E2=94=82 =E2=94=82 =E2= =94=82 0 =E2=94=82 =E2=94=82 =E2= =94=82 =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=96=BA MemSpace= =E2=94=80=E2=94=BC=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=96=BA IA: 0x8000_0000 =E2=94=82 =E2=94=82 = 0x8000_0000 =E2=94=94=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=98 bus@5f000000 { compatible =3D "simple-bus"; #address-cells =3D <1>; #size-cells =3D <1>; ranges =3D <0x5f000000 0x0 0x5f000000 0x21000000>, <0x80000000 0x0 0x70000000 0x10000000>; pcieb: pcie@5f010000 { compatible =3D "fsl,imx8q-pcie"; reg =3D <0x5f010000 0x10000>, <0x8ff00000 0x80000>; reg-names =3D "dbi", "config"; #address-cells =3D <3>; #size-cells =3D <2>; device_type =3D "pci"; bus-range =3D <0x00 0xff>; ranges =3D <0x81000000 0 0x00000000 0x8ff80000 0 0x00010000= >, <0x82000000 0 0x80000000 0x80000000 0 0x0ff00000>; ... }; }; 'cpu_untranslate_addr' in of_pci_range can indicate above diagram IA address information. Signed-off-by: Frank Li Reviewed-by: Rob Herring (Arm) --- Change from v1 to v2 - add cpu_untranslate_addr in of_pci_range, instead adding new API. --- drivers/of/address.c | 2 ++ include/linux/of_address.h | 1 + 2 files changed, 3 insertions(+) diff --git a/drivers/of/address.c b/drivers/of/address.c index 286f0c161e332..f4cb82f5313cf 100644 --- a/drivers/of/address.c +++ b/drivers/of/address.c @@ -811,6 +811,8 @@ struct of_pci_range *of_pci_range_parser_one(struct of_= pci_range_parser *parser, else range->cpu_addr =3D of_translate_address(parser->node, parser->range + na); + + range->cpu_untranslate_addr =3D of_read_number(parser->range + na, parser= ->pna); range->size =3D of_read_number(parser->range + parser->pna + na, ns); =20 parser->range +=3D np; diff --git a/include/linux/of_address.h b/include/linux/of_address.h index 26a19daf0d092..0683ce0c07f68 100644 --- a/include/linux/of_address.h +++ b/include/linux/of_address.h @@ -26,6 +26,7 @@ struct of_pci_range { u64 bus_addr; }; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240926-pci_fixup_addr-v2-2-e4524541edf4@nxp.com> References: <20240926-pci_fixup_addr-v2-0-e4524541edf4@nxp.com> In-Reply-To: <20240926-pci_fixup_addr-v2-0-e4524541edf4@nxp.com> To: Rob Herring , Saravana Kannan , Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Richard Zhu , Lucas Stach , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, Frank Li X-Mailer: b4 0.13-dev-e586c X-Developer-Signature: v=1; a=ed25519-sha256; t=1727369253; l=6330; i=Frank.Li@nxp.com; s=20240130; h=from:subject:message-id; bh=9UjixEiIWjU2Rw1R//IY4okKQq5e+4Lm/9kG3kM4QOQ=; b=q9h9KFax1bOFqYOQT9j41i+XoLB60/QqkG3o6i3uWdyqfh4+ocMXLrofzpIpfprWxamA4TAwY r+alQ/+SJAwDNmS4W3Njt7ovEv5qmQudOSNVvuxrDiFy0mDhTRtR05s X-Developer-Key: i=Frank.Li@nxp.com; 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Most system it is the same as CPU address, but some hardware like i.MX8QXP convert it to difference address by bus fabric. See below diagram: =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 =E2=94=8C=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 =E2= =94=82 =E2=94=82 IA: 0x8ff0_0000 =E2=94=82 =E2=94=82 =E2=94=82 CPU =E2=94=9C=E2=94=80=E2=94=80=E2=94=80=E2=96=BA=E2=94=82 B= US =E2=94=9C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=90 =E2=94=82 PCI =E2=94=82 =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=98 =E2= =94=82 =E2=94=82 IA: 0x8ff8_0000 =E2=94=82 =E2=94=82 = =E2=94=82 CPU Addr =E2=94=82 Fabric =E2=94=9C=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=90 =E2=94=82 =E2=94=82 Controller =E2=94=82 0x7000_0000 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94= =82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94= =82 =E2=94=82 =E2=94=82 PCI Addr =E2=94=82 =E2=94=82 =E2=94=82 =E2=94= =94=E2=94=80=E2=94=80=E2=96=BA CfgSpace =E2=94=80=E2=94=BC=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=96=BA =E2=94=82 =E2=94=9C=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 =E2=94=82 = =E2=94=82 =E2=94=82 0 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 = =E2=94=82 =E2=94=82 =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=98 =E2=94=82 =E2=94=94=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=96=BA IOSpace =E2= =94=80=E2=94=BC=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=96=BA =E2=94=82 =E2=94=82 = =E2=94=82 0 =E2=94=82 =E2=94=82 = =E2=94=82 =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=96=BA MemSp= ace =E2=94=80=E2=94=BC=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=96=BA IA: 0x8000_0000 =E2=94=82 =E2=94= =82 0x8000_0000 =E2=94=94=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=98 bus@5f000000 { compatible =3D "simple-bus"; #address-cells =3D <1>; #size-cells =3D <1>; ranges =3D <0x5f000000 0x0 0x5f000000 0x21000000>, <0x80000000 0x0 0x70000000 0x10000000>; pcie@5f010000 { compatible =3D "fsl,imx8q-pcie"; reg =3D <0x5f010000 0x10000>, <0x8ff00000 0x80000>; reg-names =3D "dbi", "config"; #address-cells =3D <3>; #size-cells =3D <2>; device_type =3D "pci"; bus-range =3D <0x00 0xff>; ranges =3D <0x81000000 0 0x00000000 0x8ff80000 0 0x00010000>, <0x82000000 0 0x80000000 0x80000000 0 0x0ff00000>; ... }; }; Term 'IA' here means the address just before PCIe controller. After ATU use this IA instead CPU address, cpu_addr_fixup() can be removed. Signed-off-by: Frank Li --- Change from v1 to v2 - update because patch1 change get untranslate address method. - add using_dtbus_info in case break back compatibility for exited platform. --- drivers/pci/controller/dwc/pcie-designware-host.c | 42 +++++++++++++++++++= ++++ drivers/pci/controller/dwc/pcie-designware.h | 8 +++++ 2 files changed, 50 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 3e41865c72904..95b927efb5e46 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -418,6 +418,34 @@ static void dw_pcie_host_request_msg_tlp_res(struct dw= _pcie_rp *pp) } } =20 +static int dw_pcie_get_untranslate_addr(struct dw_pcie *pci, resource_size= _t pci_addr, + resource_size_t *i_addr) +{ + struct device *dev =3D pci->dev; + struct device_node *np =3D dev->of_node; + struct of_range_parser parser; + struct of_range range; + int ret; + + if (!pci->using_dtbus_info) { + *i_addr =3D pci_addr; + return 0; + } + + ret =3D of_range_parser_init(&parser, np); + if (ret) + return ret; + + for_each_of_pci_range(&parser, &range) { + if (pci_addr =3D=3D range.bus_addr) { + *i_addr =3D range.cpu_untranslate_addr; + break; + } + } + + return 0; +} + int dw_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); @@ -427,6 +455,7 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) struct resource_entry *win; struct pci_host_bridge *bridge; struct resource *res; + int index; int ret; =20 raw_spin_lock_init(&pp->lock); @@ -440,6 +469,13 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) pp->cfg0_size =3D resource_size(res); pp->cfg0_base =3D res->start; =20 + if (pci->using_dtbus_info) { + index =3D of_property_match_string(np, "reg-names", "config"); + if (index < 0) + return -EINVAL; + of_property_read_reg(np, index, &pp->cfg0_base, NULL); + } + pp->va_cfg0_base =3D devm_pci_remap_cfg_resource(dev, res); if (IS_ERR(pp->va_cfg0_base)) return PTR_ERR(pp->va_cfg0_base); @@ -462,6 +498,9 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) pp->io_base =3D pci_pio_to_address(win->res->start); } =20 + if (dw_pcie_get_untranslate_addr(pci, pp->io_bus_addr, &pp->io_base)) + return -ENODEV; + /* Set default bus ops */ bridge->ops =3D &dw_pcie_ops; bridge->child_ops =3D &dw_child_pcie_ops; @@ -733,6 +772,9 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) atu.cpu_addr =3D entry->res->start; atu.pci_addr =3D entry->res->start - entry->offset; =20 + if (dw_pcie_get_untranslate_addr(pci, atu.pci_addr, &atu.cpu_addr)) + return -EINVAL; + /* Adjust iATU size if MSG TLP region was allocated before */ if (pp->msg_res && pp->msg_res->parent =3D=3D entry->res) atu.size =3D resource_size(entry->res) - diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index c189781524fb8..e22d32b5a5f19 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -464,6 +464,14 @@ struct dw_pcie { struct reset_control_bulk_data core_rsts[DW_PCIE_NUM_CORE_RSTS]; struct gpio_desc *pe_rst; bool suspended; + /* + * Use device tree 'ranges' property of bus node instead using + * cpu_addr_fixup(). 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Signed-off-by: Frank Li --- Change from v1 to v2 - set using_dtbus_info true --- drivers/pci/controller/dwc/pci-imx6.c | 22 ++-------------------- 1 file changed, 2 insertions(+), 20 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index 1e58c24137e7f..94f3411352bf0 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -82,7 +82,6 @@ enum imx_pcie_variants { #define IMX_PCIE_FLAG_HAS_PHY_RESET BIT(5) #define IMX_PCIE_FLAG_HAS_SERDES BIT(6) #define IMX_PCIE_FLAG_SUPPORT_64BIT BIT(7) -#define IMX_PCIE_FLAG_CPU_ADDR_FIXUP BIT(8) =20 #define imx_check_flag(pci, val) (pci->drvdata->flags & val) =20 @@ -1015,22 +1014,6 @@ static void imx_pcie_host_exit(struct dw_pcie_rp *pp) regulator_disable(imx_pcie->vpcie); } =20 -static u64 imx_pcie_cpu_addr_fixup(struct dw_pcie *pcie, u64 cpu_addr) -{ - struct imx_pcie *imx_pcie =3D to_imx_pcie(pcie); - struct dw_pcie_rp *pp =3D &pcie->pp; - struct resource_entry *entry; - - if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_CPU_ADDR_FIXUP)) - return cpu_addr; - - entry =3D resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM); - if (!entry) - return cpu_addr; - - return cpu_addr - entry->offset; -} - static const struct dw_pcie_host_ops imx_pcie_host_ops =3D { .init =3D imx_pcie_host_init, .deinit =3D imx_pcie_host_exit, @@ -1039,7 +1022,6 @@ static const struct dw_pcie_host_ops imx_pcie_host_op= s =3D { static const struct dw_pcie_ops dw_pcie_ops =3D { .start_link =3D imx_pcie_start_link, .stop_link =3D imx_pcie_stop_link, - .cpu_addr_fixup =3D imx_pcie_cpu_addr_fixup, }; =20 static void imx_pcie_ep_init(struct dw_pcie_ep *ep) @@ -1459,6 +1441,7 @@ static int imx_pcie_probe(struct platform_device *pde= v) if (ret) return ret; =20 + pci->using_dtbus_info =3D true; if (imx_pcie->drvdata->mode =3D=3D DW_PCIE_EP_TYPE) { ret =3D imx_add_pcie_ep(imx_pcie, pdev); if (ret < 0) @@ -1598,8 +1581,7 @@ static const struct imx_pcie_drvdata drvdata[] =3D { }, [IMX8Q] =3D { .variant =3D IMX8Q, - .flags =3D IMX_PCIE_FLAG_HAS_PHYDRV | - IMX_PCIE_FLAG_CPU_ADDR_FIXUP, + .flags =3D IMX_PCIE_FLAG_HAS_PHYDRV, .clk_names =3D imx8q_clks, .clks_cnt =3D ARRAY_SIZE(imx8q_clks), }, --=20 2.34.1