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For example, on the i.MX95 platform, a lookup table must be configured to inform the hardware how to convert pci_device_id to stream (bus master) ID, which is used by the IOMMU and MSI controller to identify bus master device. Enablement will be failure when there is not enough lookup table resource. Avoid DMA write to wrong position. That is the reason why pci_fixup_enable can't work since not return value for fixup function. Signed-off-by: Frank Li --- drivers/pci/pci.c | 19 +++++++++++++++++++ include/linux/pci.h | 2 ++ 2 files changed, 21 insertions(+) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 7d85c04fbba2a..e0f83ed53d964 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -2057,6 +2057,7 @@ static int do_pci_enable_device(struct pci_dev *dev, = int bars) { int err; struct pci_dev *bridge; + struct pci_bus *bus; u16 cmd; u8 pin; =20 @@ -2068,6 +2069,15 @@ static int do_pci_enable_device(struct pci_dev *dev,= int bars) if (bridge) pcie_aspm_powersave_config_link(bridge); =20 + bus =3D dev->bus; + while (bus) { + if (bus->ops->enable_device) + err =3D bus->ops->enable_device(bus, dev); + if (err) + return err; + bus =3D bus->parent; + } + err =3D pcibios_enable_device(dev, bars); if (err < 0) return err; @@ -2262,12 +2272,21 @@ void pci_disable_enabled_device(struct pci_dev *dev) */ void pci_disable_device(struct pci_dev *dev) { + struct pci_bus *bus; + dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <=3D 0, "disabling already-disabled device"); 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This involves examining the msi-map and smmu-map to ensure consistent mapping of PCI BDF to the same stream IDs. Subsequently, LUT-related registers are configured. In the absence of an msi-map, the built-in MSI controller is utilized as a fallback. Additionally, register a PCI bus callback function enable_device() and disable_device() to config LUT when enable a new PCI device. Signed-off-by: Frank Li --- drivers/pci/controller/dwc/pci-imx6.c | 133 ++++++++++++++++++++++++++++++= +++- 1 file changed, 132 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index 94f3411352bf0..1fe07f64d0d88 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -55,6 +55,22 @@ #define IMX95_PE0_GEN_CTRL_3 0x1058 #define IMX95_PCIE_LTSSM_EN BIT(0) =20 +#define IMX95_PE0_LUT_ACSCTRL 0x1008 +#define IMX95_PEO_LUT_RWA BIT(16) +#define IMX95_PE0_LUT_ENLOC GENMASK(4, 0) + +#define IMX95_PE0_LUT_DATA1 0x100c +#define IMX95_PE0_LUT_VLD BIT(31) +#define IMX95_PE0_LUT_DAC_ID GENMASK(10, 8) +#define IMX95_PE0_LUT_STREAM_ID GENMASK(5, 0) + +#define IMX95_PE0_LUT_DATA2 0x1010 +#define IMX95_PE0_LUT_REQID GENMASK(31, 16) +#define IMX95_PE0_LUT_MASK GENMASK(15, 0) + +#define IMX95_SID_MASK GENMASK(5, 0) +#define IMX95_MAX_LUT 32 + #define to_imx_pcie(x) dev_get_drvdata((x)->dev) =20 enum imx_pcie_variants { @@ -82,6 +98,7 @@ enum imx_pcie_variants { #define IMX_PCIE_FLAG_HAS_PHY_RESET BIT(5) #define IMX_PCIE_FLAG_HAS_SERDES BIT(6) #define IMX_PCIE_FLAG_SUPPORT_64BIT BIT(7) +#define IMX_PCIE_FLAG_HAS_LUT BIT(8) =20 #define imx_check_flag(pci, val) (pci->drvdata->flags & val) =20 @@ -134,6 +151,7 @@ struct imx_pcie { struct device *pd_pcie_phy; struct phy *phy; const struct imx_pcie_drvdata *drvdata; + struct mutex lock; }; =20 /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */ @@ -925,6 +943,111 @@ static void imx_pcie_stop_link(struct dw_pcie *pci) imx_pcie_ltssm_disable(dev); } =20 +static int imx_pcie_add_lut(struct imx_pcie *imx_pcie, u16 reqid, u8 sid) +{ + struct dw_pcie *pci =3D imx_pcie->pci; + struct device *dev =3D pci->dev; + u32 data1, data2; + int i; + + if (sid >=3D 64) { + dev_err(dev, "Invalid SID for index %d\n", sid); + return -EINVAL; + } + + guard(mutex)(&imx_pcie->lock); + + for (i =3D 0; i < IMX95_MAX_LUT; i++) { + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, IMX95_PEO_LUT_= RWA | i); + + regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, &data1); + if (data1 & IMX95_PE0_LUT_VLD) + continue; + + data1 =3D FIELD_PREP(IMX95_PE0_LUT_DAC_ID, 0); + data1 |=3D FIELD_PREP(IMX95_PE0_LUT_STREAM_ID, sid); + data1 |=3D IMX95_PE0_LUT_VLD; + + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, data1); + + data2 =3D 0xffff; + data2 |=3D FIELD_PREP(IMX95_PE0_LUT_REQID, reqid); + + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, data2); + + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, i); + + return 0; + } + + dev_err(dev, "All lut already used\n"); + return -EINVAL; +} + +static void imx_pcie_remove_lut(struct imx_pcie *imx_pcie, u16 reqid) +{ + u32 data2 =3D 0; + int i; + + guard(mutex)(&imx_pcie->lock); + + for (i =3D 0; i < IMX95_MAX_LUT; i++) { + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, IMX95_PEO_LUT_= RWA | i); + + regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, &data2); + if (FIELD_GET(IMX95_PE0_LUT_REQID, data2) =3D=3D reqid) { + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, 0); + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, 0); + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, i); + } + } +} + +static int imx_pcie_enable_device(struct pci_bus *bus, struct pci_dev *pde= v) +{ + u32 sid_i =3D 0, sid_m =3D 0, rid =3D pci_dev_id(pdev); + struct imx_pcie *imx_pcie; + struct device *dev; + int err; + + imx_pcie =3D to_imx_pcie(to_dw_pcie_from_pp(bus->sysdata)); + dev =3D imx_pcie->pci->dev; + + err =3D of_map_id(dev->of_node, rid, "iommu-map", "iommu-map-mask", NULL,= &sid_i); + if (err) + return err; + + err =3D of_map_id(dev->of_node, rid, "msi-map", "msi-map-mask", NULL, &si= d_m); + if (err) + return err; + + if (sid_i !=3D rid && sid_m !=3D rid) + if ((sid_i & IMX95_SID_MASK) !=3D (sid_m & IMX95_SID_MASK)) { + dev_err(dev, "its and iommu stream id miss match, please check dts file= \n"); + return -EINVAL; + } + + /* if iommu-map is not existed then use msi-map's stream id*/ + if (sid_i =3D=3D rid) + sid_i =3D sid_m; + + sid_i &=3D IMX95_SID_MASK; + + if (sid_i !=3D rid) + return imx_pcie_add_lut(imx_pcie, rid, sid_i); + + /* Use dwc built-in MSI controller */ + return 0; +} + +static void imx_pcie_disable_device(struct pci_bus *bus, struct pci_dev *p= dev) +{ + struct imx_pcie *imx_pcie; + + imx_pcie =3D to_imx_pcie(to_dw_pcie_from_pp(bus->sysdata)); + imx_pcie_remove_lut(imx_pcie, pci_dev_id(pdev)); +} + static int imx_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); @@ -941,6 +1064,11 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp) } } =20 + if (pp->bridge && imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_LUT)) { + pp->bridge->ops->enable_device =3D imx_pcie_enable_device; + pp->bridge->ops->disable_device =3D imx_pcie_disable_device; + } + imx_pcie_assert_core_reset(imx_pcie); =20 if (imx_pcie->drvdata->init_phy) @@ -1292,6 +1420,8 @@ static int imx_pcie_probe(struct platform_device *pde= v) imx_pcie->pci =3D pci; imx_pcie->drvdata =3D of_device_get_match_data(dev); =20 + mutex_init(&imx_pcie->lock); + /* Find the PHY if one is defined, only imx7d uses it */ np =3D of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0); if (np) { @@ -1587,7 +1717,8 @@ static const struct imx_pcie_drvdata drvdata[] =3D { }, [IMX95] =3D { .variant =3D IMX95, - .flags =3D IMX_PCIE_FLAG_HAS_SERDES, + .flags =3D IMX_PCIE_FLAG_HAS_SERDES | + IMX_PCIE_FLAG_HAS_LUT, .clk_names =3D imx8mq_clks, .clks_cnt =3D ARRAY_SIZE(imx8mq_clks), .ltssm_off =3D IMX95_PE0_GEN_CTRL_3, --=20 2.34.1