From nobody Fri Nov 29 00:53:51 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DEE5F18BB84; Thu, 26 Sep 2024 06:55:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727333737; cv=none; b=U187dk3bRwznl4NkZKBxxWaWiCR/8bnsRRfCeVLpuE4Aeihs7t4TWFyq4HldfCstULpIMWK4hBE2/hm9aIiQYpSLPHBpxyQNBdaClKB2ltABtkiX2xXjlNnbX1sdU57fQfW9lmORWrYU9sqTtRrpZRhvQZYFRNedAdn9QGrmee8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727333737; c=relaxed/simple; bh=SWUPv2yT9vFS1HF8hRCvwlmEe4NDPJrRcVUDDOhbUmo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=VXAwe7aoNA+i13CcN0rYdIkEs++RwjhjDQoWsTpoDqFSSLAkuQqlDhtFFlfEk7z3gYJps/joEU6BmQjKXBoumP7kZy1Rs61OgLkUOid0HSzvKnATKDvCxWB7SAkV/ON2S9FyMbYR2R4tJjb2/BYhr3ebySbpAYr4gjrvZLA7GPI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=ln7lkkWb; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="ln7lkkWb" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48PH5C1Z027655; Thu, 26 Sep 2024 06:55:14 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= ZMYU44qOA/0KMilXTlkfwD0/Wursf8pVE12AIec0iDA=; b=ln7lkkWb58bLbLGm SAFcToDFHFmXLdUi0fX00/2+lYJlQd77vXzJfcwIBZfMe9bj6Ck4Yqv/El3UaKch PGZstY+FcBXMwkTZlbIRXOVQ6A42XthVcVPB7KDHgTFvPZrUWqVds9jdy4Wv3RSD 0VorGgSnowVM4MBmlRisqP1gRj9sKzNJEH4TOZyGj9nYp8DVmiJpd20w6PNhd/SJ UCaMbKFxNobdzNEq4vCX40+ySokNs2R1hCnZ3+jWIDFdZNqPtcY+mWwOl1gMhK5p qMlg0LFCv/xu10Ms2O+jualuqjkuLMI1lIRsCDxGga08gO5xwhiIPfBKXI4Zwc2C 96a9QQ== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 41spc2xec6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 26 Sep 2024 06:55:13 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48Q6tDNd010853 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 26 Sep 2024 06:55:13 GMT Received: from lijuang2-gv.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 25 Sep 2024 23:55:06 -0700 From: Lijuan Gao Date: Thu, 26 Sep 2024 14:54:41 +0800 Subject: [PATCH v3 1/7] dt-bindings: arm: qcom: document QCS615 and the reference board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240926-add_initial_support_for_qcs615-v3-1-e37617e91c62@quicinc.com> References: <20240926-add_initial_support_for_qcs615-v3-0-e37617e91c62@quicinc.com> In-Reply-To: <20240926-add_initial_support_for_qcs615-v3-0-e37617e91c62@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Gleixner , Catalin Marinas , Will Deacon CC: , , , , , Lijuan Gao , "Krzysztof Kozlowski" X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727333702; l=1010; i=quic_lijuang@quicinc.com; s=20240827; h=from:subject:message-id; bh=SWUPv2yT9vFS1HF8hRCvwlmEe4NDPJrRcVUDDOhbUmo=; b=wzx+zlK1xDrKcDme0fW9zJ9SO6YKMh9XbwCPFMO1yplpywQVWHsAnYo9KrQuh+lBSV3Pvd6/C kFi6Gr7b3EyAXZBqi2uo2zda+al4xrBdY1lpNV4Hf2T7xj8ucursF91 X-Developer-Key: i=quic_lijuang@quicinc.com; a=ed25519; pk=1zeM8FpQK/J1jSFHn8iXHeb3xt7F/3GvHv7ET2RNJxE= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: buzxagTfgaNbyofgELwUFwRxJPDnPzZn X-Proofpoint-ORIG-GUID: buzxagTfgaNbyofgELwUFwRxJPDnPzZn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 suspectscore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 malwarescore=0 adultscore=0 phishscore=0 mlxlogscore=999 bulkscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409260044 Document the QCS615 SoC and its reference board QCS615 RIDE. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Lijuan Gao --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index 5cb54d69af0b..a0c9e7179ce9 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -42,6 +42,7 @@ description: | msm8996 msm8998 qcs404 + qcs615 qcs8550 qcm2290 qcm6490 @@ -895,6 +896,11 @@ properties: - const: qcom,qcs404-evb - const: qcom,qcs404 =20 + - items: + - enum: + - qcom,qcs615-ride + - const: qcom,qcs615 + - items: - enum: - qcom,sa8155p-adp --=20 2.46.0 From nobody Fri Nov 29 00:53:51 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E5A018EFC6; Thu, 26 Sep 2024 06:55:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727333739; cv=none; b=cuZnfDPYzyBNPiDdyZiXc3aDMEvQ+s+A7l6+bHWqmkUruazEB6oAbIaSjKnTLx0CTYXwNyOvqzOCf34GMVTaROtMX6BQD1NFDzb1W1e+PFIcpO65HENOmw5HEPpfBQQ6JGfLo8LlDsECUHSzeiwsCGcnfElaY0TshKQWyoFTJAE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727333739; c=relaxed/simple; bh=gIP0/TCZdf9SS0xaxin/HqkuUE20HR2NpxJlMV7qgmE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=tt88b+9BiVZh4Lk6dBwBZvyL1Ueo3J2mCYVJUvK7W9rER0lUZbREm4ilYnOPbDbu6xYruvQwkudr8+sS7Ti9M+2gD1kdFmAqTSuf0+QeTeEJBgX9gx4k7kzq+/mOgfdR+WUnG8ehWKjyD5RkHCQpw+K/M8gG5I6/2J8HUXD1lg8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Z1oe3Lkx; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Z1oe3Lkx" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48PH5PDg010614; Thu, 26 Sep 2024 06:55:18 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= yqm2LjLXE/r1TJLp2pEnHWxRn3Y+3lElNlsr2cs//dg=; b=Z1oe3LkxENYtOUy7 KjxY5XW0jX6XISspWH3xlCQ4okrcZv0eJqo+sQ+1j546CTVGBph3V2KjnTQ2OceZ OrWnHJsHf5Tu+Eny/cmh1dk7z8FCXST6h9qSvzUWOwEdXZN2WvigtnwGztC9PMKI xfEW/O6MCErwBeCWQWDZUIoKYvUZxS826QPtWkVIpsGdHapforPpsLmjPe/gixnS KrJw+2YDuTw/i1HWag7kWHYeT339G/w2xy5+UlZutKPUbakeNiOjV66gZlbLYidI DrhjUQvS1sHZCDoFAOjWiTeWUyKs4I9VisrKU2UoWbUcgamgbDk6HlXwHMO/qpTX zhBq0w== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 41sph6xrqg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 26 Sep 2024 06:55:18 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48Q6tGnX008073 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 26 Sep 2024 06:55:17 GMT Received: from lijuang2-gv.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 25 Sep 2024 23:55:09 -0700 From: Lijuan Gao Date: Thu, 26 Sep 2024 14:54:42 +0800 Subject: [PATCH v3 2/7] dt-bindings: arm: qcom,ids: add SoC ID for QCS615 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240926-add_initial_support_for_qcs615-v3-2-e37617e91c62@quicinc.com> References: <20240926-add_initial_support_for_qcs615-v3-0-e37617e91c62@quicinc.com> In-Reply-To: <20240926-add_initial_support_for_qcs615-v3-0-e37617e91c62@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Gleixner , Catalin Marinas , Will Deacon CC: , , , , , Lijuan Gao , "Krzysztof Kozlowski" X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727333702; l=708; i=quic_lijuang@quicinc.com; s=20240827; h=from:subject:message-id; bh=gIP0/TCZdf9SS0xaxin/HqkuUE20HR2NpxJlMV7qgmE=; b=kvqXIZIbh3/VS0ThfCbtnL9LO0TRDZlMxzh/7kRQF7z0ydechawoh+KyodAOPaW63Vl/t6UTj jcz6jKRIOqIDwGv3ZKYDkBT04bWFVoqbfMw++u3W4kER7az6ROIzFww X-Developer-Key: i=quic_lijuang@quicinc.com; a=ed25519; pk=1zeM8FpQK/J1jSFHn8iXHeb3xt7F/3GvHv7ET2RNJxE= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: LRDKJ3x9rmi4VazUIWOYW0eC8QgoA_-E X-Proofpoint-ORIG-GUID: LRDKJ3x9rmi4VazUIWOYW0eC8QgoA_-E X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 bulkscore=0 spamscore=0 clxscore=1015 mlxlogscore=742 mlxscore=0 adultscore=0 phishscore=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409260044 Add the ID for the Qualcomm QCS615 SoC. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Lijuan Gao --- include/dt-bindings/arm/qcom,ids.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/q= com,ids.h index 8332f8d82f96..73a69fc535f6 100644 --- a/include/dt-bindings/arm/qcom,ids.h +++ b/include/dt-bindings/arm/qcom,ids.h @@ -278,6 +278,7 @@ #define QCOM_ID_IPQ5321 650 #define QCOM_ID_QCS8300 674 #define QCOM_ID_QCS8275 675 +#define QCOM_ID_QCS615 680 =20 /* * The board type and revision information, used by Qualcomm bootloaders a= nd --=20 2.46.0 From nobody Fri Nov 29 00:53:51 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5BAB8178CE2; Thu, 26 Sep 2024 06:55:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727333735; cv=none; b=sJLANyAnx97gNDfSezIAVfiwqXz0MFcI1OCBldTiy+2UjKqk7CFO0McMlwva2+SSUD3wHtXkEYyyf3M7yZsKox9c8kLonJe/TROEb3dCqbNO1e3DkXTOUrxrOEwW632wFP8qY35c+TPb/tliSVnz97aEM4W3eg8gEUPtH7zMj/Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727333735; c=relaxed/simple; bh=AtswLMPp1Wi7CQvp+HGZVxBi+0M87Go/UAkK7Kw+6RE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=tPRk2zhWF/lfZw7WDFxr9ui6416X0eEwBvAGW9VI2O/cLL6VanPQJizL0LKuF/ZwHvplJO2ne14f2Py5Sqg5KA6ZizvOjaIkLPnOh8irEMDgcYZB3N2U5IWsTI6gXWes7jsCuL1z4P5caoNZo8nLw4F82da0XbcwiQ0uaHEKNBw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=iRZoG0KT; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="iRZoG0KT" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48PH5NNq010569; Thu, 26 Sep 2024 06:55:22 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= zY6WwSnWBK+sJbMEG9WnEhZquIYMOfDGtRU22+UrV6w=; b=iRZoG0KTASZSRUSA EQHxuOlv3p74ivS7Oi4naRqQVqq2ugVaT6xjynlo0EwNVJZf0sdiyK3OKOiH7OH1 8dY/vMvYM408NyoMImfCKLGuQ8rkbM6wueAa1nD7tnOVKsVwgojjp/gHx+hcIdOb NWoN366/x5/m2inFZJaaAZYrIkfZUkyggO1U13Py6ZTefxN2mEa99sdHkZnWZGAW TEP0G1Jfj+kDBZ8GWEDk3+RCDxESr4ydihHjMkq5/fNEnvlVat8XCdLICYfi6C/c qdkUZxbLC8xsYkEEkI4rwYeoWueW8FZFa1/ngekAkHbx35Q+7Il3qb1kri9LK5Od xS+cqQ== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 41sph6xrqp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 26 Sep 2024 06:55:21 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48Q6tK6G031854 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 26 Sep 2024 06:55:20 GMT Received: from lijuang2-gv.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 25 Sep 2024 23:55:13 -0700 From: Lijuan Gao Date: Thu, 26 Sep 2024 14:54:43 +0800 Subject: [PATCH v3 3/7] dt-bindings: qcom,pdc: document QCS615 Power Domain Controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240926-add_initial_support_for_qcs615-v3-3-e37617e91c62@quicinc.com> References: <20240926-add_initial_support_for_qcs615-v3-0-e37617e91c62@quicinc.com> In-Reply-To: <20240926-add_initial_support_for_qcs615-v3-0-e37617e91c62@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Gleixner , Catalin Marinas , Will Deacon CC: , , , , , Lijuan Gao , "Krzysztof Kozlowski" X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727333702; l=871; i=quic_lijuang@quicinc.com; s=20240827; h=from:subject:message-id; bh=AtswLMPp1Wi7CQvp+HGZVxBi+0M87Go/UAkK7Kw+6RE=; b=vi69A2X0tnrLIU7YOElypZV6J3K/AE3yrHuSmsAXhAIFr1eyzcFPPabGr3jO4hxQEqFBooOJI oiD0bmuw/fpB3ZfyttLTf78pj2DaZwoxoGc9U/DTUjont1NlK4sArsR X-Developer-Key: i=quic_lijuang@quicinc.com; a=ed25519; pk=1zeM8FpQK/J1jSFHn8iXHeb3xt7F/3GvHv7ET2RNJxE= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: dGs3OACMHEYKFtu81gCZmCL4oHGpzGRd X-Proofpoint-ORIG-GUID: dGs3OACMHEYKFtu81gCZmCL4oHGpzGRd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 bulkscore=0 spamscore=0 clxscore=1015 mlxlogscore=829 mlxscore=0 adultscore=0 phishscore=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409260044 Add a compatible for the Power Domain Controller on QCS615 platform. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Lijuan Gao --- Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pd= c.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.ya= ml index b1ea08a41bb0..ac7ccd989441 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml @@ -26,6 +26,7 @@ properties: compatible: items: - enum: + - qcom,qcs615-pdc - qcom,qdu1000-pdc - qcom,sa8255p-pdc - qcom,sa8775p-pdc --=20 2.46.0 From nobody Fri Nov 29 00:53:51 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BAF7E189539; Thu, 26 Sep 2024 06:55:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727333738; cv=none; b=Pwhqo5++wzVSLpRmxLN9qWdlVp10nnGJxE8yHGMHw+8Cv9bq4ErMrdbGVVNjFUJ22MEBkQSXk0x+eJxQ2Z7j2q8KOQJl6S6gywUQHIhqjckmm5eoJOp3SrMtQ5rLlKh/CBnha+2NiVc5SBCty60blD+vKlSoZmXgAfUolMxV2q8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727333738; c=relaxed/simple; bh=+E3/689TwEgY7ix6TLXHltPSLY7R7Acumow2lUJcdto=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=Rnh1On9LfgmkMIpTFenby0zwZs0qbABKpzLb2jTIcz7Br6Qa+Bn5/iZxPz956BroGhAf+QJ6iIu6HP7aYNE0yWTpBd87w/upXtxz2yjEEPN31+YeUZUtmq5Wm/K57lqxh+2xunQZEnSdJTBm5gy7doZU8a55VRdIuZ2cv11fAP4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=cq63EdLP; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="cq63EdLP" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48PH5Oh6010596; Thu, 26 Sep 2024 06:55:25 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 9XrGdMl6JyAxrI7nfjlW1YxjHF1XB4CjpzdoNqBPCmw=; b=cq63EdLPPESoAYj5 2YqvCl6Fn6r74BhODTNgqZ4xOdntjg9lIKOeWyd8ea0m4KhhWJ9cpKj2tjvPwARh 13A3/mi0F0RpHZf5p7c/vVXioeU04USHleTmSNOt/KD5UjcTsWUE5O+2Kwd0ODw5 nKCZxa/BG0RxJJa12BtaiSx9jUkFxTGnwRswRkstFlj0vBtRY3cddpeM7ILe1lmI yt2RC7p2AINp7PKrHHGiX6C33zz68/c6s4Vkkl7OcWc5atiBvyjaUdmLDEQgVd/C nTOVh8Z8tRYQJhNyBwFwUAfHo4/7vTlPDGrbaB9CQyLIA/JEfvUCRcHh6deaetbY 0jei/A== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 41sph6xrqt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 26 Sep 2024 06:55:25 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48Q6tNLA031871 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 26 Sep 2024 06:55:24 GMT Received: from lijuang2-gv.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 25 Sep 2024 23:55:17 -0700 From: Lijuan Gao Date: Thu, 26 Sep 2024 14:54:44 +0800 Subject: [PATCH v3 4/7] soc: qcom: socinfo: Add QCS615 SoC ID table entry Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240926-add_initial_support_for_qcs615-v3-4-e37617e91c62@quicinc.com> References: <20240926-add_initial_support_for_qcs615-v3-0-e37617e91c62@quicinc.com> In-Reply-To: <20240926-add_initial_support_for_qcs615-v3-0-e37617e91c62@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Gleixner , Catalin Marinas , Will Deacon CC: , , , , , Lijuan Gao , "Krzysztof Kozlowski" X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727333702; l=705; i=quic_lijuang@quicinc.com; s=20240827; h=from:subject:message-id; bh=+E3/689TwEgY7ix6TLXHltPSLY7R7Acumow2lUJcdto=; b=ay1/snPaq50JWr7aI9Tzd5Z8TE3ZzPYjEu/kjTETd87G6EI5mvnOgzYP1wrP2tjt2dXag/TCf c8G/ViUKLN/DJmQz4uKfwreDw453hh9dFwSckObZajh4M/Ow8sLbQwh X-Developer-Key: i=quic_lijuang@quicinc.com; a=ed25519; pk=1zeM8FpQK/J1jSFHn8iXHeb3xt7F/3GvHv7ET2RNJxE= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 9lKVu8J477tprwpaAMslbJQwAs3Dzq61 X-Proofpoint-ORIG-GUID: 9lKVu8J477tprwpaAMslbJQwAs3Dzq61 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 bulkscore=0 spamscore=0 clxscore=1015 mlxlogscore=999 mlxscore=0 adultscore=0 phishscore=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409260044 Add SoC Info support for the QCS615 platform. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Lijuan Gao --- drivers/soc/qcom/socinfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 24c3971f2ef1..aed430f10eec 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -445,6 +445,7 @@ static const struct soc_id soc_id[] =3D { { qcom_board_id(IPQ5321) }, { qcom_board_id(QCS8300) }, { qcom_board_id(QCS8275) }, + { qcom_board_id(QCS615) }, }; =20 static const char *socinfo_machine(struct device *dev, unsigned int id) --=20 2.46.0 From nobody Fri Nov 29 00:53:51 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CCA01A3BC0; Thu, 26 Sep 2024 06:55:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727333742; cv=none; b=Jx+yAuMRiwfRLp2ATOzmaka+kmg9fFCRgCq3+/ENGgrWFvw04Ru2SOj4Zjevv9r4ZHim71Xi9LjqJF30ZeS4bdzSYiokFLNiMIVuzUT3X8MhsOD7UEOWOMfqzmvGCRj9I1NM+5mVeCZ1cP9ZgpQsYEKsj19ox0+QYaV53NWBYIE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727333742; c=relaxed/simple; bh=U+axW+21wOlelLitUkCovPZSnTLec9tHQGVUMyLKg7w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=Cmlu3gSnAeTqsAliyTZVLGn0D3dROwLMv2By4+gzoH+01UezxDPfpyLuJfI0YXGdw/V0PRtOooz3gRgVXdyqqsvE9PlOmXZiOXatqVAyXhvpkEp0lj36aCGOrh7vTCmOBIHm4g1Lw7KQGHB62G6PoQQwSuo0EVfCRiaZ9lwHDZg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=eVnpEQdQ; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="eVnpEQdQ" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48PH5M8r032311; Thu, 26 Sep 2024 06:55:29 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= y1GZ5bqAvfMVh5+0CaXHzkFGGg6CwAeAzbpfHg6U2Uw=; b=eVnpEQdQNeL+sMZf B1+5k4RJpT7XkaSv1nklfyy8lp31sqq4g+Fvi5dDXTd5CypBdfyNMx83yQtnaUzh 9c8TzWpMloTNdk9aL01QSIIbKcDg9wHG4oOf5amdV1zEZpg5qXHkgQQlpx9lcdQU EHCJoCQdQUvfxNPUcPMOHvwZFBRFI8TDBhZKti9BTDmU5LRUaQlZMe8rHHPUFeqV aqBXVMlblWvrfkhCuJ+Xvf103+bAIYDQnIQEyPT3PU7UxWthzxYYhxJT3w6O3mlI ctpu0aNfVLyg7wG7w4i8K6FPx5NDPwExn1ZLAbFfIHFRkYtCsmnTcM2yCQCdQvVr nDSBDQ== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 41sp7upqu9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 26 Sep 2024 06:55:29 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48Q6tSof008627 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 26 Sep 2024 06:55:28 GMT Received: from lijuang2-gv.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 25 Sep 2024 23:55:21 -0700 From: Lijuan Gao Date: Thu, 26 Sep 2024 14:54:45 +0800 Subject: [PATCH v3 5/7] arm64: dts: qcom: add initial support for QCS615 DTSI Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240926-add_initial_support_for_qcs615-v3-5-e37617e91c62@quicinc.com> References: <20240926-add_initial_support_for_qcs615-v3-0-e37617e91c62@quicinc.com> In-Reply-To: <20240926-add_initial_support_for_qcs615-v3-0-e37617e91c62@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Gleixner , Catalin Marinas , Will Deacon CC: , , , , , Lijuan Gao , Tingguo Cheng , Taniya Das , "Swetha Chintavatla" X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727333702; l=18872; i=quic_lijuang@quicinc.com; s=20240827; h=from:subject:message-id; bh=U+axW+21wOlelLitUkCovPZSnTLec9tHQGVUMyLKg7w=; b=ohnmDPFjxuR7Uo15gXZsphJQlxZ4SYGNhO5m2u3eDc/nML2b7X0ewSMCji868Yl0HPAa/hpPq KsBkGjlkKDyAs8xmgN2o9cRxBGL8/Azh9f5TBZG/ot6ip5Re/atr7g7 X-Developer-Key: i=quic_lijuang@quicinc.com; a=ed25519; pk=1zeM8FpQK/J1jSFHn8iXHeb3xt7F/3GvHv7ET2RNJxE= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Wmjv5PEc4DYvoNnlKd2bwyRkhk1L4Up5 X-Proofpoint-ORIG-GUID: Wmjv5PEc4DYvoNnlKd2bwyRkhk1L4Up5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 mlxlogscore=999 mlxscore=0 phishscore=0 suspectscore=0 impostorscore=0 spamscore=0 malwarescore=0 priorityscore=1501 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409260044 Add initial DTSI for QCS615 SoC. Features added in this revision: - CPUs with PSCI idle states - Interrupt-controller with PDC wakeup support - Timers, TCSR Clock Controllers - Reserved Shared memory - QFPROM - TLMM - Watchdog - RPMH controller - Sleep stats driver - Rpmhpd power controller - Interconnect - GCC and Rpmhcc - QUP with Uart serial support [Tingguo: added rpmhpd power controller nodes] Co-developed-by: Tingguo Cheng Signed-off-by: Tingguo Cheng [Taniya: added clocks nodes] Co-developed-by: Taniya Das Signed-off-by: Taniya Das [Swetha: added interconnect nodes] Co-developed-by: Swetha Chintavatla Signed-off-by: Swetha Chintavatla Signed-off-by: Lijuan Gao --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 688 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 688 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qco= m/qcs615.dtsi new file mode 100644 index 000000000000..ac4c4c751da1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -0,0 +1,688 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent =3D <&intc>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0 0x0>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd0>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + + l2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0 0x100>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd1>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_100>; + + l2_100: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0 0x200>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd2>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_200>; + + l2_200: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0 0x300>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd3>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_300>; + + l2_300: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu4: cpu@400 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0 0x400>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd4>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_400>; + + l2_400: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu5: cpu@500 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0 0x500>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd5>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_500>; + + l2_500: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu6: cpu@600 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a76"; + reg =3D <0x0 0x600>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd6>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_600>; + #cooling-cells =3D <2>; + + l2_600: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu7: cpu@700 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a76"; + reg =3D <0x0 0x700>; + enable-method =3D "psci"; + power-domains =3D <&cpu_pd7>; + power-domain-names =3D "psci"; + next-level-cache =3D <&l2_700>; + + l2_700: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + + core4 { + cpu =3D <&cpu4>; + }; + + core5 { + cpu =3D <&cpu5>; + }; + + core6 { + cpu =3D <&cpu6>; + }; + + core7 { + cpu =3D <&cpu7>; + }; + }; + }; + + l3_0: l3-cache { + compatible =3D "cache"; + cache-level =3D <3>; + cache-unified; + }; + }; + + idle-states { + entry-method =3D "psci"; + + little_cpu_sleep_0: cpu-sleep-0-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "silver-power-collapse"; + arm,psci-suspend-param =3D <0x40000003>; + entry-latency-us =3D <549>; + exit-latency-us =3D <901>; + min-residency-us =3D <1774>; + local-timer-stop; + }; + + little_cpu_sleep_1: cpu-sleep-0-1 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "silver-rail-power-collapse"; + arm,psci-suspend-param =3D <0x40000004>; + entry-latency-us =3D <702>; + exit-latency-us =3D <915>; + min-residency-us =3D <4001>; + local-timer-stop; + }; + + big_cpu_sleep_0: cpu-sleep-1-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "gold-power-collapse"; + arm,psci-suspend-param =3D <0x40000003>; + entry-latency-us =3D <523>; + exit-latency-us =3D <1244>; + min-residency-us =3D <2207>; + local-timer-stop; + }; + + big_cpu_sleep_1: cpu-sleep-1-1 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "gold-rail-power-collapse"; + arm,psci-suspend-param =3D <0x40000004>; + entry-latency-us =3D <526>; + exit-latency-us =3D <1854>; + min-residency-us =3D <5555>; + local-timer-stop; + }; + }; + + domain-idle-states { + cluster_sleep_0: cluster-sleep-0 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x41000044>; + entry-latency-us =3D <2752>; + exit-latency-us =3D <3048>; + min-residency-us =3D <6118>; + }; + + cluster_sleep_1: cluster-sleep-1 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x41001344>; + entry-latency-us =3D <3263>; + exit-latency-us =3D <4562>; + min-residency-us =3D <8467>; + }; + + cluster_sleep_2: cluster-sleep-2 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x4100b344>; + entry-latency-us =3D <3638>; + exit-latency-us =3D <6562>; + min-residency-us =3D <9826>; + }; + }; + + memory@80000000 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the size */ + reg =3D <0 0x80000000 0 0>; + }; + + camnoc_virt: interconnect-0 { + compatible =3D "qcom,qcs615-camnoc-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + ipa_virt: interconnect-1 { + compatible =3D "qcom,qcs615-ipa-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + mc_virt: interconnect-2 { + compatible =3D "qcom,qcs615-mc-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + + cpu_pd0: power-domain-cpu0 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; + }; + + cpu_pd1: power-domain-cpu1 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; + }; + + cpu_pd2: power-domain-cpu2 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; + }; + + cpu_pd3: power-domain-cpu3 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; + }; + + cpu_pd4: power-domain-cpu4 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; + }; + + cpu_pd5: power-domain-cpu5 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; + }; + + cpu_pd6: power-domain-cpu6 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; + }; + + cpu_pd7: power-domain-cpu7 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; + }; + + cluster_pd: power-domain-cluster { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cluster_sleep_0 + &cluster_sleep_1 + &cluster_sleep_2>; + }; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + smem_region: smem@86000000 { + compatible =3D "qcom,smem"; + reg =3D <0x0 0x86000000 0x0 0x200000>; + no-map; + hwlocks =3D <&tcsr_mutex 3>; + }; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + ranges =3D <0 0 0 0 0x10 0>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + gcc: clock-controller@100000 { + compatible =3D "qcom,qcs615-gcc"; + reg =3D <0 0x00100000 0 0x1f0000>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + qfprom: efuse@780000 { + compatible =3D "qcom,qcs615-qfprom", "qcom,qfprom"; + reg =3D <0x0 0x00780000 0x0 0x7000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; + + qupv3_id_0: geniqup@8c0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x8c0000 0x0 0x6000>; + ranges; + clocks =3D <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names =3D "m-ahb", + "s-ahb"; + #address-cells =3D <2>; + #size-cells =3D <2>; + status =3D "disabled"; + + uart0: serial@880000 { + compatible =3D "qcom,geni-debug-uart"; + reg =3D <0x0 0x880000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart0_tx>, <&qup_uart0_rx>; + pinctrl-names =3D "default"; + interrupts =3D ; + interconnects =3D <&aggre1_noc MASTER_QUP_0 0 + &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 + &config_noc SLAVE_QUP_0 0>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + status =3D "disabled"; + }; + }; + + config_noc: interconnect@1500000 { + reg =3D <0x0 0x1500000 0x0 0x5080>; + compatible =3D "qcom,qcs615-config-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + system_noc: interconnect@1620000 { + reg =3D <0x0 0x1620000 0x0 0x1f300>; + compatible =3D "qcom,qcs615-system-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@1700000 { + reg =3D <0x0 0x1700000 0x0 0x3f200>; + compatible =3D "qcom,qcs615-aggre1-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1740000 { + reg =3D <0x0 0x1740000 0x0 0x1c100>; + compatible =3D "qcom,qcs615-mmss-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x0 0x01f40000 0x0 0x20000>; + #hwlock-cells =3D <1>; + }; + + tcsr: syscon@1fc0000 { + compatible =3D "qcom,qcs615-tcsr", "syscon"; + reg =3D <0x0 0x1fc0000 0x0 0x30000>; + }; + + tlmm: pinctrl@3100000 { + compatible =3D "qcom,qcs615-tlmm"; + reg =3D <0x0 0x03100000 0x0 0x300000>, + <0x0 0x03500000 0x0 0x300000>, + <0x0 0x03d00000 0x0 0x300000>; + reg-names =3D "east", + "west", + "south"; + interrupts =3D ; + gpio-ranges =3D <&tlmm 0 0 123>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + wakeup-parent =3D <&pdc>; + + qup_uart0_tx: qup-uart0-tx-state { + pins =3D "gpio16"; + function =3D "qup0"; + }; + + qup_uart0_rx: qup-uart0-rx-state { + pins =3D "gpio17"; + function =3D "qup0"; + }; + }; + + dc_noc: interconnect@9160000 { + reg =3D <0x0 0x9160000 0x0 0x3200>; + compatible =3D "qcom,qcs615-dc-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + gem_noc: interconnect@9680000 { + reg =3D <0x0 0x9680000 0x0 0x3e200>; + compatible =3D "qcom,qcs615-gem-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + pdc: interrupt-controller@b220000 { + compatible =3D "qcom,qcs615-pdc", "qcom,pdc"; + reg =3D <0x0 0x0b220000 0x0 0x30000>, + <0x0 0x17c000f0 0x0 0x64>; + qcom,pdc-ranges =3D <0 480 94>, <94 609 31>, <125 63 1>; + interrupt-parent =3D <&intc>; + #interrupt-cells =3D <2>; + interrupt-controller; + }; + + sram@c3f0000 { + compatible =3D "qcom,rpmh-stats"; + reg =3D <0x0 0x0c3f0000 0x0 0x400>; + }; + + intc: interrupt-controller@17a00000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x17a00000 0x0 0x10000>, /* GICD */ + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ + interrupts =3D ; + #interrupt-cells =3D <3>; + interrupt-controller; + #redistributor-regions =3D <1>; + redistributor-stride =3D <0x0 0x20000>; + }; + + watchdog: watchdog@17c10000 { + compatible =3D "qcom,apss-wdt-qcs615", "qcom,kpss-wdt"; + reg =3D <0x0 0x17c10000 0x0 0x1000>; + interrupts =3D ; + }; + + timer@17c20000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0 0x17c20000 0x0 0x1000>; + ranges =3D <0 0 0 0x20000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + frame@17c21000 { + reg =3D <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + frame-number =3D <0>; + interrupts =3D , + ; + }; + + frame@17c23000 { + reg =3D <0x17c23000 0x1000>; + frame-number =3D <1>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@17c25000 { + reg =3D <0x17c25000 0x1000>; + frame-number =3D <2>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@17c27000 { + reg =3D <0x17c27000 0x1000>; + frame-number =3D <3>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@17c29000 { + reg =3D <0x17c29000 0x1000>; + frame-number =3D <4>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@17c2b000 { + reg =3D <0x17c2b000 0x1000>; + frame-number =3D <5>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@17c2d000 { + reg =3D <0x17c2d000 0x1000>; + frame-number =3D <6>; + interrupts =3D ; + status =3D "disabled"; + }; + }; + + apps_rsc: rsc@18200000 { + compatible =3D "qcom,rpmh-rsc"; + reg =3D <0x0 0x18200000 0x0 0x10000>, + <0x0 0x18210000 0x0 0x10000>, + <0x0 0x18220000 0x0 0x10000>; + reg-names =3D "drv-0", + "drv-1", + "drv-2"; + + interrupts =3D , + , + ; + + qcom,drv-id =3D <2>; + qcom,tcs-offset =3D <0xd00>; + qcom,tcs-config =3D , + , + , + ; + + label =3D "apps_rsc"; + power-domains =3D <&cluster_pd>; + + apps_bcm_voter: bcm-voter { + compatible =3D "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible =3D "qcom,qcs615-rpmh-clk"; + clock-names =3D "xo"; + + #clock-cells =3D <1>; + }; + + rpmhpd: power-controller { + compatible =3D "qcom,qcs615-rpmhpd"; + #power-domain-cells =3D <1>; + operating-points-v2 =3D <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + rpmhpd_opp_ret: opp-0 { + opp-level =3D ; + }; + + rpmhpd_opp_min_svs: opp-1 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs: opp-2 { + opp-level =3D ; + }; + + rpmhpd_opp_svs: opp-3 { + opp-level =3D ; + }; + + rpmhpd_opp_svs_l1: opp-4 { + opp-level =3D ; + }; + + rpmhpd_opp_nom: opp-5 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l1: opp-6 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l2: opp-7 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo: opp-8 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l1: opp-9 { + opp-level =3D ; + }; + }; + }; + }; + }; + + arch_timer: timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; +}; --=20 2.46.0 From nobody Fri Nov 29 00:53:51 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED5331A3BD2; Thu, 26 Sep 2024 06:55:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727333742; cv=none; b=BPTfjGSiG+yUpR12+G5rcR1JEtFKANbJfpSxAAPlVmGyHzzaY1f/A7balwb6zDoZ9WXnLnckmOLe6JQvD5pOORlnF8wcIwSc20hwhBNKG8/hbOBwexO6RoSkDiABMuYeQRo8xaEQW3ggzrgnQhz1H2AKEpcbLLVv+XCAAqojthU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727333742; c=relaxed/simple; bh=2IH8Zzar5GV4Fw2NGwpIicF46E2EG/SZJYCTFRatSgg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=p+9A1oEYQRJa+Qyfzc14IzZ5UtDB9MOVC0QXkZ3pl6q7+WxvLtfqVpF9l9wHu5AnuN+37aZw7IRNN8QP2YUSZT7HoPg1tRbL7+e4KSH2hpjSVcf7gXEcpI/Kv0JN1W/d6eqxa5xFD6jlRvQzXe1uF0929DL0d2V6bLZ6wVuL7Yg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=VENEs/Rv; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="VENEs/Rv" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48PH5CHR027662; Thu, 26 Sep 2024 06:55:32 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= koK9wVEvOVgkUGHFzu0WLiM9W7Ow8a2U+nTAy+y/XgM=; b=VENEs/RvhVTJI4WC 8Ry1ZuJ9oOSdFKjd1ZTKolS4sHDP2Z0hiczKoZi0kYj0C5E63cgHXEzSxYK2EG2n UNVyT3JgZCns3NySO3x2k1TUzpxxyv0S1VfKX2EC9Ea9eCO4L7fd+WKdP0cZi7QT aAdEjqeVYjHHtL9ziAIiQaxcebMhQp4AxzpbS8019P9B2dDljKUHAHdKv1FRPlk6 4rsMUoNLo8m7Q22q39m7YHpn25ILh4tF+uLHJyAtRZ35W7MBZaocjaGqaSniGirT yYqhcPzAogms0pgUD1WiOEPWK40rpXA6WkkW084ThXlJ7J0RsMYj8Ci/fecZ1B4K QnWrGw== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 41spc2xed4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 26 Sep 2024 06:55:31 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48Q6tV6m025390 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 26 Sep 2024 06:55:31 GMT Received: from lijuang2-gv.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 25 Sep 2024 23:55:24 -0700 From: Lijuan Gao Date: Thu, 26 Sep 2024 14:54:46 +0800 Subject: [PATCH v3 6/7] arm64: dts: qcom: add base QCS615 RIDE dts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240926-add_initial_support_for_qcs615-v3-6-e37617e91c62@quicinc.com> References: <20240926-add_initial_support_for_qcs615-v3-0-e37617e91c62@quicinc.com> In-Reply-To: <20240926-add_initial_support_for_qcs615-v3-0-e37617e91c62@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Gleixner , Catalin Marinas , Will Deacon CC: , , , , , Lijuan Gao , Tingguo Cheng X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727333702; l=7657; i=quic_lijuang@quicinc.com; s=20240827; h=from:subject:message-id; bh=2IH8Zzar5GV4Fw2NGwpIicF46E2EG/SZJYCTFRatSgg=; b=X3zk8dmr78owro1Q8pOvoZCqaFj/UXDFJ0C76YWnjjdZ9GR9VJOZwfWQM4kJ4XC4EhyuS6jM2 6cCFKbUgttYByRC9RR3QuT9tERd0gYpFw1R8NG/OClKSIsTjHiKu2IQ X-Developer-Key: i=quic_lijuang@quicinc.com; a=ed25519; pk=1zeM8FpQK/J1jSFHn8iXHeb3xt7F/3GvHv7ET2RNJxE= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 8F2c-C7xdVWk3sdNdfCQp8akttNLitV8 X-Proofpoint-ORIG-GUID: 8F2c-C7xdVWk3sdNdfCQp8akttNLitV8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 suspectscore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 malwarescore=0 adultscore=0 phishscore=0 mlxlogscore=999 bulkscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409260044 Add initial support for Qualcomm QCS615 RIDE board and enable the QCS615 RIDE board to shell with uart console. [Tingguo: added regulator nodes] Co-developed-by: Tingguo Cheng Signed-off-by: Tingguo Cheng Signed-off-by: Lijuan Gao --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/qcs615-ride.dts | 222 +++++++++++++++++++++++++++= ++++ 2 files changed, 223 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index ae002c7cf126..30a1c679bbb7 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -110,6 +110,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D qcm6490-idp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcm6490-shift-otter.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs404-evb-4000.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D qcs615-ride.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs6490-rb3gen2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs8550-aim300-aiot.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qdu1000-idp.dtb diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts= /qcom/qcs615-ride.dts new file mode 100644 index 000000000000..4ef969a6af15 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ +/dts-v1/; + +#include +#include "qcs615.dtsi" +/ { + model =3D "Qualcomm Technologies, Inc. QCS615 Ride"; + compatible =3D "qcom,qcs615-ride", "qcom,qcs615"; + chassis-type =3D "embedded"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + clocks { + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <32000>; + #clock-cells =3D <0>; + }; + + xo_board_clk: xo-board-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <38400000>; + #clock-cells =3D <0>; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id =3D "a"; + + vreg_s3a: smps3 { + regulator-name =3D "vreg_s3a"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <650000>; + regulator-initial-mode =3D ; + }; + + vreg_s4a: smps4 { + regulator-name =3D "vreg_s4a"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1829000>; + regulator-initial-mode =3D ; + }; + + vreg_s5a: smps5 { + regulator-name =3D "vreg_s5a"; + regulator-min-microvolt =3D <1896000>; + regulator-max-microvolt =3D <2040000>; + regulator-initial-mode =3D ; + }; + + vreg_s6a: smps6 { + regulator-name =3D "vreg_s6a"; + regulator-min-microvolt =3D <1304000>; + regulator-max-microvolt =3D <1404000>; + regulator-initial-mode =3D ; + }; + + vreg_l1a: ldo1 { + regulator-name =3D "vreg_l1a"; + regulator-min-microvolt =3D <488000>; + regulator-max-microvolt =3D <852000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2a: ldo2 { + regulator-name =3D "vreg_l2a"; + regulator-min-microvolt =3D <1650000>; + regulator-max-microvolt =3D <3100000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3a: ldo3 { + regulator-name =3D "vreg_l3a"; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1248000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l5a: ldo5 { + regulator-name =3D "vreg_l5a"; + regulator-min-microvolt =3D <875000>; + regulator-max-microvolt =3D <975000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l7a: ldo7 { + regulator-name =3D "vreg_l7a"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1900000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l8a: ldo8 { + regulator-name =3D "vreg_l8a"; + regulator-min-microvolt =3D <1150000>; + regulator-max-microvolt =3D <1350000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l10a: ldo10 { + regulator-name =3D "vreg_l10a"; + regulator-min-microvolt =3D <2950000>; + regulator-max-microvolt =3D <3312000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l11a: ldo11 { + regulator-name =3D "vreg_l11a"; + regulator-min-microvolt =3D <1232000>; + regulator-max-microvolt =3D <1260000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l12a: ldo12 { + regulator-name =3D "vreg_l12a"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1890000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l13a: ldo13 { + regulator-name =3D "vreg_l13a"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3230000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l15a: ldo15 { + regulator-name =3D "vreg_l15a"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1904000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l16a: ldo16 { + regulator-name =3D "vreg_l16a"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3312000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l17a: ldo17 { + regulator-name =3D "vreg_l17a"; + regulator-min-microvolt =3D <2950000>; + regulator-max-microvolt =3D <3312000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; +}; + +&gcc { + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; +}; + +&qupv3_id_0 { + status =3D "okay"; +}; + +&rpmhcc { + clocks =3D <&xo_board_clk>; +}; + +&uart0 { + status =3D "okay"; +}; + +&watchdog { + clocks =3D <&sleep_clk>; +}; --=20 2.46.0 From nobody Fri Nov 29 00:53:51 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 696601A4B80; Thu, 26 Sep 2024 06:55:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727333745; cv=none; b=G0R9o09Z9rD/ekECq+UaquJP890cbUrZrP1KH6ZyZwXpFeWSOOgFQTmeyem1LpjhhBJpeYZSFf5GUFASm983WhNEKlMIPwUrY0HBpD58zRoyXb59l0GPc2oYWbK2L2fUpLZ5fFlWfPWwsDpZi+zUyJR5qrzZnk11ZbTKXSvqp5c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727333745; c=relaxed/simple; bh=xxwXitskCsakF/qCZJEqZAA31USkl0hjaEN4KrBg0hI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=DBWGf9C5GdFd66vv9yYF3qHSi/A3ZAExTTkncWLiteQKVUbv4jC39DAT6FrRWvkiYKL+BRi34/LYZbCDbqnl1Cx7srCjgbRjb8iVI8o1dibqTX5yjeC8jpOR1zHeazCF6twksolow7OayoLGDsmPhX2ySZBD6sKOdA/vo6fKBPo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=YIDqIrCd; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="YIDqIrCd" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48PH5HJq024190; Thu, 26 Sep 2024 06:55:36 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= GEIp388/DE4pBQf4egikwq/BjLVrUcJcWKKsYbY9JRw=; b=YIDqIrCdbvK5rO2Q QFhQh0sE9Z4sgz6wG3fLMZ1dGX64wMHpflGTZGC5tY+yjewfBGNpMVVvC5LlnVe4 Wb2iDaBD8AN4iEsYY02APfEcxe7i5Vy1n7ST1kIW/i1BZ6OFL5/TyDOp8/jMzB/y zTlCPrY6UgUc0wG0PIvxCyBsCAqq/bm0xSluMDhJGtrGQd7Dxro4drSQpU9W/73A C+QwuMp+i2czBw3SL9lbH8rbc1PQ0MzA/6ZnlYfFH2IamJIfczaAUpZM0iYKqc5N q57z/Ifme7duPrx9Aiqqdp3y28mQQbjiEb3Eb+xGgyIffdQqqK76+SW7+rhgfaFv SzEF0A== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 41spwexacd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 26 Sep 2024 06:55:36 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48Q6tZ3i025456 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 26 Sep 2024 06:55:35 GMT Received: from lijuang2-gv.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 25 Sep 2024 23:55:28 -0700 From: Lijuan Gao Date: Thu, 26 Sep 2024 14:54:47 +0800 Subject: [PATCH v3 7/7] arm64: defconfig: enable clock controller, interconnect and pinctrl for QCS615 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240926-add_initial_support_for_qcs615-v3-7-e37617e91c62@quicinc.com> References: <20240926-add_initial_support_for_qcs615-v3-0-e37617e91c62@quicinc.com> In-Reply-To: <20240926-add_initial_support_for_qcs615-v3-0-e37617e91c62@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Gleixner , Catalin Marinas , Will Deacon CC: , , , , , Lijuan Gao X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727333702; l=1429; i=quic_lijuang@quicinc.com; s=20240827; h=from:subject:message-id; bh=xxwXitskCsakF/qCZJEqZAA31USkl0hjaEN4KrBg0hI=; b=1YCY5X16pS8znV6g54YI2IubtsRyf61+FCIYu6S4vgTY/O3T4saD4h6KQqncbOPztr/Lkx853 hsEObmY4gnZAhhkC8yKNzzhXbdFR6W5K/HF2+odlabsVZh012XdycJw X-Developer-Key: i=quic_lijuang@quicinc.com; a=ed25519; pk=1zeM8FpQK/J1jSFHn8iXHeb3xt7F/3GvHv7ET2RNJxE= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Tybk08A8YWJ6X48OMDEYSwb4VrQi3pLO X-Proofpoint-ORIG-GUID: Tybk08A8YWJ6X48OMDEYSwb4VrQi3pLO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 adultscore=0 priorityscore=1501 clxscore=1015 malwarescore=0 mlxscore=0 mlxlogscore=700 impostorscore=0 phishscore=0 spamscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409260043 Enable clock controller, interconnect and pinctrl for Qualcomm QCS615 platform to boot to UART console. The serial engine depends on gcc, interconnect and pinctrl. Since the serial console driver is only available as built-in, so these configs needs be built-in for the UART device to probe and register the console. Signed-off-by: Lijuan Gao --- arch/arm64/configs/defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 5fdbfea7a5b2..c066fe3a32c3 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -607,6 +607,7 @@ CONFIG_PINCTRL_MSM8996=3Dy CONFIG_PINCTRL_MSM8998=3Dy CONFIG_PINCTRL_QCM2290=3Dy CONFIG_PINCTRL_QCS404=3Dy +CONFIG_PINCTRL_QCS615=3Dy CONFIG_PINCTRL_QDF2XXX=3Dy CONFIG_PINCTRL_QDU1000=3Dy CONFIG_PINCTRL_SA8775P=3Dy @@ -1323,6 +1324,7 @@ CONFIG_MSM_MMCC_8998=3Dm CONFIG_QCM_GCC_2290=3Dy CONFIG_QCM_DISPCC_2290=3Dm CONFIG_QCS_GCC_404=3Dy +CONFIG_QCS_GCC_615=3Dy CONFIG_QDU_GCC_1000=3Dy CONFIG_SC_CAMCC_8280XP=3Dm CONFIG_SC_DISPCC_7280=3Dm @@ -1625,6 +1627,7 @@ CONFIG_INTERCONNECT_QCOM_MSM8996=3Dy CONFIG_INTERCONNECT_QCOM_OSM_L3=3Dm CONFIG_INTERCONNECT_QCOM_QCM2290=3Dy CONFIG_INTERCONNECT_QCOM_QCS404=3Dm +CONFIG_INTERCONNECT_QCOM_QCS615=3Dy CONFIG_INTERCONNECT_QCOM_QDU1000=3Dy CONFIG_INTERCONNECT_QCOM_SA8775P=3Dy CONFIG_INTERCONNECT_QCOM_SC7180=3Dy --=20 2.46.0