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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240926-add-performance-tuning-configuration-v2-1-fdbb654f5767@gmail.com> References: <20240926-add-performance-tuning-configuration-v2-0-fdbb654f5767@gmail.com> In-Reply-To: <20240926-add-performance-tuning-configuration-v2-0-fdbb654f5767@gmail.com> To: Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , yasin.lee.x@outlook.com Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Yasin Lee X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1728; i=yasin.lee.x@gmail.com; h=from:subject:message-id; bh=iIzynT3wxdbNQUAm28xrSi7VcFi+h9bvAP8GS/IJDxs=; b=owGbwMvMwCEYyfeRr6Zs90zG02pJDGlfbHkzBAqY33psE6w+fMetWL+MZePE6+f+qBSe/zNvw a3juk3BHaUsDIIcDLJiiixnXr9hzVd9uCf4t2sGzBxWJpAhDFycAjCRgmhGhs26095+NJi63ao3 YPmuZU//qi2XTH1V6n9GIWld07t/398z/I9vjxZ0FmIpFGnNsK9sXZ/oV1dTZOB7fVZIzqJ7q7V 40gA= X-Developer-Key: i=yasin.lee.x@gmail.com; a=openpgp; fpr=CCEBEC056F25E1BC53FB4568590EF10E7C76BB99 When hardware design introduces significant sensor data noise, performance can be improved by adjusting register settings. Signed-off-by: Yasin Lee --- .../bindings/iio/proximity/tyhx,hx9023s.yaml | 19 +++++++++++++++= ++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/proximity/tyhx,hx9023s.y= aml b/Documentation/devicetree/bindings/iio/proximity/tyhx,hx9023s.yaml index 64ce8bc8bd36..0673c40472bd 100644 --- a/Documentation/devicetree/bindings/iio/proximity/tyhx,hx9023s.yaml +++ b/Documentation/devicetree/bindings/iio/proximity/tyhx,hx9023s.yaml @@ -28,6 +28,18 @@ properties: =20 vdd-supply: true =20 + tyhx,performance-tuning: + description: + Optional, When hardware design introduces significant sensor data no= ise, + performance can be improved by adjusting register settings, including + but not limited to sample integration time and average sample count. + Performance tuning parameters represented as register address-value = pairs. + The array consists of 8-bit values, where each pair represents a reg= ister + address followed by the value to be written to that register. + $ref: /schemas/types.yaml#/definitions/uint8-array + minItems: 2 + maxItems: 512 + "#address-cells": const: 1 =20 @@ -65,6 +77,13 @@ examples: interrupt-parent =3D <&pio>; interrupts =3D <16 IRQ_TYPE_EDGE_FALLING>; vdd-supply =3D <&pp1800_prox>; + tyhx,performance-tuning =3D [00 00 + 02 17 + 0D 44 + 0E 44 + 0F 04 + 1F 65 + 21 65]; =20 #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.43.0