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For QM/QXP, the 4 power domains are: DSP, DSP_RAM, MU13A, MU13B. First off, drop MU13A from the count. This is attached to the platform device of lsio_mu13. This decreases the count to 3. Secondly, drop DSP and DSP_RAM from the count for QXP. These are attached to the platform devices of the lpcgs (used as clock providers for the DSP). With this in mind, the number of required power domains for QXP is 1 (MU13B), while for QM it's 3 (MU13B, DSP, DSP_RAM). Additionally, two extra power domains may be required in the case of QM/QXP DSPs. These are IRQSTR_DSP and MU2A. For the nodes using the "-hifi4" compatibles these PDs are optional, while for nodes using the "-dsp" compatibles these are mandatory. These changes reflect all of this information. Signed-off-by: Laurentiu Mihalcea --- .../devicetree/bindings/dsp/fsl,dsp.yaml | 62 +++++++++++++++---- 1 file changed, 49 insertions(+), 13 deletions(-) diff --git a/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml b/Documenta= tion/devicetree/bindings/dsp/fsl,dsp.yaml index 9af40da5688e..e2f016af1048 100644 --- a/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml +++ b/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml @@ -51,8 +51,6 @@ properties: description: List of phandle and PM domain specifier as documented in Documentation/devicetree/bindings/power/power_domain.txt - minItems: 1 - maxItems: 4 =20 mboxes: description: @@ -97,16 +95,55 @@ allOf: properties: compatible: contains: - enum: - - fsl,imx8qxp-dsp - - fsl,imx8qm-dsp - - fsl,imx8qxp-hifi4 - - fsl,imx8qm-hifi4 + const: fsl,imx8qxp-hifi4 then: properties: power-domains: - minItems: 4 - else: + maxItems: 3 + + - if: + properties: + compatible: + contains: + const: fsl,imx8qxp-dsp + then: + properties: + power-domains: + minItems: 3 + maxItems: 3 + + - if: + properties: + compatible: + contains: + const: fsl,imx8qm-dsp + then: + properties: + power-domains: + minItems: 5 + maxItems: 5 + + - if: + properties: + compatible: + contains: + const: fsl,imx8qm-hifi4 + then: + properties: + power-domains: + minItems: 3 + maxItems: 5 + + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8mp-dsp + - fsl,imx8mp-hifi4 + - fsl,imx8ulp-dsp + - fsl,imx8ulp-hifi4 + then: properties: power-domains: maxItems: 1 @@ -157,10 +194,9 @@ examples: <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>, <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>; 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Wed, 25 Sep 2024 16:21:03 -0700 (PDT) From: Laurentiu Mihalcea To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Daniel Baluta , Shengjiu Wang , Iuliana Prodan Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 2/6] dt-bindings: arm: arm,mhuv2: remove power domain from example client node Date: Wed, 25 Sep 2024 19:20:04 -0400 Message-Id: <20240925232008.205802-3-laurentiumihalcea111@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240925232008.205802-1-laurentiumihalcea111@gmail.com> References: <20240925232008.205802-1-laurentiumihalcea111@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Laurentiu Mihalcea The number of power domains required for DT nodes using the 'fsl,imx8qxp-dsp' compatible is 3. Remove one power domain from the example client node using this compatible to align with this. Signed-off-by: Laurentiu Mihalcea --- Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml b/Doc= umentation/devicetree/bindings/mailbox/arm,mhuv2.yaml index a4f1fe63659a..9e878c028036 100644 --- a/Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml +++ b/Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml @@ -197,7 +197,7 @@ examples: reg =3D <0 0x596e8000 0 0x88000>; clocks =3D <&adma_lpcg 0>, <&adma_lpcg 1>, <&adma_lpcg 2>; clock-names =3D "ipg", "ocram", "core"; - power-domains =3D <&pd 0>, <&pd 1>, <&pd 2>, <&pd 3>; + power-domains =3D <&pd 0>, <&pd 1>, <&pd 2>; mbox-names =3D "txdb0", "txdb1", "rxdb0", "rxdb1"; mboxes =3D <&mhu_tx 2 0>, //data-transfer protocol with 5 wind= ows, mhu-tx <&mhu_tx 3 0>, //data-transfer protocol with 7 window= s, mhu-tx --=20 2.34.1 From nobody Fri Nov 29 00:39:00 2024 Received: from mail-ed1-f45.google.com (mail-ed1-f45.google.com [209.85.208.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE2961A3BDA; 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charset="utf-8" From: Laurentiu Mihalcea Currently, the dsp node is configured for SOF usage, which is not the "default" case and should be done in a separate SOF DTS. As such, configure the dsp node for rproc usage, which is the "default" case. This also includes the addition of the 2 optional power domains which may be required by some applications. Signed-off-by: Laurentiu Mihalcea --- .../boot/dts/freescale/imx8-ss-audio.dtsi | 20 +++++++++---------- arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 15 +++++++++++++- arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 19 ++++++++++++++++++ 3 files changed, 42 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi b/arch/arm64/= boot/dts/freescale/imx8-ss-audio.dtsi index ff5df0fed9e9..28970211dd67 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi @@ -431,22 +431,20 @@ dsp_ram_lpcg: clock-controller@59590000 { }; =20 dsp: dsp@596e8000 { - compatible =3D "fsl,imx8qxp-dsp"; + compatible =3D "fsl,imx8qxp-hifi4"; reg =3D <0x596e8000 0x88000>; clocks =3D <&dsp_lpcg IMX_LPCG_CLK_5>, <&dsp_ram_lpcg IMX_LPCG_CLK_4>, <&dsp_lpcg IMX_LPCG_CLK_7>; clock-names =3D "ipg", "ocram", "core"; - power-domains =3D <&pd IMX_SC_R_MU_13A>, - <&pd IMX_SC_R_MU_13B>, - <&pd IMX_SC_R_DSP>, - <&pd IMX_SC_R_DSP_RAM>; - mbox-names =3D "txdb0", "txdb1", - "rxdb0", "rxdb1"; - mboxes =3D <&lsio_mu13 2 0>, - <&lsio_mu13 2 1>, - <&lsio_mu13 3 0>, - <&lsio_mu13 3 1>; + power-domains =3D <&pd IMX_SC_R_MU_13B>, + <&pd IMX_SC_R_IRQSTR_DSP>, + <&pd IMX_SC_R_MU_2A>; + mbox-names =3D "tx", "rx", "rxdb"; + mboxes =3D <&lsio_mu13 0 0>, + <&lsio_mu13 1 0>, + <&lsio_mu13 3 0>; + firmware-name =3D "imx/dsp/hifi4.bin"; status =3D "disabled"; }; =20 diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boo= t/dts/freescale/imx8qxp-mek.dts index 936ba5ecdcac..527933a3eb5c 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -63,7 +63,8 @@ sound-wm8960 { }; =20 &dsp { - memory-region =3D <&dsp_reserved>; + memory-region =3D <&dsp_vdev0buffer>, <&dsp_vdev0vring0>, + <&dsp_vdev0vring1>, <&dsp_reserved>; status =3D "okay"; }; =20 @@ -71,6 +72,18 @@ &dsp_reserved { status =3D "okay"; }; =20 +&dsp_vdev0buffer { + status =3D "okay"; +}; + +&dsp_vdev0vring0 { + status =3D "okay"; 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charset="utf-8" From: Laurentiu Mihalcea On i.MX8QM, the DSP is in the VPU subsystem, which means that using the 'dsp' node from 'imx8-ss-audio.dtsi' is wrong as it's placed under the wrong bus. As such, drop it. Signed-off-by: Laurentiu Mihalcea --- arch/arm64/boot/dts/freescale/imx8qm.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dt= s/freescale/imx8qm.dtsi index 3ee6e2869e3c..f8b577ebdbef 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -603,3 +603,5 @@ mipi_pll_div2_clk: clock-controller-mipi-div2-pll { #include "imx8qm-ss-audio.dtsi" #include "imx8qm-ss-lvds.dtsi" #include "imx8qm-ss-mipi.dtsi" + +/delete-node/ &dsp; --=20 2.34.1 From nobody Fri Nov 29 00:39:00 2024 Received: from mail-ed1-f49.google.com (mail-ed1-f49.google.com [209.85.208.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7DFDD1A4B7A; Wed, 25 Sep 2024 23:21:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.49 ARC-Seal: i=1; a=rsa-sha256; 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charset="utf-8" From: Laurentiu Mihalcea Add DT node for i.MX8QM's DSP, which is found in the VPU subsystem. Signed-off-by: Laurentiu Mihalcea --- arch/arm64/boot/dts/freescale/imx8qm.dtsi | 27 +++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dt= s/freescale/imx8qm.dtsi index f8b577ebdbef..ae0165a44dcd 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -581,6 +581,33 @@ mipi_pll_div2_clk: clock-controller-mipi-div2-pll { clock-output-names =3D "mipi_pll_div2_clk"; }; =20 + vpu_subsys_dsp: bus@55000000 { + compatible =3D "simple-bus"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x55000000 0x0 0x55000000 0x1000000>; + + vpu_dsp: dsp@556e8000 { + compatible =3D "fsl,imx8qm-hifi4"; + reg =3D <0x556e8000 0x88000>; + clocks =3D <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + clock-names =3D "ipg", "ocram", "core"; + power-domains =3D <&pd IMX_SC_R_MU_13B>, + <&pd IMX_SC_R_DSP>, + <&pd IMX_SC_R_DSP_RAM>, + <&pd IMX_SC_R_IRQSTR_DSP>, + <&pd IMX_SC_R_MU_2A>; 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Wed, 25 Sep 2024 16:21:15 -0700 (PDT) From: Laurentiu Mihalcea To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Daniel Baluta , Shengjiu Wang , Iuliana Prodan Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 6/6] arm64: dts: imx8qm: enable dsp node for rproc usage Date: Wed, 25 Sep 2024 19:20:08 -0400 Message-Id: <20240925232008.205802-7-laurentiumihalcea111@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240925232008.205802-1-laurentiumihalcea111@gmail.com> References: <20240925232008.205802-1-laurentiumihalcea111@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Laurentiu Mihalcea Set the status of the dsp node to "okay" and assign and add its reserved memory regions. Signed-off-by: Laurentiu Mihalcea --- arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 27 ++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot= /dts/freescale/imx8qm-mek.dts index 62203eed6a6c..7ee69ce7b193 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -92,6 +92,27 @@ vdevbuffer: memory@90400000 { reg =3D <0 0x90400000 0 0x100000>; no-map; }; + + dsp_reserved: dsp@92400000 { + reg =3D <0 0x92400000 0 0x1000000>; + no-map; + }; + + dsp_vdev0vring0: vdev0vring0@942f0000 { + reg =3D <0 0x942f0000 0 0x8000>; + no-map; + }; + + dsp_vdev0vring1: vdev0vring1@942f8000 { + reg =3D <0 0x942f8000 0 0x8000>; + no-map; + }; + + dsp_vdev0buffer: vdev0buffer@94300000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x94300000 0 0x100000>; + no-map; + }; }; =20 lvds_backlight0: backlight-lvds0 { @@ -640,6 +661,12 @@ &sai7 { status =3D "okay"; }; =20 +&vpu_dsp { + memory-region =3D <&dsp_vdev0buffer>, <&dsp_vdev0vring0>, + <&dsp_vdev0vring1>, <&dsp_reserved>; + status =3D "okay"; +}; + &iomuxc { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_hog>; --=20 2.34.1