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Wed, 25 Sep 2024 06:42:05 -0500 From: Amit Kumar Mahapatra To: , , , CC: , , , , , , Amit Kumar Mahapatra Subject: [PATCH v2] dt-bindings: spi: zynqmp-qspi: Include two 'reg' properties only for the Zynq UltraScale QSPI Date: Wed, 25 Sep 2024 17:12:03 +0530 Message-ID: <20240925114203.2234735-1-amit.kumar-mahapatra@amd.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB05.amd.com: amit.kumar-mahapatra@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004684:EE_|SN7PR12MB6669:EE_ X-MS-Office365-Filtering-Correlation-Id: d6521310-d77f-496f-6d1e-08dcdd5717b4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?OhYttNbCTcEBUKxgonPq+83rHXQdYXH9HcRdgpaudoACmdCxntQRElM9WQDc?= =?us-ascii?Q?TLaN1n+1pPMeTGJktiRbYTrqz0BIJGkW6BTMEwqeV68oETGvejEBtvW1hFhh?= =?us-ascii?Q?vkVL+WMlMk/6WRDGv9N1ZUe2FiOwtsJh/wWOkZW8vbvCgvzkhGGr5yWY8i6Q?= =?us-ascii?Q?pmx+WIfDCQgWTzfJoMQ8gulAX47NSwnqePh3Lz7vGkq3g09aQPMjlE2D6NMR?= =?us-ascii?Q?TkqVnh5tqWyWyA017vobSzekhLdiN88JS6hCgvaw6dZZxwODk+9ae4acuGYx?= =?us-ascii?Q?/JrTid6vb9B8O1RRyCXISxOog76hUSGo/2wpAogRJEnxFCJY7Iy/fXi/z+nD?= =?us-ascii?Q?r/BPDPAv9ndAHzkeBHkIyyFluecgGurzKhaap1wy0Nmkp3555Ah94QwUDYlA?= =?us-ascii?Q?CMS0F4IFQwbMCL+ZyuPdvzXm3QjuepeQnyL9b0YpRggY8p87kfSJTGjcmvf3?= =?us-ascii?Q?HTgBnkZderEVSbqIAcoCX38nCPOGTW3RlvmeK0Qeo7uJYJZQQTCGHamaul87?= =?us-ascii?Q?nezo4JO+7OCjTIl9ejMrcANiM18bbSgOztLHdwas690+04AJx6GL+Pl/hGFy?= =?us-ascii?Q?FobqWXmQpAEjBdg0FB0d0fxd+wy8XGer+Ey4N0fSdgg8irGZvBx6/TU3be2F?= =?us-ascii?Q?UdKGlDfn04zKfAsphJFDNxwh9TVEDysc/kVHAf5o74Yv/FogZRfdt/fbplay?= =?us-ascii?Q?eYJMR1cl0a3mtrdr1baON5GncY7Qxcbk7cYqQjuO7W7RzcmGrqYnS+5g+QpG?= =?us-ascii?Q?vMQUEaN2vkGEID0eZnOUUvmLrFMlomtzHNcfVULOFiTWlNA4FqGoy3+BkogA?= =?us-ascii?Q?tgzSIQohW+KfQssl2y4yRAG8xu4eQSQqoXQlWZ/R909B4tv8DUloaxwMrwpF?= =?us-ascii?Q?XqDv+2vDswbJhOAzvwbG2wp7svhGxBz6XYTuFYars07HuUawI9zK9O+/cJJA?= =?us-ascii?Q?kgZgKnpieI2hpT1CR1l1FtBOOtnqZrUf67KXVRgMySpEJaeyfVOwbEie/aiY?= =?us-ascii?Q?45peiKRROEZC8imABKDv6fX+ZA0grEtXDxaRNi8Wn4Efde7+Rst6Qp5/8hzQ?= =?us-ascii?Q?c85YRVSvkWJY+FtM1H20Vqx5VUzQJHEiyZ+tbqrlu1kx54skT6zJewe/E9Ma?= =?us-ascii?Q?MZuoPsCkEvnGdP2eG9tKhiOE5CfLM7MiOhFhikh+DKsp/LoqJMCV16eCesXp?= =?us-ascii?Q?zFiWp20gmIHVtC5rA6MDPSFaF3VSxA1DdUJjXkxbVXqje/4X4NgkcRegMV6g?= =?us-ascii?Q?L4vpN+2rSJVsxUsfYAX5AdqAxbmfwYOA9ibYAapjvmyzcbwmud/Q1NR298dC?= =?us-ascii?Q?qQfzt0yOL6UW9ipbXDlGa9oyuKpbuegY06ZKUtLKZ27h/mQRixgHtMMaYw7m?= =?us-ascii?Q?EVaORetkCLotqKS+d7nUyrPKZj/f?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Sep 2024 11:42:10.8580 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d6521310-d77f-496f-6d1e-08dcdd5717b4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004684.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6669 Content-Type: text/plain; charset="utf-8" Linear mode is only supported by the Zynq UltraScale QSPI controller, so update the bindings to include two 'reg' properties only for the Zynq UltraScale QSPI controller. Signed-off-by: Amit Kumar Mahapatra Reviewed-by: Krzysztof Kozlowski --- BRANCH: for-next Changes in v2: - In the if block changed 'maxItems' to 'minItems'. - Retained 'reg' property definition and added 'minItems'. - Moved the allOf block down to the end of the binding. --- .../bindings/spi/spi-zynqmp-qspi.yaml | 22 ++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml b/D= ocumentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml index e5199b109dad..04d4d3b4916d 100644 --- a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml @@ -9,9 +9,6 @@ title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller maintainers: - Michal Simek =20 -allOf: - - $ref: spi-controller.yaml# - properties: compatible: enum: @@ -19,6 +16,7 @@ properties: - xlnx,zynqmp-qspi-1.0 =20 reg: + minItems: 1 maxItems: 2 =20 interrupts: @@ -47,6 +45,24 @@ required: =20 unevaluatedProperties: false =20 +allOf: + - $ref: spi-controller.yaml# + + - if: + properties: + compatible: + contains: + const: xlnx,zynqmp-qspi-1.0 + then: + properties: + reg: + minItems: 2 + + else: + properties: + reg: + maxItems: 1 + examples: - | #include --=20 2.34.1