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Add one more nested power-domain layer to pass the check. Acked-by: Rob Herring (Arm) Signed-off-by: Fei Shao --- .../devicetree/bindings/power/mediatek,power-controller.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/power/mediatek,power-control= ler.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controlle= r.yaml index 8985e2df8a56..a7df4041b745 100644 --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml @@ -54,6 +54,10 @@ patternProperties: patternProperties: "^power-domain@[0-9a-f]+$": $ref: "#/$defs/power-domain-node" + patternProperties: + "^power-domain@[0-9a-f]+$": + $ref: "#/$defs/power-domain-node" + unevaluatedProperties: false unevaluatedProperties: false unevaluatedProperties: false unevaluatedProperties: false --=20 2.46.0.792.g87dc391469-goog From nobody Fri Nov 29 02:58:16 2024 Received: from mail-pf1-f169.google.com (mail-pf1-f169.google.com [209.85.210.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E2BA216F908 for ; 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Wed, 25 Sep 2024 04:01:28 -0700 (PDT) Received: from fshao-p620.tpe.corp.google.com ([2401:fa00:1:10:2b86:78b6:8ebc:e17a]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7e6b7c73085sm2570298a12.59.2024.09.25.04.01.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Sep 2024 04:01:28 -0700 (PDT) From: Fei Shao To: AngeloGioacchino Del Regno Cc: Fei Shao , Bjorn Helgaas , Conor Dooley , Jianjun Wang , Krzysztof Kozlowski , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Lorenzo Bianconi , Lorenzo Pieralisi , Manivannan Sadhasivam , Matthias Brugger , Rob Herring , Ryder Lee , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-pci@vger.kernel.org Subject: [PATCH 2/6] dt-bindings: PCI: mediatek-gen3: Allow exact number of clocks only Date: Wed, 25 Sep 2024 18:57:46 +0800 Message-ID: <20240925110044.3678055-3-fshao@chromium.org> X-Mailer: git-send-email 2.46.0.792.g87dc391469-goog In-Reply-To: <20240925110044.3678055-1-fshao@chromium.org> References: <20240925110044.3678055-1-fshao@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In MediaTek PCIe gen3 bindings, "clocks" accepts a range of 1-6 clocks across all SoCs. But in practice, each SoC requires a particular number of clocks as defined in "clock-names", and the length of "clocks" and "clock-names" can be inconsistent with current bindings. For example: - MT8188, MT8192 and MT8195 all require 6 clocks, while the bindings accept 4-6 clocks. - MT7986 requires 4 clocks, while the bindings accept 4-6 clocks. Update minItems and maxItems properties for individual SoCs as needed to only accept the correct number of clocks. Fixes: c6abd0eadec6 ("dt-bindings: PCI: mediatek-gen3: Add support for Airo= ha EN7581") Signed-off-by: Fei Shao Acked-by: Bjorn Helgaas Reviewed-by: Krzysztof Kozlowski reviewed-by for v6.13, thank you! --- .../devicetree/bindings/pci/mediatek-pcie-gen3.yaml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml = b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml index 898c1be2d6a4..f05aab2b1add 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml @@ -149,7 +149,7 @@ allOf: then: properties: clocks: - minItems: 4 + minItems: 6 =20 clock-names: items: @@ -178,7 +178,7 @@ allOf: then: properties: clocks: - minItems: 4 + minItems: 6 =20 clock-names: items: @@ -207,6 +207,7 @@ allOf: properties: clocks: minItems: 4 + maxItems: 4 =20 clock-names: items: --=20 2.46.0.792.g87dc391469-goog From nobody Fri Nov 29 02:58:16 2024 Received: from mail-pf1-f182.google.com (mail-pf1-f182.google.com [209.85.210.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B1D4E1741C0 for ; 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Wed, 25 Sep 2024 04:01:32 -0700 (PDT) Received: from fshao-p620.tpe.corp.google.com ([2401:fa00:1:10:2b86:78b6:8ebc:e17a]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7e6b7c73085sm2570298a12.59.2024.09.25.04.01.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Sep 2024 04:01:30 -0700 (PDT) From: Fei Shao To: AngeloGioacchino Del Regno Cc: Fei Shao , Conor Dooley , Krzysztof Kozlowski , Matthias Brugger , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH 3/6] arm64: dts: mediatek: mt8188: Define CPU big core cluster Date: Wed, 25 Sep 2024 18:57:47 +0800 Message-ID: <20240925110044.3678055-4-fshao@chromium.org> X-Mailer: git-send-email 2.46.0.792.g87dc391469-goog In-Reply-To: <20240925110044.3678055-1-fshao@chromium.org> References: <20240925110044.3678055-1-fshao@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MT8188 SoC features two CPU clusters: one with 6 little Cortex-A55 cores, and the other with 2 big Cortex-A78 cores. Update the CPU topology to reflect the actual hardware configurations. Signed-off-by: Fei Shao --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index cd27966d2e3c..51bf08b2ff9b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -195,12 +195,14 @@ core4 { core5 { cpu =3D <&cpu5>; }; + }; =20 - core6 { + cluster1 { + core0 { cpu =3D <&cpu6>; }; =20 - core7 { + core1 { cpu =3D <&cpu7>; }; }; --=20 2.46.0.792.g87dc391469-goog From nobody Fri Nov 29 02:58:16 2024 Received: from mail-pf1-f177.google.com (mail-pf1-f177.google.com [209.85.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E5101474CE for ; Wed, 25 Sep 2024 11:01:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.177 ARC-Seal: i=1; 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Wed, 25 Sep 2024 04:01:34 -0700 (PDT) From: Fei Shao To: AngeloGioacchino Del Regno Cc: Fei Shao , Conor Dooley , Krzysztof Kozlowski , Matthias Brugger , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH 4/6] arm64: dts: mediatek: mt8188: Add missing dma-ranges to soc node Date: Wed, 25 Sep 2024 18:57:48 +0800 Message-ID: <20240925110044.3678055-5-fshao@chromium.org> X-Mailer: git-send-email 2.46.0.792.g87dc391469-goog In-Reply-To: <20240925110044.3678055-1-fshao@chromium.org> References: <20240925110044.3678055-1-fshao@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the missing dma-ranges property to the soc node, similar to how it was done for MT8195 and MT8192. This allows the entire 16GB of iova range to be used and enables multimedia processing usages, like vcodec and MIPI camera. Signed-off-by: Fei Shao Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index 51bf08b2ff9b..ff5c8e0597f9 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -880,6 +880,7 @@ soc { #address-cells =3D <2>; #size-cells =3D <2>; compatible =3D "simple-bus"; + dma-ranges =3D <0x0 0x0 0x0 0x0 0x4 0x0>; ranges; =20 gic: interrupt-controller@c000000 { --=20 2.46.0.792.g87dc391469-goog From nobody Fri Nov 29 02:58:16 2024 Received: from mail-pf1-f182.google.com (mail-pf1-f182.google.com [209.85.210.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B7A9E188A06 for ; Wed, 25 Sep 2024 11:01:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.182 ARC-Seal: i=1; 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Wed, 25 Sep 2024 04:01:37 -0700 (PDT) From: Fei Shao To: AngeloGioacchino Del Regno Cc: Fei Shao , Conor Dooley , Krzysztof Kozlowski , Matthias Brugger , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH 5/6] arm64: dts: mediatek: mt8188: Move vdec1 power domain under vdec0 Date: Wed, 25 Sep 2024 18:57:49 +0800 Message-ID: <20240925110044.3678055-6-fshao@chromium.org> X-Mailer: git-send-email 2.46.0.792.g87dc391469-goog In-Reply-To: <20240925110044.3678055-1-fshao@chromium.org> References: <20240925110044.3678055-1-fshao@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There are two hardware IP blocks in MT8188 video decoder pipeline: vdec-lat and vdec-core, which are powered by vdec0 and vdec1 power domains respectively. We noticed that vdec-core needs to be powered down before vdec-lat during suspend to prevent failures. It's unclear if it's an intended hardware design or due to power isolation glitch. But in any case, we observed a power-off sequence here, and it can be considered as an indirect dependency implication between the vdec0 and vdec1 domains. Given that, update vdec1 as a sub-domain of vdec0 to enforce the sequence. Also, use more specific clock names for both power domains. Signed-off-by: Fei Shao --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index ff5c8e0597f9..a6cd08ea74eb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -1064,20 +1064,22 @@ power-domain@MT8188_POWER_DOMAIN_VPPSYS1 { #power-domain-cells =3D <0>; }; =20 - power-domain@MT8188_POWER_DOMAIN_VDEC1 { - reg =3D ; - clocks =3D <&vdecsys CLK_VDEC2_LARB1>; - clock-names =3D "ss-vdec"; - mediatek,infracfg =3D <&infracfg_ao>; - #power-domain-cells =3D <0>; - }; - power-domain@MT8188_POWER_DOMAIN_VDEC0 { reg =3D ; clocks =3D <&vdecsys_soc CLK_VDEC1_SOC_LARB1>; - clock-names =3D "ss-vdec"; + clock-names =3D "ss-vdec1-soc-l1"; mediatek,infracfg =3D <&infracfg_ao>; - #power-domain-cells =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@MT8188_POWER_DOMAIN_VDEC1 { + reg =3D ; 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charset="utf-8" The MediaTek mmsys is more than just a clock controller; it's a system controller. In addition to clock controls, it provides display pipeline routing controls and other miscellaneous control registers. On the MT8188 and MT8195 SoCs, the mmsys blocks utilize the same mmsys driver but have been aliased to "vdosys" and "vppsys", likely to better represent their actual functionality. Update the vppsys node names and compatibles in MT8188 DT to reflect that and fix dtbs_check errors against mediatek/mt8188-evb.dtb. Signed-off-by: Fei Shao Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index a6cd08ea74eb..98ba3485a8bd 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -1783,8 +1783,8 @@ mfgcfg: clock-controller@13fbf000 { #clock-cells =3D <1>; }; =20 - vppsys0: clock-controller@14000000 { - compatible =3D "mediatek,mt8188-vppsys0"; + vppsys0: syscon@14000000 { + compatible =3D "mediatek,mt8188-vppsys0", "syscon"; reg =3D <0 0x14000000 0 0x1000>; #clock-cells =3D <1>; }; @@ -1801,8 +1801,8 @@ wpesys_vpp0: clock-controller@14e02000 { #clock-cells =3D <1>; }; =20 - vppsys1: clock-controller@14f00000 { - compatible =3D "mediatek,mt8188-vppsys1"; + vppsys1: syscon@14f00000 { + compatible =3D "mediatek,mt8188-vppsys1", "syscon"; reg =3D <0 0x14f00000 0 0x1000>; #clock-cells =3D <1>; }; --=20 2.46.0.792.g87dc391469-goog