From nobody Fri Nov 29 03:39:28 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D46613A884 for ; Wed, 25 Sep 2024 10:19:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727259576; cv=none; b=q62WZFCeLuRiYc9ItxO2dJlhrP3X7BZinGBHtFECmGldoq1fvZUthur4TKcPw/WdjWZHkOAvqVLAypx82AqI19t6+Q1gzRKWQQ8536FbmfzIY4vVs8knworJj+ng6eUOD02vDT2iLxbY1HbCiL+x1v4LfiXm+6tUakjJjGD2rGM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727259576; c=relaxed/simple; bh=P8fWp9wrH1M4T/6xu0weHkak9mP60R/bWhToEDUpbmA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=WaoWd5q+3cKITsn9f0K2Fv3Z0okD1/zQnh+B0ziCva/sjX7mSXPtNyl3Kdpuwo0o5lHDLC7eOqfZWPdhYPLI8yz2jx6R+wwz2265mAC7+Bk85nTfHEaGNmYUdpytQ1J3QxHkgrPsgSOoHaZ9SXYTYrWf8XuqeBonx2BQWgf0QEY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=OQtds6+1; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="OQtds6+1" X-UUID: a6c26bec7b2711efb66947d174671e26-20240925 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=IDDoq6n155yp2huL1be1iYeaanZR0hGeY9yLalpGtL0=; b=OQtds6+1xZXNo/odhQORZ+4ekf0xe5cCdMKPh4bAbvb+AQf+IxO52LX15qIYxc4Esm1wJ1XQ6mu2TbYxkKnhrSkgHvcHv9h/w6bIPSVV+jfXDj71+L5VnjiCoj79xUMWuILDFVRkvnTF74TBNZotX8nmtpIWpV0Y7ai7vo/EpvU=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.41,REQID:40d4b041-6419-4c0b-9aed-87f6ff47f0a7,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:6dc6a47,CLOUDID:48ff8a9e-8e9a-4ac1-b510-390a86b53c0a,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES :1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: a6c26bec7b2711efb66947d174671e26-20240925 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1647118905; Wed, 25 Sep 2024 18:19:30 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 25 Sep 2024 18:19:28 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 25 Sep 2024 18:19:28 +0800 From: Jason-JH.Lin To: Alper Nebi Yasak , Chun-Kuang Hu , AngeloGioacchino Del Regno CC: Shawn Sung , , , , , "Jason-JH . Lin" , Singo Chang , Nancy Lin , Subject: [PATCH v5 1/2] drm/mediatek: ovl: Add fmt_convert function pointer to driver data Date: Wed, 25 Sep 2024 18:19:26 +0800 Message-ID: <20240925101927.17042-2-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240925101927.17042-1-jason-jh.lin@mediatek.com> References: <20240925101927.17042-1-jason-jh.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" OVL_CON_CLRFMT_MAN is a configuration for extending color format settings of DISP_REG_OVL_CON(n). It will change some of the original color format settings. Take the settings of (3 << 12) for example. - If OVL_CON_CLRFMT_MAN =3D 0 means OVL_CON_CLRFMT_RGBA8888. - If OVL_CON_CLRFMT_MAN =3D 1 means OVL_CON_CLRFMT_PARGB8888. Since OVL_CON_CLRFMT_MAN is not supported on previous SoCs, It breaks the OVL color format setting of MT8173. Therefore, the fmt_convert function pointer is added to the driver data and mtk_ovl_fmt_convert_with_blend is implemented for MT8192 and MT8195 that support OVL_CON_CLRFMT_MAN, and mtk_ovl_fmt_convert is implemented for other SoCs that do not support it to solve the degradation problem. Fixes: a3f7f7ef4bfe ("drm/mediatek: Support "Pre-multiplied" blending in OV= L") Signed-off-by: Jason-JH.Lin Tested-by: Alper Nebi Yasak Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 68 ++++++++++++++++++++++--- 1 file changed, 61 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 89b439dcf3a6..8f7b7e07aeb1 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -143,6 +143,7 @@ struct mtk_disp_ovl_data { unsigned int addr; unsigned int gmc_bits; unsigned int layer_nr; + unsigned int (*fmt_convert)(struct device *dev, struct mtk_plane_state *s= tate); bool fmt_rgb565_is_0; bool smi_id_en; bool supports_afbc; @@ -386,13 +387,59 @@ void mtk_ovl_layer_off(struct device *dev, unsigned i= nt idx, DISP_REG_OVL_RDMA_CTRL(idx)); } =20 -static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int= fmt, - unsigned int blend_mode) +static unsigned int mtk_ovl_fmt_convert(struct device *dev, struct mtk_pla= ne_state *state) { - /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX" - * is defined in mediatek HW data sheet. - * The alphabet order in XXX is no relation to data - * arrangement in memory. + struct mtk_disp_ovl *ovl =3D dev_get_drvdata(dev); + unsigned int fmt =3D state->pending.format; + + switch (fmt) { + default: + case DRM_FORMAT_RGB565: + return OVL_CON_CLRFMT_RGB565(ovl); + case DRM_FORMAT_BGR565: + return OVL_CON_CLRFMT_RGB565(ovl) | OVL_CON_BYTE_SWAP; + case DRM_FORMAT_RGB888: + return OVL_CON_CLRFMT_RGB888(ovl); + case DRM_FORMAT_BGR888: + return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP; + case DRM_FORMAT_RGBX8888: + case DRM_FORMAT_RGBA8888: + case DRM_FORMAT_RGBX1010102: + case DRM_FORMAT_RGBA1010102: + return OVL_CON_CLRFMT_RGBA8888; + case DRM_FORMAT_BGRX8888: + case DRM_FORMAT_BGRA8888: + case DRM_FORMAT_BGRX1010102: + case DRM_FORMAT_BGRA1010102: + return OVL_CON_CLRFMT_BGRA8888; + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_XRGB2101010: + case DRM_FORMAT_ARGB2101010: + return OVL_CON_CLRFMT_ARGB8888; + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_ABGR8888: + case DRM_FORMAT_XBGR2101010: + case DRM_FORMAT_ABGR2101010: + return OVL_CON_CLRFMT_ABGR8888; + case DRM_FORMAT_UYVY: + return OVL_CON_CLRFMT_UYVY | OVL_CON_MTX_YUV_TO_RGB; + case DRM_FORMAT_YUYV: + return OVL_CON_CLRFMT_YUYV | OVL_CON_MTX_YUV_TO_RGB; + } +} + +static unsigned int mtk_ovl_fmt_convert_with_blend(struct device *dev, + struct mtk_plane_state *state) +{ + struct mtk_disp_ovl *ovl =3D dev_get_drvdata(dev); + unsigned int fmt =3D state->pending.format; + unsigned int blend_mode =3D state->base.pixel_blend_mode; + + /* + * For the platforms where OVL_CON_CLRFMT_MAN is defined in the + * hardware data sheet and supports premultiplied color formats + * such as OVL_CON_CLRFMT_PARGB8888. */ switch (fmt) { default: @@ -471,7 +518,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned = int idx, return; } =20 - con =3D ovl_fmt_convert(ovl, fmt, blend_mode); + con =3D ovl->data->fmt_convert(dev, state); if (state->base.fb) { con |=3D OVL_CON_AEN; con |=3D state->base.alpha & OVL_CON_ALPHA; @@ -625,6 +672,7 @@ static const struct mtk_disp_ovl_data mt2701_ovl_driver= _data =3D { .addr =3D DISP_REG_OVL_ADDR_MT2701, .gmc_bits =3D 8, .layer_nr =3D 4, + .fmt_convert =3D mtk_ovl_fmt_convert, .fmt_rgb565_is_0 =3D false, .formats =3D mt8173_formats, .num_formats =3D ARRAY_SIZE(mt8173_formats), @@ -634,6 +682,7 @@ static const struct mtk_disp_ovl_data mt8173_ovl_driver= _data =3D { .addr =3D DISP_REG_OVL_ADDR_MT8173, .gmc_bits =3D 8, .layer_nr =3D 4, + .fmt_convert =3D mtk_ovl_fmt_convert, .fmt_rgb565_is_0 =3D true, .formats =3D mt8173_formats, .num_formats =3D ARRAY_SIZE(mt8173_formats), @@ -643,6 +692,7 @@ static const struct mtk_disp_ovl_data mt8183_ovl_driver= _data =3D { .addr =3D DISP_REG_OVL_ADDR_MT8173, .gmc_bits =3D 10, .layer_nr =3D 4, + .fmt_convert =3D mtk_ovl_fmt_convert, .fmt_rgb565_is_0 =3D true, .formats =3D mt8173_formats, .num_formats =3D ARRAY_SIZE(mt8173_formats), @@ -652,6 +702,7 @@ static const struct mtk_disp_ovl_data mt8183_ovl_2l_dri= ver_data =3D { .addr =3D DISP_REG_OVL_ADDR_MT8173, .gmc_bits =3D 10, .layer_nr =3D 2, + .fmt_convert =3D mtk_ovl_fmt_convert, .fmt_rgb565_is_0 =3D true, .formats =3D mt8173_formats, .num_formats =3D ARRAY_SIZE(mt8173_formats), @@ -661,6 +712,7 @@ static const struct mtk_disp_ovl_data mt8192_ovl_driver= _data =3D { .addr =3D DISP_REG_OVL_ADDR_MT8173, .gmc_bits =3D 10, .layer_nr =3D 4, + .fmt_convert =3D mtk_ovl_fmt_convert_with_blend, .fmt_rgb565_is_0 =3D true, .smi_id_en =3D true, .formats =3D mt8173_formats, @@ -671,6 +723,7 @@ static const struct mtk_disp_ovl_data mt8192_ovl_2l_dri= ver_data =3D { .addr =3D DISP_REG_OVL_ADDR_MT8173, .gmc_bits =3D 10, .layer_nr =3D 2, + .fmt_convert =3D mtk_ovl_fmt_convert_with_blend, .fmt_rgb565_is_0 =3D true, .smi_id_en =3D true, .formats =3D mt8173_formats, @@ -681,6 +734,7 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver= _data =3D { .addr =3D DISP_REG_OVL_ADDR_MT8173, .gmc_bits =3D 10, .layer_nr =3D 4, + .fmt_convert =3D mtk_ovl_fmt_convert_with_blend, .fmt_rgb565_is_0 =3D true, .smi_id_en =3D true, .supports_afbc =3D true, --=20 2.43.0 From nobody Fri Nov 29 03:39:28 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCAEF140E38 for ; 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Lin" , Singo Chang , "Nancy Lin" , Subject: [PATCH v5 2/2] drm/mediatek: Add blend_modes to mtk_plane_init() for different SoCs Date: Wed, 25 Sep 2024 18:19:27 +0800 Message-ID: <20240925101927.17042-3-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240925101927.17042-1-jason-jh.lin@mediatek.com> References: <20240925101927.17042-1-jason-jh.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--12.099800-8.000000 X-TMASE-MatchedRID: LFhZ4D3Qpaxe0FYiuVD/cPSZ/2axrnPBqQzUsXJNLuEGW3hFnC9N1R0h hGd4LdX+mSouTgBPZUd8ADwuiKcPjo6drwfS3MqJxQvMEFMAcCURvEpVd3vS1d9RlPzeVuQQIoh SIvsUL+/BfR/WU+6YOHOL9OTtf6MNg4jZH72x495c/msUC5wFQTFcf92WG8u/FLXUWU5hGiHu9+ Mep8zDYi3HX1fgk1LKuKSvVO9Kzes3+hnFgqdP4oSvKOGqLLPK1xODifxSLQObKItl61J/yZ+in TK0bC9eKrauXd3MZDUzaXOJNfDG7eerR+zZRY2Vmvy5hPqBnT1A0AYJ6FdmlGui6oIEpU60 X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--12.099800-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 7E0120F04BD04BAF96546765F76E0C0877D1DE509AEBE842A0334595B7E84D1D2000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since some SoCs support premultiplied pixel formats but some do not, the blend_modes parameter is added to mtk_plane_init(), which is obtained from the mtk_ddp_comp_get_blend_modes function implemented in different OVL components. The OVL component can use driver data to set the blend mode capabilities for different SoCs. Fixes: 4225d5d5e779 ("drm/mediatek: Support alpha blending in display drive= r") Signed-off-by: Jason-JH.Lin --- drivers/gpu/drm/mediatek/mtk_crtc.c | 1 + drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 2 ++ drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 10 ++++++++ drivers/gpu/drm/mediatek/mtk_disp_drv.h | 3 +++ drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 25 +++++++++++++++++++ .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 7 ++++++ drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 8 ++++++ drivers/gpu/drm/mediatek/mtk_plane.c | 9 +++---- drivers/gpu/drm/mediatek/mtk_plane.h | 4 +-- 9 files changed, 61 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.c b/drivers/gpu/drm/mediatek= /mtk_crtc.c index 175b00e5a253..b65f196f2015 100644 --- a/drivers/gpu/drm/mediatek/mtk_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_crtc.c @@ -913,6 +913,7 @@ static int mtk_crtc_init_comp_planes(struct drm_device = *drm_dev, BIT(pipe), mtk_crtc_plane_type(mtk_crtc->layer_nr, num_planes), mtk_ddp_comp_supported_rotations(comp), + mtk_ddp_comp_get_blend_modes(comp), mtk_ddp_comp_get_formats(comp), mtk_ddp_comp_get_num_formats(comp), i); if (ret) diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.c index be66d94be361..edc6417639e6 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c @@ -363,6 +363,7 @@ static const struct mtk_ddp_comp_funcs ddp_ovl =3D { .layer_config =3D mtk_ovl_layer_config, .bgclr_in_on =3D mtk_ovl_bgclr_in_on, .bgclr_in_off =3D mtk_ovl_bgclr_in_off, + .get_blend_modes =3D mtk_ovl_get_blend_modes, .get_formats =3D mtk_ovl_get_formats, .get_num_formats =3D mtk_ovl_get_num_formats, }; @@ -416,6 +417,7 @@ static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = =3D { .disconnect =3D mtk_ovl_adaptor_disconnect, .add =3D mtk_ovl_adaptor_add_comp, .remove =3D mtk_ovl_adaptor_remove_comp, + .get_blend_modes =3D mtk_ovl_adaptor_get_blend_modes, .get_formats =3D mtk_ovl_adaptor_get_formats, .get_num_formats =3D mtk_ovl_adaptor_get_num_formats, .mode_valid =3D mtk_ovl_adaptor_mode_valid, diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.h index ecf6dc283cd7..79562af1180f 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h @@ -80,6 +80,7 @@ struct mtk_ddp_comp_funcs { void (*ctm_set)(struct device *dev, struct drm_crtc_state *state); struct device * (*dma_dev_get)(struct device *dev); + const u32 (*get_blend_modes)(struct device *dev); const u32 *(*get_formats)(struct device *dev); size_t (*get_num_formats)(struct device *dev); void (*connect)(struct device *dev, struct device *mmsys_dev, unsigned in= t next); @@ -266,6 +267,15 @@ static inline struct device *mtk_ddp_comp_dma_dev_get(= struct mtk_ddp_comp *comp) return comp->dev; } =20 +static inline +const u32 mtk_ddp_comp_get_blend_modes(struct mtk_ddp_comp *comp) +{ + if (comp->funcs && comp->funcs->get_blend_modes) + return comp->funcs->get_blend_modes(comp->dev); + + return 0; +} + static inline const u32 *mtk_ddp_comp_get_formats(struct mtk_ddp_comp *comp) { diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/medi= atek/mtk_disp_drv.h index 082ac18fe04a..ea07b3b55b1c 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -103,6 +103,7 @@ void mtk_ovl_register_vblank_cb(struct device *dev, void mtk_ovl_unregister_vblank_cb(struct device *dev); void mtk_ovl_enable_vblank(struct device *dev); void mtk_ovl_disable_vblank(struct device *dev); +const u32 mtk_ovl_get_blend_modes(struct device *dev); const u32 *mtk_ovl_get_formats(struct device *dev); size_t mtk_ovl_get_num_formats(struct device *dev); =20 @@ -131,6 +132,7 @@ void mtk_ovl_adaptor_start(struct device *dev); void mtk_ovl_adaptor_stop(struct device *dev); unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev); struct device *mtk_ovl_adaptor_dma_dev_get(struct device *dev); +const u32 mtk_ovl_adaptor_get_blend_modes(struct device *dev); const u32 *mtk_ovl_adaptor_get_formats(struct device *dev); size_t mtk_ovl_adaptor_get_num_formats(struct device *dev); enum drm_mode_status mtk_ovl_adaptor_mode_valid(struct device *dev, @@ -165,6 +167,7 @@ void mtk_mdp_rdma_start(struct device *dev, struct cmdq= _pkt *cmdq_pkt); void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt *cmdq_pkt); void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg *cfg, struct cmdq_pkt *cmdq_pkt); +const u32 mtk_mdp_rdma_get_blend_modes(struct device *dev); const u32 *mtk_mdp_rdma_get_formats(struct device *dev); size_t mtk_mdp_rdma_get_num_formats(struct device *dev); =20 diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 8f7b7e07aeb1..864dc96aad01 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -147,6 +147,7 @@ struct mtk_disp_ovl_data { bool fmt_rgb565_is_0; bool smi_id_en; bool supports_afbc; + const u32 blend_modes; const u32 *formats; size_t num_formats; bool supports_clrfmt_ext; @@ -215,6 +216,13 @@ void mtk_ovl_disable_vblank(struct device *dev) writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_INTEN); } =20 +const u32 mtk_ovl_get_blend_modes(struct device *dev) +{ + struct mtk_disp_ovl *ovl =3D dev_get_drvdata(dev); + + return ovl->data->blend_modes; +} + const u32 *mtk_ovl_get_formats(struct device *dev) { struct mtk_disp_ovl *ovl =3D dev_get_drvdata(dev); @@ -674,6 +682,8 @@ static const struct mtk_disp_ovl_data mt2701_ovl_driver= _data =3D { .layer_nr =3D 4, .fmt_convert =3D mtk_ovl_fmt_convert, .fmt_rgb565_is_0 =3D false, + .blend_modes =3D BIT(DRM_MODE_BLEND_COVERAGE) | + BIT(DRM_MODE_BLEND_PIXEL_NONE), .formats =3D mt8173_formats, .num_formats =3D ARRAY_SIZE(mt8173_formats), }; @@ -684,6 +694,8 @@ static const struct mtk_disp_ovl_data mt8173_ovl_driver= _data =3D { .layer_nr =3D 4, .fmt_convert =3D mtk_ovl_fmt_convert, .fmt_rgb565_is_0 =3D true, + .blend_modes =3D BIT(DRM_MODE_BLEND_COVERAGE) | + BIT(DRM_MODE_BLEND_PIXEL_NONE), .formats =3D mt8173_formats, .num_formats =3D ARRAY_SIZE(mt8173_formats), }; @@ -694,6 +706,8 @@ static const struct mtk_disp_ovl_data mt8183_ovl_driver= _data =3D { .layer_nr =3D 4, .fmt_convert =3D mtk_ovl_fmt_convert, .fmt_rgb565_is_0 =3D true, + .blend_modes =3D BIT(DRM_MODE_BLEND_COVERAGE) | + BIT(DRM_MODE_BLEND_PIXEL_NONE), .formats =3D mt8173_formats, .num_formats =3D ARRAY_SIZE(mt8173_formats), }; @@ -704,6 +718,8 @@ static const struct mtk_disp_ovl_data mt8183_ovl_2l_dri= ver_data =3D { .layer_nr =3D 2, .fmt_convert =3D mtk_ovl_fmt_convert, .fmt_rgb565_is_0 =3D true, + .blend_modes =3D BIT(DRM_MODE_BLEND_COVERAGE) | + BIT(DRM_MODE_BLEND_PIXEL_NONE), .formats =3D mt8173_formats, .num_formats =3D ARRAY_SIZE(mt8173_formats), }; @@ -715,6 +731,9 @@ static const struct mtk_disp_ovl_data mt8192_ovl_driver= _data =3D { .fmt_convert =3D mtk_ovl_fmt_convert_with_blend, .fmt_rgb565_is_0 =3D true, .smi_id_en =3D true, + .blend_modes =3D BIT(DRM_MODE_BLEND_PREMULTI) | + BIT(DRM_MODE_BLEND_COVERAGE) | + BIT(DRM_MODE_BLEND_PIXEL_NONE), .formats =3D mt8173_formats, .num_formats =3D ARRAY_SIZE(mt8173_formats), }; @@ -726,6 +745,9 @@ static const struct mtk_disp_ovl_data mt8192_ovl_2l_dri= ver_data =3D { .fmt_convert =3D mtk_ovl_fmt_convert_with_blend, .fmt_rgb565_is_0 =3D true, .smi_id_en =3D true, + .blend_modes =3D BIT(DRM_MODE_BLEND_PREMULTI) | + BIT(DRM_MODE_BLEND_COVERAGE) | + BIT(DRM_MODE_BLEND_PIXEL_NONE), .formats =3D mt8173_formats, .num_formats =3D ARRAY_SIZE(mt8173_formats), }; @@ -738,6 +760,9 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver= _data =3D { .fmt_rgb565_is_0 =3D true, .smi_id_en =3D true, .supports_afbc =3D true, + .blend_modes =3D BIT(DRM_MODE_BLEND_PREMULTI) | + BIT(DRM_MODE_BLEND_COVERAGE) | + BIT(DRM_MODE_BLEND_PIXEL_NONE), .formats =3D mt8195_formats, .num_formats =3D ARRAY_SIZE(mt8195_formats), .supports_clrfmt_ext =3D true, diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index c6768210b08b..2d47b6eb4c19 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -400,6 +400,13 @@ void mtk_ovl_adaptor_disable_vblank(struct device *dev) mtk_ethdr_disable_vblank(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0= ]); } =20 +const u32 mtk_ovl_adaptor_get_blend_modes(struct device *dev) +{ + struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); + + return mtk_mdp_rdma_get_blend_modes(ovl_adaptor->ovl_adaptor_comp[OVL_ADA= PTOR_MDP_RDMA0]); +} + const u32 *mtk_ovl_adaptor_get_formats(struct device *dev) { struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/medi= atek/mtk_mdp_rdma.c index 7c1a8c796833..a011d2e664f4 100644 --- a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c @@ -3,6 +3,7 @@ * Copyright (c) 2021 MediaTek Inc. */ =20 +#include #include #include #include @@ -232,6 +233,13 @@ void mtk_mdp_rdma_config(struct device *dev, struct mt= k_mdp_rdma_cfg *cfg, MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_H); } =20 +const u32 mtk_mdp_rdma_get_blend_modes(struct device *dev) +{ + return BIT(DRM_MODE_BLEND_PREMULTI) | + BIT(DRM_MODE_BLEND_COVERAGE) | + BIT(DRM_MODE_BLEND_PIXEL_NONE); +} + const u32 *mtk_mdp_rdma_get_formats(struct device *dev) { return formats; diff --git a/drivers/gpu/drm/mediatek/mtk_plane.c b/drivers/gpu/drm/mediate= k/mtk_plane.c index 7d2cb4e0fafa..eb545b81bf2f 100644 --- a/drivers/gpu/drm/mediatek/mtk_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_plane.c @@ -320,8 +320,8 @@ static const struct drm_plane_helper_funcs mtk_plane_he= lper_funcs =3D { =20 int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane, unsigned long possible_crtcs, enum drm_plane_type type, - unsigned int supported_rotations, const u32 *formats, - size_t num_formats, unsigned int plane_idx) + unsigned int supported_rotations, const u32 blend_modes, + const u32 *formats, size_t num_formats, unsigned int plane_idx) { int err; =20 @@ -366,10 +366,7 @@ int mtk_plane_init(struct drm_device *dev, struct drm_= plane *plane, if (err) DRM_ERROR("failed to create property: alpha\n"); =20 - err =3D drm_plane_create_blend_mode_property(plane, - BIT(DRM_MODE_BLEND_PREMULTI) | - BIT(DRM_MODE_BLEND_COVERAGE) | - BIT(DRM_MODE_BLEND_PIXEL_NONE)); + err =3D drm_plane_create_blend_mode_property(plane, blend_modes); if (err) DRM_ERROR("failed to create property: blend_mode\n"); =20 diff --git a/drivers/gpu/drm/mediatek/mtk_plane.h b/drivers/gpu/drm/mediate= k/mtk_plane.h index 5b177eac67b7..3b13b89989c7 100644 --- a/drivers/gpu/drm/mediatek/mtk_plane.h +++ b/drivers/gpu/drm/mediatek/mtk_plane.h @@ -48,6 +48,6 @@ to_mtk_plane_state(struct drm_plane_state *state) =20 int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane, unsigned long possible_crtcs, enum drm_plane_type type, - unsigned int supported_rotations, const u32 *formats, - size_t num_formats, unsigned int plane_idx); + unsigned int supported_rotations, const u32 blend_modes, + const u32 *formats, size_t num_formats, unsigned int plane_idx); #endif --=20 2.43.0