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However, this fixed values only appli= es to the set of conditions of IC_CAP_LOADING =3D 400pF and IC_FREQ_OPTIMIZATION =3D 1. Outside of this conditions set, if this fixed values are still used, the calculated HCNT and LCNT will make the SCL frequency unabled to reach 3.4 MHz. If hs_hcnt and hs_lcnt are calculated based on fixed tHIGH =3D 160 and tLOW =3D 320, SCL frequency may not reach 3.4 MHz when IC_CAP_LOADING is not 400pF or IC_FREQ_OPTIMIZATION is not 1. Section 3.15.4.5 in DesignWare DW_apb_i2c Databook v2.03 says when IC_CLK_FREQ_OPTIMIZATION =3D 0, MIN_SCL_HIGHtime =3D 60 ns for 3.4 Mbps, bus loading =3D 100pF =3D 120 ns for 3,4 Mbps, bus loading =3D 400pF MIN_SCL_LOWtime =3D 160 ns for 3.4 Mbps, bus loading =3D 100pF =3D 320 ns for 3.4 Mbps, bus loading =3D 400pF and section 3.15.4.6 says when IC_CLK_FREQ_OPTIMIZATION =3D 1, MIN_SCL_HIGHtime =3D 60 ns for 3.4 Mbps, bus loading =3D 100pF =3D 160 ns for 3.4 Mbps, bus loading =3D 400pF MIN_SCL_LOWtime =3D 120 ns for 3.4 Mbps, bus loading =3D 100pF =3D 320 ns for 3.4 Mbps, bus loading =3D 400pF In order to calculate more accurate hs_hcnt and hs_lcnt, two hardware parameters IC_CAP_LOADING and IC_CLK_FREQ_OPTIMIZATION must be considered together. Signed-off-by: Michael Wu --- drivers/i2c/busses/i2c-designware-common.c | 16 ++++++++++++++ drivers/i2c/busses/i2c-designware-core.h | 8 +++++++ drivers/i2c/busses/i2c-designware-master.c | 24 +++++++++++++++++++-- drivers/i2c/busses/i2c-designware-platdrv.c | 2 ++ 4 files changed, 48 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/busses/i2c-designware-common.c b/drivers/i2c/busse= s/i2c-designware-common.c index e8a688d04aee..f0a7d0ce6fd6 100644 --- a/drivers/i2c/busses/i2c-designware-common.c +++ b/drivers/i2c/busses/i2c-designware-common.c @@ -332,6 +332,22 @@ void i2c_dw_adjust_bus_speed(struct dw_i2c_dev *dev) } EXPORT_SYMBOL_GPL(i2c_dw_adjust_bus_speed); =20 +void i2c_dw_parse_of(struct dw_i2c_dev *dev) +{ + int ret; + + ret =3D device_property_read_u32(dev->dev, "bus-loading", + &dev->bus_loading); + if (ret || dev->bus_loading < 400) + dev->bus_loading =3D 100; + else + dev->bus_loading =3D 400; + + dev->clk_freq_optimized =3D + device_property_read_bool(dev->dev, "clk-freq-optimized"); + +} + u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset) { /* diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/= i2c-designware-core.h index e9606c00b8d1..064ba3426499 100644 --- a/drivers/i2c/busses/i2c-designware-core.h +++ b/drivers/i2c/busses/i2c-designware-core.h @@ -242,6 +242,11 @@ struct reset_control; * @set_sda_hold_time: callback to retrieve IP specific SDA hold timing * @mode: operation mode - DW_IC_MASTER or DW_IC_SLAVE * @rinfo: I=C2=B2C GPIO recovery information + * @bus_loading: for high speed mode, the bus loading affects the high and= low + * pulse width of SCL + * @clk_freq_optimized: indicate whether the system clock frequency is red= uced + * by reducing the internal latency required to generate the high period + * and low period of the SCL line * * HCNT and LCNT parameters can be used if the platform knows more accurate * values than the one computed based only on the input clock frequency. @@ -300,6 +305,8 @@ struct dw_i2c_dev { int (*set_sda_hold_time)(struct dw_i2c_dev *dev); int mode; struct i2c_bus_recovery_info rinfo; + u32 bus_loading; + bool clk_freq_optimized; }; =20 #define ACCESS_INTR_MASK BIT(0) @@ -329,6 +336,7 @@ struct i2c_dw_semaphore_callbacks { }; =20 int i2c_dw_init_regmap(struct dw_i2c_dev *dev); +void i2c_dw_parse_of(struct dw_i2c_dev *dev); u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset); u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset); int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev); diff --git a/drivers/i2c/busses/i2c-designware-master.c b/drivers/i2c/busse= s/i2c-designware-master.c index c7e56002809a..7b187f68394e 100644 --- a/drivers/i2c/busses/i2c-designware-master.c +++ b/drivers/i2c/busses/i2c-designware-master.c @@ -140,16 +140,36 @@ static int i2c_dw_set_timings_master(struct dw_i2c_de= v *dev) dev->hs_hcnt =3D 0; dev->hs_lcnt =3D 0; } else if (!dev->hs_hcnt || !dev->hs_lcnt) { + u32 t_high, t_low; + + if (dev->clk_freq_optimized) { + if (dev->bus_loading =3D=3D 400) { + t_high =3D 160; + t_low =3D 320; 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charset="utf-8" Since there are no registers controlling the hardware parameters IC_CAP_LOADING and IC_CLK_FREQ_OPTIMIZATION, their values can only be noted in the device tree. "bus-loading" is used to declare the value of IC_CAP_LOADING, and "clk-freq-optimized" is used to declare IC_CLK_FREQ_OPTIMIZATION =3D 1. Signed-off-by: Michael Wu --- .../bindings/i2c/snps,designware-i2c.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml= b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml index 60035a787e5c..f954f5014a00 100644 --- a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml @@ -87,6 +87,16 @@ properties: This value is used to compute the tHIGH period. default: 300 =20 + bus-loading: + description: | + This property should be 100 or 400 for high speed mode. + This value is used to compute the tHIGH period and the tLOW period. + default: 100 + + clk_freq_optimized: + description: | + Thie property is used to declare whether the internal latency is red= uced. + dmas: items: - description: TX DMA Channel @@ -146,4 +156,13 @@ examples: interrupts =3D <8>; clocks =3D <&ahb_clk>; }; + - | + i2c@ce500000 { + compatible =3D "snps,designware-i2c"; + reg =3D <0xce500000 0x1000>; + interrupts =3D <37 1>; + clock-frequency =3D <3400000>; + bus-loading =3D <400>; + clk-freq-optimized; + }; ... --=20 2.43.0