From nobody Fri Nov 29 03:54:00 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 77D45156F42; Wed, 25 Sep 2024 07:18:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727248698; cv=none; b=tZ0KrHmvxT475bJEIsRp7AXWxdNkyRoVMqk3bBhzg0xFLwO4tNVjg/Ilw91rLKSYgU8MWKjsPAkqpq6FyqXDu/NFOq10tZ1gevSAmXumzYy4Ke422mcX73afth04IUsnNZJsZad1df4BkmES5jCAt0UIH6xIzfgAQgIOMHdH6yg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727248698; c=relaxed/simple; bh=2IDEaQdHVRA6UXhFk6RoOdjsd2rk2dkPvQAi0fjzvdA=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=KAn7k+FhBUex/9Eas6ND1f7KcW7l0UOqa5NtEToGSKt7kj6BnM+iiYplYYxv2iiXaQsqnK3hOvfYFV7RChrSU82e+4XO8aNuDe4Fj80WV4co3NxNUkxZKiXZx8ZF7lY/E4ow0Ecf24jFGT+7dzaLG5WoJpNQk9WiIEjmO+RX5xU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=rzuZoIok; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="rzuZoIok" X-UUID: 521a6c027b0e11efb66947d174671e26-20240925 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=VpzhxiIWGVCS4kVdPRp582B1kElY78w2rnCabRZFkD0=; b=rzuZoIok7Qo2pKmUA3pbSbMPKK5TPSQt6gmR2YwnY1tqP8TwvzJsmUhzu0Jj2KCre+MKcbW1tyHB4Vfy0KTjqTY+NZoUnGtfQeGI0f1hfVPQqaz/wuU1NxqJ/xBgXgOZ+rDyOZD+z1oClfWCg7woynzN2w3bMIHkGI/X+WVkPzY=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.41,REQID:ea9557cc-2a9d-4956-99f4-f8171655d5fa,IP:0,U RL:25,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:25 X-CID-META: VersionHash:6dc6a47,CLOUDID:8119bcd0-7921-4900-88a1-3aef019a55ce,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES :1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: 521a6c027b0e11efb66947d174671e26-20240925 Received: from mtkmbs09n1.mediatek.inc [(172.21.101.35)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1434475805; Wed, 25 Sep 2024 15:18:10 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 25 Sep 2024 00:18:09 -0700 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 25 Sep 2024 15:18:09 +0800 From: Macpaul Lin To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , , , , , Alexandre Mergnat CC: Bear Wang , Pablo Sun , Macpaul Lin , Macpaul Lin , Sen Chu , Chris-qj chen , MediaTek Chromebook Upstream , Chen-Yu Tsai , Tommy Chen Subject: [PATCH v2] arm64: dts: mediatek: mt8195: Add power domain for dp_intf0 Date: Wed, 25 Sep 2024 15:18:07 +0800 Message-ID: <20240925071807.19603-1-macpaul.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" During inspecting dtbs_check errors, we found the power domain setting of DPI node "dp_intf0" is missing. Add power domain setting to "MT8195_POWER_DOMAIN_VDOSYS0" for "dp_intf0" Signed-off-by: Tommy Chen Signed-off-by: Macpaul Lin --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 1 + 1 file changed, 1 insertion(+) Changes for v1: - This patch is related to adding mt8195-dp-intf to DT schema fix for - http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml=20 - patch: https://lore.kernel.org/all/20240924103156.13119-6-macpaul.lin@m= ediatek.com/ Changes for v2: - Fix typo for Tommy's email address. Others remains no change. diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index ade685ed2190..6218bd7abb05 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -3252,6 +3252,7 @@ dp_intf0: dp-intf@1c015000 { compatible =3D "mediatek,mt8195-dp-intf"; reg =3D <0 0x1c015000 0 0x1000>; interrupts =3D ; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VDOSYS0>; clocks =3D <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, <&vdosys0 CLK_VDO0_DP_INTF0>, <&apmixedsys CLK_APMIXED_TVDPLL1>; --=20 2.45.2