From nobody Fri Nov 29 03:57:31 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0869F148FF5; Wed, 25 Sep 2024 02:47:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727232434; cv=none; b=O2hVggE7U/QyCEvJXfwRxNpz2RpoGlmxu1raBUfGdcEXfvrkKOYsIWprapt1KR+srvbhEfi/SXQawPkxiJs0S7Y4kJLUHcE0NWGotC1ai156owYTYz30bA1obuGYB9IdIAzY3hcmIEWEDH+IS2A/BC9ib6W2q214KOuw3tnT4s8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727232434; c=relaxed/simple; bh=KaE7JObUOq0Hcir5tFk/BG6islLlrFQy8Kf+EuSeDvI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Vw5obGzsu832Jhm2fzafqiGxqXzp7b+iwVlSoH49yZVYXGzXqfx0QEQfCSQM6tFOo6/hhMz+pac31OOCYCCtlCfIRMiipnvaTjCUXK0HkGqPPNrvxrFjWZTCOoxHJsphN/32ogZuSF7J7E/3ILkwRk2X5eXc7bZgq5EocpEG6vg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Qv8/0POU; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Qv8/0POU" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1727232432; x=1758768432; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KaE7JObUOq0Hcir5tFk/BG6islLlrFQy8Kf+EuSeDvI=; b=Qv8/0POU7ce61vC3gni/NTpbxhuLmtJrk1kO7VzuNB8tc1npxd27GVo6 F8HF7YVVtsbFeFl63Pnz4gE3Ntvh56ORW9VXxyY/lYbYjp+6OLfZh44+Q hKor7TOPKWFw9wVECs1vg+q511HFIyIrENSdpehj032Q5O2w0/752D6fT UyQFw/h//YatvGQqUCxhyRezyYw+jNOdNTuvtWIntMQ3JRI/YT4wMZn+M /VWZF2VZqC60+vypq59r6t0VQadWpuRQyLoV8ZN5QsnmJzldpJ6qlMVO2 L7JZBkdPXb2qnw3A4mansB4n1YHuWhbIBG4pr34/NC/UgBiX8l6QK031O w==; X-CSE-ConnectionGUID: 7b5VOZPkRP6FxzMdSW2AEA== X-CSE-MsgGUID: u3JKQ+VpSkWmQdoVFfPf6Q== X-IronPort-AV: E=McAfee;i="6700,10204,11205"; a="26132026" X-IronPort-AV: E=Sophos;i="6.10,256,1719903600"; d="scan'208";a="26132026" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Sep 2024 19:47:12 -0700 X-CSE-ConnectionGUID: SSEpI4rNQSmayvsP5CKZtg== X-CSE-MsgGUID: 1Jpq3+vxR+q0bv6wWzRlqw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,256,1719903600"; d="scan'208";a="102388969" Received: from yhuang6-mobl2.sh.intel.com ([10.238.3.32]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Sep 2024 19:47:09 -0700 From: Huang Ying To: Dan Williams , Dave Jiang Cc: linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, Huang Ying , Jonathan Cameron , Davidlohr Bueso , Jonathan Cameron , Alison Schofield , Vishal Verma , Ira Weiny , Alejandro Lucero Subject: [RFC 1/5] cxl: Rename ACPI_CEDT_CFMWS_RESTRICT_TYPE2/TYPE3 Date: Wed, 25 Sep 2024 10:46:43 +0800 Message-Id: <20240925024647.46735-2-ying.huang@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240925024647.46735-1-ying.huang@intel.com> References: <20240925024647.46735-1-ying.huang@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" According to the description of the "Window Restrictions" field of "CFMWS Structure" in the CXL spec v3.1 section 9.18.1.3: CXL Fixed Memory Window Structure (CFMWS), the bit 0 of "Window Restrictions" is formerly known as "CXL Type 2 Memory" and renamed to "Device Coherent", while the bit 1 is formerly known as "CXL Type 3 Memory" and renamed to "Host-only Coherent". Because type 3 memory can only be host-only coherent before, while it can be host-only coherent or device coherent with "Back-Invalidate" now. To avoid confusing about type 3 memory and host-only coherent in Linux kernel, we rename corresponding bit definition from ACPI_CEDT_CFMWS_RESTRICT_TYPE2/TYPE3 to ACPI_CEDT_CFMWS_RESTRICT_DEVCOH/HOSTONLYCOH. This makes the kernel code consistent with the spec too. Also rename the corresponding cxl_decoder flags CXL_DECODER_F_TYPE2/TYPE3 to CXL_DECODER_F_DEVCOH/HOSTONLYCOH. No functionality change is expected, because we just rename the flags constant definition. Signed-off-by: "Huang, Ying" Suggested-by: Jonathan Cameron Cc: Dan Williams Cc: Davidlohr Bueso Cc: Jonathan Cameron Cc: Dave Jiang Cc: Alison Schofield Cc: Vishal Verma Cc: Ira Weiny Cc: Alejandro Lucero Reviewed-by: Davidlohr Bueso Reviewed-by: Gregory Price --- drivers/cxl/acpi.c | 8 ++++---- drivers/cxl/core/port.c | 8 ++++---- drivers/cxl/cxl.h | 14 +++++++------- include/acpi/actbl1.h | 10 +++++----- tools/testing/cxl/test/cxl.c | 18 +++++++++--------- 5 files changed, 29 insertions(+), 29 deletions(-) diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c index 82b78e331d8e..3115f246273b 100644 --- a/drivers/cxl/acpi.c +++ b/drivers/cxl/acpi.c @@ -115,10 +115,10 @@ static unsigned long cfmws_to_decoder_flags(int restr= ictions) { unsigned long flags =3D CXL_DECODER_F_ENABLE; =20 - if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE2) - flags |=3D CXL_DECODER_F_TYPE2; - if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE3) - flags |=3D CXL_DECODER_F_TYPE3; + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_DEVCOH) + flags |=3D CXL_DECODER_F_DEVCOH; + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_HOSTONLYCOH) + flags |=3D CXL_DECODER_F_HOSTONLYCOH; if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_VOLATILE) flags |=3D CXL_DECODER_F_RAM; if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_PMEM) diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 1d5007e3795a..67a8dc4d7868 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -125,8 +125,8 @@ static DEVICE_ATTR_RO(name) =20 CXL_DECODER_FLAG_ATTR(cap_pmem, CXL_DECODER_F_PMEM); CXL_DECODER_FLAG_ATTR(cap_ram, CXL_DECODER_F_RAM); -CXL_DECODER_FLAG_ATTR(cap_type2, CXL_DECODER_F_TYPE2); -CXL_DECODER_FLAG_ATTR(cap_type3, CXL_DECODER_F_TYPE3); +CXL_DECODER_FLAG_ATTR(cap_type2, CXL_DECODER_F_DEVCOH); +CXL_DECODER_FLAG_ATTR(cap_type3, CXL_DECODER_F_HOSTONLYCOH); CXL_DECODER_FLAG_ATTR(locked, CXL_DECODER_F_LOCK); =20 static ssize_t target_type_show(struct device *dev, @@ -326,14 +326,14 @@ static struct attribute *cxl_decoder_root_attrs[] =3D= { =20 static bool can_create_pmem(struct cxl_root_decoder *cxlrd) { - unsigned long flags =3D CXL_DECODER_F_TYPE3 | CXL_DECODER_F_PMEM; + unsigned long flags =3D CXL_DECODER_F_HOSTONLYCOH | CXL_DECODER_F_PMEM; =20 return (cxlrd->cxlsd.cxld.flags & flags) =3D=3D flags; } =20 static bool can_create_ram(struct cxl_root_decoder *cxlrd) { - unsigned long flags =3D CXL_DECODER_F_TYPE3 | CXL_DECODER_F_RAM; + unsigned long flags =3D CXL_DECODER_F_HOSTONLYCOH | CXL_DECODER_F_RAM; =20 return (cxlrd->cxlsd.cxld.flags & flags) =3D=3D flags; } diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 9afb407d438f..28c8783d3c14 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -315,13 +315,13 @@ resource_size_t cxl_rcd_component_reg_phys(struct dev= ice *dev, * Additionally indicate whether decoder settings were autodetected, * user customized. */ -#define CXL_DECODER_F_RAM BIT(0) -#define CXL_DECODER_F_PMEM BIT(1) -#define CXL_DECODER_F_TYPE2 BIT(2) -#define CXL_DECODER_F_TYPE3 BIT(3) -#define CXL_DECODER_F_LOCK BIT(4) -#define CXL_DECODER_F_ENABLE BIT(5) -#define CXL_DECODER_F_MASK GENMASK(5, 0) +#define CXL_DECODER_F_RAM BIT(0) +#define CXL_DECODER_F_PMEM BIT(1) +#define CXL_DECODER_F_DEVCOH BIT(2) +#define CXL_DECODER_F_HOSTONLYCOH BIT(3) +#define CXL_DECODER_F_LOCK BIT(4) +#define CXL_DECODER_F_ENABLE BIT(5) +#define CXL_DECODER_F_MASK GENMASK(5, 0) =20 enum cxl_decoder_type { CXL_DECODER_DEVMEM =3D 2, diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h index 841ef9f22795..2b38455e0f13 100644 --- a/include/acpi/actbl1.h +++ b/include/acpi/actbl1.h @@ -551,11 +551,11 @@ struct acpi_cedt_cfmws_target_element { =20 /* Values for Restrictions field above */ =20 -#define ACPI_CEDT_CFMWS_RESTRICT_TYPE2 (1) -#define ACPI_CEDT_CFMWS_RESTRICT_TYPE3 (1<<1) -#define ACPI_CEDT_CFMWS_RESTRICT_VOLATILE (1<<2) -#define ACPI_CEDT_CFMWS_RESTRICT_PMEM (1<<3) -#define ACPI_CEDT_CFMWS_RESTRICT_FIXED (1<<4) +#define ACPI_CEDT_CFMWS_RESTRICT_DEVCOH (1) +#define ACPI_CEDT_CFMWS_RESTRICT_HOSTONLYCOH (1<<1) +#define ACPI_CEDT_CFMWS_RESTRICT_VOLATILE (1<<2) +#define ACPI_CEDT_CFMWS_RESTRICT_PMEM (1<<3) +#define ACPI_CEDT_CFMWS_RESTRICT_FIXED (1<<4) =20 /* 2: CXL XOR Interleave Math Structure */ =20 diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c index 90d5afd52dd0..3982d292d286 100644 --- a/tools/testing/cxl/test/cxl.c +++ b/tools/testing/cxl/test/cxl.c @@ -209,7 +209,7 @@ static struct { }, .interleave_ways =3D 0, .granularity =3D 4, - .restrictions =3D ACPI_CEDT_CFMWS_RESTRICT_TYPE3 | + .restrictions =3D ACPI_CEDT_CFMWS_RESTRICT_HOSTONLYCOH | ACPI_CEDT_CFMWS_RESTRICT_VOLATILE, .qtg_id =3D FAKE_QTG_ID, .window_size =3D SZ_256M * 4UL, @@ -224,7 +224,7 @@ static struct { }, .interleave_ways =3D 1, .granularity =3D 4, - .restrictions =3D ACPI_CEDT_CFMWS_RESTRICT_TYPE3 | + .restrictions =3D ACPI_CEDT_CFMWS_RESTRICT_HOSTONLYCOH | ACPI_CEDT_CFMWS_RESTRICT_VOLATILE, .qtg_id =3D FAKE_QTG_ID, .window_size =3D SZ_256M * 8UL, @@ -239,7 +239,7 @@ static struct { }, .interleave_ways =3D 0, .granularity =3D 4, - .restrictions =3D ACPI_CEDT_CFMWS_RESTRICT_TYPE3 | + .restrictions =3D ACPI_CEDT_CFMWS_RESTRICT_HOSTONLYCOH | ACPI_CEDT_CFMWS_RESTRICT_PMEM, .qtg_id =3D FAKE_QTG_ID, .window_size =3D SZ_256M * 4UL, @@ -254,7 +254,7 @@ static struct { }, .interleave_ways =3D 1, .granularity =3D 4, - .restrictions =3D ACPI_CEDT_CFMWS_RESTRICT_TYPE3 | + .restrictions =3D ACPI_CEDT_CFMWS_RESTRICT_HOSTONLYCOH | ACPI_CEDT_CFMWS_RESTRICT_PMEM, .qtg_id =3D FAKE_QTG_ID, .window_size =3D SZ_256M * 8UL, @@ -269,7 +269,7 @@ static struct { }, .interleave_ways =3D 0, .granularity =3D 4, - .restrictions =3D ACPI_CEDT_CFMWS_RESTRICT_TYPE3 | + .restrictions =3D ACPI_CEDT_CFMWS_RESTRICT_HOSTONLYCOH | ACPI_CEDT_CFMWS_RESTRICT_PMEM, .qtg_id =3D FAKE_QTG_ID, .window_size =3D SZ_256M * 4UL, @@ -284,7 +284,7 @@ static struct { }, .interleave_ways =3D 0, .granularity =3D 4, - .restrictions =3D ACPI_CEDT_CFMWS_RESTRICT_TYPE3 | + .restrictions =3D ACPI_CEDT_CFMWS_RESTRICT_HOSTONLYCOH | ACPI_CEDT_CFMWS_RESTRICT_VOLATILE, .qtg_id =3D FAKE_QTG_ID, .window_size =3D SZ_256M, @@ -301,7 +301,7 @@ static struct { .interleave_arithmetic =3D ACPI_CEDT_CFMWS_ARITHMETIC_XOR, .interleave_ways =3D 0, .granularity =3D 4, - .restrictions =3D ACPI_CEDT_CFMWS_RESTRICT_TYPE3 | + .restrictions =3D ACPI_CEDT_CFMWS_RESTRICT_HOSTONLYCOH | ACPI_CEDT_CFMWS_RESTRICT_PMEM, .qtg_id =3D FAKE_QTG_ID, .window_size =3D SZ_256M * 8UL, @@ -317,7 +317,7 @@ static struct { .interleave_arithmetic =3D ACPI_CEDT_CFMWS_ARITHMETIC_XOR, .interleave_ways =3D 1, .granularity =3D 0, - .restrictions =3D ACPI_CEDT_CFMWS_RESTRICT_TYPE3 | + .restrictions =3D ACPI_CEDT_CFMWS_RESTRICT_HOSTONLYCOH | ACPI_CEDT_CFMWS_RESTRICT_PMEM, .qtg_id =3D FAKE_QTG_ID, .window_size =3D SZ_256M * 8UL, @@ -333,7 +333,7 @@ static struct { .interleave_arithmetic =3D ACPI_CEDT_CFMWS_ARITHMETIC_XOR, .interleave_ways =3D 2, .granularity =3D 0, - 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So the target device type of a cxl decoder is named as CXL_DECODER_HOSTONLYMEM for type3 devices and CXL_DECODER_DEVMEM for type2 devices. However, this isn't true anymore. CXL type3 devices can use dev coherence + back invalidation (HDM-DB) too. To avoid confusing between the device type and coherence, in this patch, CXL_DECODER_HOSTONLYMEM/DEVMEM is renamed to CXL_DECODER_EXPANDER/ACCEL. No functionality change is expected in this patch. Signed-off-by: "Huang, Ying" Cc: Jonathan Cameron Cc: Dan Williams Cc: Davidlohr Bueso Cc: Jonathan Cameron Cc: Dave Jiang Cc: Alison Schofield Cc: Vishal Verma Cc: Ira Weiny Cc: Alejandro Lucero Reviewed-by: Davidlohr Bueso Reviewed-by: Gregory Price --- drivers/cxl/acpi.c | 2 +- drivers/cxl/core/hdm.c | 16 ++++++++-------- drivers/cxl/core/port.c | 6 +++--- drivers/cxl/core/region.c | 2 +- drivers/cxl/cxl.h | 4 ++-- tools/testing/cxl/test/cxl.c | 6 +++--- 6 files changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c index 3115f246273b..21486e471305 100644 --- a/drivers/cxl/acpi.c +++ b/drivers/cxl/acpi.c @@ -382,7 +382,7 @@ static int __cxl_parse_cfmws(struct acpi_cedt_cfmws *cf= mws, =20 cxld =3D &cxlrd->cxlsd.cxld; cxld->flags =3D cfmws_to_decoder_flags(cfmws->restrictions); - cxld->target_type =3D CXL_DECODER_HOSTONLYMEM; + cxld->target_type =3D CXL_DECODER_EXPANDER; cxld->hpa_range =3D (struct range) { .start =3D cfmws->base_hpa, .end =3D cfmws->base_hpa + cfmws->window_size - 1, diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c index 3df10517a327..57b54ecdb000 100644 --- a/drivers/cxl/core/hdm.c +++ b/drivers/cxl/core/hdm.c @@ -572,7 +572,7 @@ static void cxld_set_interleave(struct cxl_decoder *cxl= d, u32 *ctrl) static void cxld_set_type(struct cxl_decoder *cxld, u32 *ctrl) { u32p_replace_bits(ctrl, - !!(cxld->target_type =3D=3D CXL_DECODER_HOSTONLYMEM), + !!(cxld->target_type =3D=3D CXL_DECODER_EXPANDER), CXL_HDM_DECODER0_CTRL_HOSTONLY); } =20 @@ -771,7 +771,7 @@ static int cxl_setup_hdm_decoder_from_dvsec( if (!len) return -ENOENT; =20 - cxld->target_type =3D CXL_DECODER_HOSTONLYMEM; + cxld->target_type =3D CXL_DECODER_EXPANDER; cxld->commit =3D NULL; cxld->reset =3D NULL; cxld->hpa_range =3D info->dvsec_range[which]; @@ -847,9 +847,9 @@ static int init_hdm_decoder(struct cxl_port *port, stru= ct cxl_decoder *cxld, if (ctrl & CXL_HDM_DECODER0_CTRL_LOCK) cxld->flags |=3D CXL_DECODER_F_LOCK; if (FIELD_GET(CXL_HDM_DECODER0_CTRL_HOSTONLY, ctrl)) - cxld->target_type =3D CXL_DECODER_HOSTONLYMEM; + cxld->target_type =3D CXL_DECODER_EXPANDER; else - cxld->target_type =3D CXL_DECODER_DEVMEM; + cxld->target_type =3D CXL_DECODER_ACCEL; =20 guard(rwsem_write)(&cxl_region_rwsem); if (cxld->id !=3D cxl_num_decoders_committed(port)) { @@ -876,16 +876,16 @@ static int init_hdm_decoder(struct cxl_port *port, st= ruct cxl_decoder *cxld, * more precision. */ if (cxlds->type =3D=3D CXL_DEVTYPE_CLASSMEM) - cxld->target_type =3D CXL_DECODER_HOSTONLYMEM; + cxld->target_type =3D CXL_DECODER_EXPANDER; else - cxld->target_type =3D CXL_DECODER_DEVMEM; + cxld->target_type =3D CXL_DECODER_ACCEL; } else { /* To be overridden by region type at commit time */ - cxld->target_type =3D CXL_DECODER_HOSTONLYMEM; + cxld->target_type =3D CXL_DECODER_EXPANDER; } =20 if (!FIELD_GET(CXL_HDM_DECODER0_CTRL_HOSTONLY, ctrl) && - cxld->target_type =3D=3D CXL_DECODER_HOSTONLYMEM) { + cxld->target_type =3D=3D CXL_DECODER_EXPANDER) { ctrl |=3D CXL_HDM_DECODER0_CTRL_HOSTONLY; writel(ctrl, hdm + CXL_HDM_DECODER0_CTRL_OFFSET(which)); } diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 67a8dc4d7868..47ad6d9329db 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -135,9 +135,9 @@ static ssize_t target_type_show(struct device *dev, struct cxl_decoder *cxld =3D to_cxl_decoder(dev); =20 switch (cxld->target_type) { - case CXL_DECODER_DEVMEM: + case CXL_DECODER_ACCEL: return sysfs_emit(buf, "accelerator\n"); - case CXL_DECODER_HOSTONLYMEM: + case CXL_DECODER_EXPANDER: return sysfs_emit(buf, "expander\n"); } return -ENXIO; @@ -1768,7 +1768,7 @@ static int cxl_decoder_init(struct cxl_port *port, st= ruct cxl_decoder *cxld) /* Pre initialize an "empty" decoder */ cxld->interleave_ways =3D 1; cxld->interleave_granularity =3D PAGE_SIZE; - cxld->target_type =3D CXL_DECODER_HOSTONLYMEM; + cxld->target_type =3D CXL_DECODER_EXPANDER; cxld->hpa_range =3D (struct range) { .start =3D 0, .end =3D -1, diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 21ad5f242875..8229e8a0072d 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -2545,7 +2545,7 @@ static struct cxl_region *__create_region(struct cxl_= root_decoder *cxlrd, return ERR_PTR(-EBUSY); } =20 - return devm_cxl_add_region(cxlrd, id, mode, CXL_DECODER_HOSTONLYMEM); + return devm_cxl_add_region(cxlrd, id, mode, CXL_DECODER_EXPANDER); } =20 static ssize_t create_pmem_region_store(struct device *dev, diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 28c8783d3c14..55b8c32f8d72 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -324,8 +324,8 @@ resource_size_t cxl_rcd_component_reg_phys(struct devic= e *dev, #define CXL_DECODER_F_MASK GENMASK(5, 0) =20 enum cxl_decoder_type { - CXL_DECODER_DEVMEM =3D 2, - CXL_DECODER_HOSTONLYMEM =3D 3, + CXL_DECODER_ACCEL =3D 2, + CXL_DECODER_EXPANDER =3D 3, }; =20 /* diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c index 3982d292d286..352a62c745c6 100644 --- a/tools/testing/cxl/test/cxl.c +++ b/tools/testing/cxl/test/cxl.c @@ -724,7 +724,7 @@ static void default_mock_decoder(struct cxl_decoder *cx= ld) =20 cxld->interleave_ways =3D 1; cxld->interleave_granularity =3D 256; - cxld->target_type =3D CXL_DECODER_HOSTONLYMEM; + cxld->target_type =3D CXL_DECODER_EXPANDER; cxld->commit =3D mock_decoder_commit; cxld->reset =3D mock_decoder_reset; } @@ -798,7 +798,7 @@ static void mock_init_hdm_decoder(struct cxl_decoder *c= xld) =20 cxld->interleave_ways =3D 2; eig_to_granularity(window->granularity, &cxld->interleave_granularity); - cxld->target_type =3D CXL_DECODER_HOSTONLYMEM; + cxld->target_type =3D CXL_DECODER_EXPANDER; cxld->flags =3D CXL_DECODER_F_ENABLE; cxled->state =3D CXL_DECODER_STATE_AUTO; port->commit_end =3D cxld->id; @@ -831,7 +831,7 @@ static void mock_init_hdm_decoder(struct cxl_decoder *c= xld) } else cxlsd->target[0] =3D dport; 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24 Sep 2024 19:47:16 -0700 From: Huang Ying To: Dan Williams , Dave Jiang Cc: linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, Huang Ying , Jonathan Cameron , Davidlohr Bueso , Jonathan Cameron , Alison Schofield , Vishal Verma , Ira Weiny , Alejandro Lucero Subject: [RFC 3/5] cxl: Separate coherence from target type Date: Wed, 25 Sep 2024 10:46:45 +0800 Message-Id: <20240925024647.46735-4-ying.huang@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240925024647.46735-1-ying.huang@intel.com> References: <20240925024647.46735-1-ying.huang@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Previously, target type (expander or accelerator) and coherence (HOSTONLY (HDM-H) or DEV (HDM-D/DB)) are synonym. So target type is used to designate coherence too. However, it's possible for expanders to use HDM-DB now. So, we need to separate coherence from target type. Accordingly, the HOSTONLY field of decoder ctrl register (CXL_HDM_DECODER0_CTRL_HOSTONLY) need to be set according to coherence. The coherence of decoders can not be determined via target type too. So, accelerator/expander device drivers need to specify coherence explicitly via newly added coherence field in struct cxl_dev_state. The coherence of each end points in a region need to be same. So, the coherence of the first end point is recorded in struct region. Which will be checked against the coherence of all other end points. Signed-off-by: "Huang, Ying" Cc: Jonathan Cameron Cc: Dan Williams Cc: Davidlohr Bueso Cc: Jonathan Cameron Cc: Dave Jiang Cc: Alison Schofield Cc: Vishal Verma Cc: Ira Weiny Cc: Alejandro Lucero Reviewed-by: Gregory Price --- drivers/cxl/core/hdm.c | 22 +++++++++++++++------- drivers/cxl/core/mbox.c | 1 + drivers/cxl/core/port.c | 1 + drivers/cxl/core/region.c | 37 ++++++++++++++++++++++++++++++++++--- drivers/cxl/cxl.h | 9 +++++++++ drivers/cxl/cxlmem.h | 11 +++++++++++ 6 files changed, 71 insertions(+), 10 deletions(-) diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c index 57b54ecdb000..478fb6691759 100644 --- a/drivers/cxl/core/hdm.c +++ b/drivers/cxl/core/hdm.c @@ -569,10 +569,10 @@ static void cxld_set_interleave(struct cxl_decoder *c= xld, u32 *ctrl) *ctrl |=3D CXL_HDM_DECODER0_CTRL_COMMIT; } =20 -static void cxld_set_type(struct cxl_decoder *cxld, u32 *ctrl) +static void cxld_set_coherence(struct cxl_decoder *cxld, u32 *ctrl) { u32p_replace_bits(ctrl, - !!(cxld->target_type =3D=3D CXL_DECODER_EXPANDER), + !!(cxld->coherence =3D=3D CXL_DECODER_HOSTONLYCOH), CXL_HDM_DECODER0_CTRL_HOSTONLY); } =20 @@ -667,7 +667,7 @@ static int cxl_decoder_commit(struct cxl_decoder *cxld) /* common decoder settings */ ctrl =3D readl(hdm + CXL_HDM_DECODER0_CTRL_OFFSET(cxld->id)); cxld_set_interleave(cxld, &ctrl); - cxld_set_type(cxld, &ctrl); + cxld_set_coherence(cxld, &ctrl); base =3D cxld->hpa_range.start; size =3D range_len(&cxld->hpa_range); =20 @@ -846,10 +846,13 @@ static int init_hdm_decoder(struct cxl_port *port, st= ruct cxl_decoder *cxld, cxld->flags |=3D CXL_DECODER_F_ENABLE; if (ctrl & CXL_HDM_DECODER0_CTRL_LOCK) cxld->flags |=3D CXL_DECODER_F_LOCK; - if (FIELD_GET(CXL_HDM_DECODER0_CTRL_HOSTONLY, ctrl)) + if (FIELD_GET(CXL_HDM_DECODER0_CTRL_HOSTONLY, ctrl)) { cxld->target_type =3D CXL_DECODER_EXPANDER; - else + cxld->coherence =3D CXL_DECODER_HOSTONLYCOH; + } else { cxld->target_type =3D CXL_DECODER_ACCEL; + cxld->coherence =3D CXL_DECODER_DEVCOH; + } =20 guard(rwsem_write)(&cxl_region_rwsem); if (cxld->id !=3D cxl_num_decoders_committed(port)) { @@ -879,13 +882,18 @@ static int init_hdm_decoder(struct cxl_port *port, st= ruct cxl_decoder *cxld, cxld->target_type =3D CXL_DECODER_EXPANDER; else cxld->target_type =3D CXL_DECODER_ACCEL; + if (cxlds->coherence =3D=3D CXL_DEVCOH_HOSTONLY) + cxld->coherence =3D CXL_DECODER_HOSTONLYCOH; + else + cxld->coherence =3D CXL_DECODER_DEVCOH; } else { - /* To be overridden by region type at commit time */ + /* To be overridden by region type/coherence at commit time */ cxld->target_type =3D CXL_DECODER_EXPANDER; + cxld->coherence =3D CXL_DECODER_HOSTONLYCOH; } =20 if (!FIELD_GET(CXL_HDM_DECODER0_CTRL_HOSTONLY, ctrl) && - cxld->target_type =3D=3D CXL_DECODER_EXPANDER) { + cxld->coherence =3D=3D CXL_DECODER_HOSTONLYCOH) { ctrl |=3D CXL_HDM_DECODER0_CTRL_HOSTONLY; writel(ctrl, hdm + CXL_HDM_DECODER0_CTRL_OFFSET(which)); } diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c index e5cdeafdf76e..3635a0a402b7 100644 --- a/drivers/cxl/core/mbox.c +++ b/drivers/cxl/core/mbox.c @@ -1424,6 +1424,7 @@ struct cxl_memdev_state *cxl_memdev_state_create(stru= ct device *dev) mds->cxlds.reg_map.host =3D dev; mds->cxlds.reg_map.resource =3D CXL_RESOURCE_NONE; mds->cxlds.type =3D CXL_DEVTYPE_CLASSMEM; + mds->cxlds.coherence =3D CXL_DEVCOH_HOSTONLY; mds->ram_perf.qos_class =3D CXL_QOS_CLASS_INVALID; mds->pmem_perf.qos_class =3D CXL_QOS_CLASS_INVALID; =20 diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 47ad6d9329db..2dee78e9b90c 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -1769,6 +1769,7 @@ static int cxl_decoder_init(struct cxl_port *port, st= ruct cxl_decoder *cxld) cxld->interleave_ways =3D 1; cxld->interleave_granularity =3D PAGE_SIZE; cxld->target_type =3D CXL_DECODER_EXPANDER; + cxld->coherence =3D CXL_DECODER_HOSTONLYCOH; cxld->hpa_range =3D (struct range) { .start =3D 0, .end =3D -1, diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 8229e8a0072d..cec7d08b6f44 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -1005,9 +1005,10 @@ static int cxl_rr_alloc_decoder(struct cxl_port *por= t, struct cxl_region *cxlr, } =20 /* - * Endpoints should already match the region type, but backstop that - * assumption with an assertion. Switch-decoders change mapping-type - * based on what is mapped when they are assigned to a region. + * Endpoints should already match the region type/coherence, but + * backstop that assumption with an assertion. Switch-decoders change + * mapping-type/coherence based on what is mapped when they are assigned + * to a region. */ dev_WARN_ONCE(&cxlr->dev, port =3D=3D cxled_to_port(cxled) && @@ -1016,6 +1017,13 @@ static int cxl_rr_alloc_decoder(struct cxl_port *por= t, struct cxl_region *cxlr, dev_name(&cxled_to_memdev(cxled)->dev), dev_name(&cxld->dev), cxld->target_type, cxlr->type); cxld->target_type =3D cxlr->type; + dev_WARN_ONCE(&cxlr->dev, + port =3D=3D cxled_to_port(cxled) && + cxld->coherence !=3D cxlr->coherence, + "%s:%s mismatch decoder coherence %d -> %d\n", + dev_name(&cxled_to_memdev(cxled)->dev), + dev_name(&cxld->dev), cxld->coherence, cxlr->coherence); + cxld->coherence =3D cxlr->coherence; cxl_rr->decoder =3D cxld; return 0; } @@ -1925,6 +1933,29 @@ static int cxl_region_attach(struct cxl_region *cxlr, return -ENXIO; } =20 + /* Set the coherence of region to that of the first endpoint */ + if (cxlr->coherence =3D=3D CXL_DECODER_INVALIDCOH) { + unsigned long flags =3D cxlrd->cxlsd.cxld.flags; + enum cxl_decoder_coherence coherence =3D cxled->cxld.coherence; + + cxlr->coherence =3D coherence; + if ((coherence =3D=3D CXL_DECODER_HOSTONLYCOH && + !(flags & CXL_DECODER_F_HOSTONLYCOH)) || + (coherence =3D=3D CXL_DECODER_DEVCOH && + !(flags & CXL_DECODER_F_DEVCOH))) { + dev_dbg(&cxlr->dev, +"%s:%s endpoint coherence: %d isn't supported by root decoder: %#lx\n", + dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev), + coherence, flags); + return -ENXIO; + } + } else if (cxled->cxld.coherence !=3D cxlr->coherence) { + dev_dbg(&cxlr->dev, "%s:%s coherence mismatch: %d vs %d\n", + dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev), + cxled->cxld.coherence, cxlr->coherence); + return -ENXIO; + } + if (!cxled->dpa_res) { dev_dbg(&cxlr->dev, "%s:%s: missing DPA allocation.\n", dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev)); diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 55b8c32f8d72..99398c868d82 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -328,6 +328,12 @@ enum cxl_decoder_type { CXL_DECODER_EXPANDER =3D 3, }; =20 +enum cxl_decoder_coherence { + CXL_DECODER_INVALIDCOH, + CXL_DECODER_HOSTONLYCOH, + CXL_DECODER_DEVCOH, +}; + /* * Current specification goes up to 8, double that seems a reasonable * software max for the foreseeable future @@ -356,6 +362,7 @@ struct cxl_decoder { int interleave_ways; int interleave_granularity; enum cxl_decoder_type target_type; + enum cxl_decoder_coherence coherence; struct cxl_region *region; unsigned long flags; int (*commit)(struct cxl_decoder *cxld); @@ -517,6 +524,7 @@ struct cxl_region_params { * @id: This region's id. Id is globally unique across all regions * @mode: Endpoint decoder allocation / access mode * @type: Endpoint decoder target type + * @coherence: Endpoint decoder coherence * @cxl_nvb: nvdimm bridge for coordinating @cxlr_pmem setup / shutdown * @cxlr_pmem: (for pmem regions) cached copy of the nvdimm bridge * @flags: Region state flags @@ -530,6 +538,7 @@ struct cxl_region { int id; enum cxl_decoder_mode mode; enum cxl_decoder_type type; + enum cxl_decoder_coherence coherence; struct cxl_nvdimm_bridge *cxl_nvb; struct cxl_pmem_region *cxlr_pmem; unsigned long flags; diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h index afb53d058d62..cc4880286134 100644 --- a/drivers/cxl/cxlmem.h +++ b/drivers/cxl/cxlmem.h @@ -393,6 +393,16 @@ enum cxl_devtype { CXL_DEVTYPE_CLASSMEM, }; =20 +/* + * enum cxl_devcoherence - the coherence of the cxl device + * @CXL_DEVCOH_DEV - HDM-D or HDM-DB + * @CXL_DEVCOH_HOSTONLY - HDM-H + */ +enum cxl_devcoherence { + CXL_DEVCOH_DEV, + CXL_DEVCOH_HOSTONLY, +}; + /** * struct cxl_dpa_perf - DPA performance property entry * @dpa_range: range for DPA address @@ -438,6 +448,7 @@ struct cxl_dev_state { struct resource ram_res; u64 serial; enum cxl_devtype type; + enum cxl_devcoherence coherence; }; =20 /** --=20 2.39.2 From nobody Fri Nov 29 03:57:31 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3879914B955; Wed, 25 Sep 2024 02:47:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727232444; cv=none; b=sXL46e+DFNF4NkMRl3t2Zf9T39pU8t52jogGvaR1TMcWuaKBLQM8pI02kbZ9Lbc3+KVxcZfQctBa8E5862TZp2sfIpEoPVr3qW4/OHmsP5MyBGW28Yj9Euin/0/6c8YRuwUHvlMIns2Rc1J9dxV7EN21bNfBYuxDa1dAqTRVOyk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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d="scan'208";a="102389036" Received: from yhuang6-mobl2.sh.intel.com ([10.238.3.32]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Sep 2024 19:47:19 -0700 From: Huang Ying To: Dan Williams , Dave Jiang Cc: linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, Huang Ying , Jonathan Cameron , Davidlohr Bueso , Jonathan Cameron , Alison Schofield , Vishal Verma , Ira Weiny , Alejandro Lucero Subject: [RFC 4/5] cxl: Set type of region to that of the first endpoint Date: Wed, 25 Sep 2024 10:46:46 +0800 Message-Id: <20240925024647.46735-5-ying.huang@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240925024647.46735-1-ying.huang@intel.com> References: <20240925024647.46735-1-ying.huang@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The type of region is hard-coded as type 3 expander now, because this is the only supported device type. As a preparation to support type 2 accelerators, we set the type of region to that of the first endpoint. Then, we will check whether the type of region is same as the type of other endpoints of the region. Because what we really need is to make sure the type of all endpoints of a region is same. The target type of endpoint devices comes from expander/accelerator device drivers via struct cxl_dev_state. Signed-off-by: "Huang, Ying" Cc: Jonathan Cameron Cc: Dan Williams Cc: Davidlohr Bueso Cc: Jonathan Cameron Cc: Dave Jiang Cc: Alison Schofield Cc: Vishal Verma Cc: Ira Weiny Cc: Alejandro Lucero Reviewed-by: Gregory Price --- drivers/cxl/acpi.c | 1 - drivers/cxl/core/hdm.c | 28 +++++++++++++--------------- drivers/cxl/core/port.c | 2 ++ drivers/cxl/core/region.c | 13 +++++++------ drivers/cxl/cxl.h | 1 + 5 files changed, 23 insertions(+), 22 deletions(-) diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c index 21486e471305..29c2a44b122c 100644 --- a/drivers/cxl/acpi.c +++ b/drivers/cxl/acpi.c @@ -382,7 +382,6 @@ static int __cxl_parse_cfmws(struct acpi_cedt_cfmws *cf= mws, =20 cxld =3D &cxlrd->cxlsd.cxld; cxld->flags =3D cfmws_to_decoder_flags(cfmws->restrictions); - cxld->target_type =3D CXL_DECODER_EXPANDER; cxld->hpa_range =3D (struct range) { .start =3D cfmws->base_hpa, .end =3D cfmws->base_hpa + cfmws->window_size - 1, diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c index 478fb6691759..c9accf8be71f 100644 --- a/drivers/cxl/core/hdm.c +++ b/drivers/cxl/core/hdm.c @@ -841,18 +841,25 @@ static int init_hdm_decoder(struct cxl_port *port, st= ruct cxl_decoder *cxld, .end =3D base + size - 1, }; =20 + if (cxled) { + struct cxl_memdev *cxlmd =3D cxled_to_memdev(cxled); + struct cxl_dev_state *cxlds =3D cxlmd->cxlds; + + if (cxlds->type =3D=3D CXL_DEVTYPE_CLASSMEM) + cxld->target_type =3D CXL_DECODER_EXPANDER; + else + cxld->target_type =3D CXL_DECODER_ACCEL; + } + /* decoders are enabled if committed */ if (committed) { cxld->flags |=3D CXL_DECODER_F_ENABLE; if (ctrl & CXL_HDM_DECODER0_CTRL_LOCK) cxld->flags |=3D CXL_DECODER_F_LOCK; - if (FIELD_GET(CXL_HDM_DECODER0_CTRL_HOSTONLY, ctrl)) { - cxld->target_type =3D CXL_DECODER_EXPANDER; + if (FIELD_GET(CXL_HDM_DECODER0_CTRL_HOSTONLY, ctrl)) cxld->coherence =3D CXL_DECODER_HOSTONLYCOH; - } else { - cxld->target_type =3D CXL_DECODER_ACCEL; + else cxld->coherence =3D CXL_DECODER_DEVCOH; - } =20 guard(rwsem_write)(&cxl_region_rwsem); if (cxld->id !=3D cxl_num_decoders_committed(port)) { @@ -874,21 +881,12 @@ static int init_hdm_decoder(struct cxl_port *port, st= ruct cxl_decoder *cxld, struct cxl_memdev *cxlmd =3D cxled_to_memdev(cxled); struct cxl_dev_state *cxlds =3D cxlmd->cxlds; =20 - /* - * Default by devtype until a device arrives that needs - * more precision. - */ - if (cxlds->type =3D=3D CXL_DEVTYPE_CLASSMEM) - cxld->target_type =3D CXL_DECODER_EXPANDER; - else - cxld->target_type =3D CXL_DECODER_ACCEL; if (cxlds->coherence =3D=3D CXL_DEVCOH_HOSTONLY) cxld->coherence =3D CXL_DECODER_HOSTONLYCOH; else cxld->coherence =3D CXL_DECODER_DEVCOH; } else { - /* To be overridden by region type/coherence at commit time */ - cxld->target_type =3D CXL_DECODER_EXPANDER; + /* To be overridden by region coherence at commit time */ cxld->coherence =3D CXL_DECODER_HOSTONLYCOH; } =20 diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 2dee78e9b90c..5633b7316cb3 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -139,6 +139,8 @@ static ssize_t target_type_show(struct device *dev, return sysfs_emit(buf, "accelerator\n"); case CXL_DECODER_EXPANDER: return sysfs_emit(buf, "expander\n"); + default: + break; } return -ENXIO; } diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index cec7d08b6f44..9c68ec445128 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -1926,7 +1926,10 @@ static int cxl_region_attach(struct cxl_region *cxlr, return -ENXIO; } =20 - if (cxled->cxld.target_type !=3D cxlr->type) { + /* Set the type of region to that of the first endpoint */ + if (cxlr->type =3D=3D CXL_DECODER_INVALID) { + cxlr->type =3D cxled->cxld.target_type; + } else if (cxled->cxld.target_type !=3D cxlr->type) { dev_dbg(&cxlr->dev, "%s:%s type mismatch: %d vs %d\n", dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev), cxled->cxld.target_type, cxlr->type); @@ -2482,7 +2485,6 @@ static int cxl_region_calculate_adistance(struct noti= fier_block *nb, * @cxlrd: root decoder * @id: memregion id to create, or memregion_free() on failure * @mode: mode for the endpoint decoders of this region - * @type: select whether this is an expander or accelerator (type-2 or typ= e-3) * * This is the second step of region initialization. Regions exist within = an * address space which is mapped by a @cxlrd. @@ -2492,8 +2494,7 @@ static int cxl_region_calculate_adistance(struct noti= fier_block *nb, */ static struct cxl_region *devm_cxl_add_region(struct cxl_root_decoder *cxl= rd, int id, - enum cxl_decoder_mode mode, - enum cxl_decoder_type type) + enum cxl_decoder_mode mode) { struct cxl_port *port =3D to_cxl_port(cxlrd->cxlsd.cxld.dev.parent); struct cxl_region *cxlr; @@ -2504,7 +2505,7 @@ static struct cxl_region *devm_cxl_add_region(struct = cxl_root_decoder *cxlrd, if (IS_ERR(cxlr)) return cxlr; cxlr->mode =3D mode; - cxlr->type =3D type; + cxlr->type =3D CXL_DECODER_INVALID; =20 dev =3D &cxlr->dev; rc =3D dev_set_name(dev, "region%d", id); @@ -2576,7 +2577,7 @@ static struct cxl_region *__create_region(struct cxl_= root_decoder *cxlrd, return ERR_PTR(-EBUSY); } =20 - return devm_cxl_add_region(cxlrd, id, mode, CXL_DECODER_EXPANDER); + return devm_cxl_add_region(cxlrd, id, mode); } =20 static ssize_t create_pmem_region_store(struct device *dev, diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 99398c868d82..2a2d2c483654 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -324,6 +324,7 @@ resource_size_t cxl_rcd_component_reg_phys(struct devic= e *dev, #define CXL_DECODER_F_MASK GENMASK(5, 0) =20 enum cxl_decoder_type { + CXL_DECODER_INVALID, CXL_DECODER_ACCEL =3D 2, CXL_DECODER_EXPANDER =3D 3, }; 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X-CSE-ConnectionGUID: hDIZOXMpTlGBwS7Jo/BI6w== X-CSE-MsgGUID: vIOnRRAyQ361nmUje2JJeg== X-IronPort-AV: E=McAfee;i="6700,10204,11205"; a="26132074" X-IronPort-AV: E=Sophos;i="6.10,256,1719903600"; d="scan'208";a="26132074" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Sep 2024 19:47:25 -0700 X-CSE-ConnectionGUID: moQoaoE4S9m+ypWf8ECacg== X-CSE-MsgGUID: 6WX5nXaVQaOAq5hfkePxAg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,256,1719903600"; d="scan'208";a="102389059" Received: from yhuang6-mobl2.sh.intel.com ([10.238.3.32]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Sep 2024 19:47:22 -0700 From: Huang Ying To: Dan Williams , Dave Jiang Cc: linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, Huang Ying , Davidlohr Bueso , Jonathan Cameron , Alison Schofield , Vishal Verma , Ira Weiny , Alejandro Lucero Subject: [RFC 5/5] cxl: Avoid to create dax regions for type2 accelerators Date: Wed, 25 Sep 2024 10:46:47 +0800 Message-Id: <20240925024647.46735-6-ying.huang@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240925024647.46735-1-ying.huang@intel.com> References: <20240925024647.46735-1-ying.huang@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The memory range of a type2 accelerator should be managed by the type2 accelerator specific driver instead of the common dax region drivers, as discussed in [1]. [1] https://lore.kernel.org/linux-cxl/66469ff1b8fbc_2c2629427@dwillia2-xfh.= jf.intel.com.notmuch/ So, in this patch, we skip dax regions creation for type2 accelerator device memory regions. Based on: https://lore.kernel.org/linux-cxl/168592159835.1948938.1647215579= 839222774.stgit@dwillia2-xfh.jf.intel.com/ Signed-off-by: "Huang, Ying" Co-developed-by: Dan Williams Signed-off-by: Dan Williams Cc: Davidlohr Bueso Cc: Jonathan Cameron Cc: Dave Jiang Cc: Alison Schofield Cc: Vishal Verma Cc: Ira Weiny Cc: Alejandro Lucero Reviewed-by: Gregory Price --- drivers/cxl/core/region.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 9c68ec445128..b276752c38da 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -3466,6 +3466,14 @@ static int cxl_region_probe(struct device *dev) p->res->start, p->res->end, cxlr, is_system_ram) > 0) return 0; + /* + * Accelerator regions have specific usage, skip + * device-dax registration. + */ + if (cxlr->type =3D=3D CXL_DECODER_ACCEL) + return 0; + + /* Expander routes to device-dax */ return devm_cxl_add_dax_region(cxlr); default: dev_dbg(&cxlr->dev, "unsupported region mode: %d\n", --=20 2.39.2