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Wed, 25 Sep 2024 10:44:06 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48PAi5l7023834 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 25 Sep 2024 10:44:05 GMT Received: from jingyw-gv.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 25 Sep 2024 03:43:59 -0700 From: Jingyi Wang Date: Wed, 25 Sep 2024 18:43:34 +0800 Subject: [PATCH v2 3/4] arm64: dts: qcom: add initial support for QCS8300 DTSI Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240925-qcs8300_initial_dtsi-v2-3-494c40fa2a42@quicinc.com> References: <20240925-qcs8300_initial_dtsi-v2-0-494c40fa2a42@quicinc.com> In-Reply-To: <20240925-qcs8300_initial_dtsi-v2-0-494c40fa2a42@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon CC: , , , , , , , Jingyi Wang , "Zhenhua Huang" , Xin Liu , "Kyle Deng" , Tingguo Cheng , Raviteja Laggyshetty X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727261026; l=39416; i=quic_jingyw@quicinc.com; s=20240910; h=from:subject:message-id; bh=9ZrF3c7i2vLTIGpGIIHFCw0OQPrQpNyzD7B6ymLcV+o=; b=oDcYuMRfKrCV4/Vlm74VBUphqyCnx1kz0fZtzzMgw5vf6OryZFH5ZDHjan06053GkaRQRueT8 Zxh5x8URm58CGSU4/vSB/Ps2IdXFPY7P+wWOmh0HxZKxt68CIpxgOoZ X-Developer-Key: i=quic_jingyw@quicinc.com; a=ed25519; pk=ZRP1KgWMhlXXWlSYLoO7TSfwKgt6ke8hw5xWcSY+wLQ= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: FupoVCsN2A_iIshT_zcsDR2AJ8eHCvrk X-Proofpoint-GUID: FupoVCsN2A_iIshT_zcsDR2AJ8eHCvrk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 mlxscore=0 suspectscore=0 impostorscore=0 spamscore=0 phishscore=0 mlxlogscore=999 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409250073 Add initial DTSI for QCS8300 SoC. Features added in this revision: - CPUs with PSCI idle states - Interrupt-controller with PDC wakeup support - Timers, TCSR Clock Controllers - Reserved Shared memory - GCC and RPMHCC - TLMM - Interconnect - QuP with uart - SMMU - QFPROM - Rpmhpd power controller - UFS - Inter-Processor Communication Controller - SRAM - Remoteprocs including ADSP,CDSP and GPDSP - BWMONs [Zhenhua: added the smmu node] Co-developed-by: Zhenhua Huang Signed-off-by: Zhenhua Huang [Xin: added ufs/adsp/gpdsp nodes] Co-developed-by: Xin Liu Signed-off-by: Xin Liu [Kyle: added the aoss_qmp node] Co-developed-by: Kyle Deng Signed-off-by: Kyle Deng [Tingguo: added the rpmhpd nodes] Co-developed-by: Tingguo Cheng Signed-off-by: Tingguo Cheng [Raviteja: added interconnect nodes] Co-developed-by: Raviteja Laggyshetty Signed-off-by: Raviteja Laggyshetty Signed-off-by: Jingyi Wang Reviewed-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 1375 +++++++++++++++++++++++++++++= ++++ 1 file changed, 1375 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qc= om/qcs8300.dtsi new file mode 100644 index 000000000000..2c35f96c3f28 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -0,0 +1,1375 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent =3D <&intc>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78c"; + reg =3D <0x0 0x0>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + power-domains =3D <&cpu_pd0>; + power-domain-names =3D "psci"; + + l2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78c"; + reg =3D <0x0 0x100>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_1>; + power-domains =3D <&cpu_pd1>; + power-domain-names =3D "psci"; + + l2_1: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78c"; + reg =3D <0x0 0x200>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_2>; + power-domains =3D <&cpu_pd2>; + power-domain-names =3D "psci"; + + l2_2: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78c"; + reg =3D <0x0 0x300>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_3>; + power-domains =3D <&cpu_pd3>; + power-domain-names =3D "psci"; + + l2_3: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu4: cpu@10000 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0 0x10000>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_4>; + power-domains =3D <&cpu_pd4>; + power-domain-names =3D "psci"; + + l2_4: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_1>; + }; + }; + + cpu5: cpu@10100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0 0x10100>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_5>; + power-domains =3D <&cpu_pd5>; + power-domain-names =3D "psci"; + + l2_5: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_1>; + }; + }; + + cpu6: cpu@10200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0 0x10200>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_6>; + power-domains =3D <&cpu_pd6>; + power-domain-names =3D "psci"; + + l2_6: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_1>; + }; + }; + + cpu7: cpu@10300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0 0x10300>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_7>; + power-domains =3D <&cpu_pd7>; + power-domain-names =3D "psci"; + + l2_7: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_1>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + + core4 { + cpu =3D <&cpu4>; + }; + + core5 { + cpu =3D <&cpu5>; + }; + + core6 { + cpu =3D <&cpu6>; + }; + + core7 { + cpu =3D <&cpu7>; + }; + }; + }; + + l3_0: l3-cache-0 { + compatible =3D "cache"; + cache-level =3D <3>; + cache-unified; + }; + + l3_1: l3-cache-1 { + compatible =3D "cache"; + cache-level =3D <3>; + cache-unified; + }; + + idle-states { + entry-method =3D "psci"; + + little_cpu_sleep_0: cpu-sleep-0-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "silver-power-collapse"; + arm,psci-suspend-param =3D <0x40000003>; + entry-latency-us =3D <449>; + exit-latency-us =3D <801>; + min-residency-us =3D <1574>; + local-timer-stop; + }; + + little_cpu_sleep_1: cpu-sleep-0-1 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "silver-rail-power-collapse"; + arm,psci-suspend-param =3D <0x40000004>; + entry-latency-us =3D <602>; + exit-latency-us =3D <961>; + min-residency-us =3D <4288>; + local-timer-stop; + }; + + big_cpu_sleep_0: cpu-sleep-1-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "gold-power-collapse"; + arm,psci-suspend-param =3D <0x40000003>; + entry-latency-us =3D <549>; + exit-latency-us =3D <901>; + min-residency-us =3D <1774>; + local-timer-stop; + }; + + big_cpu_sleep_1: cpu-sleep-1-1 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "gold-rail-power-collapse"; + arm,psci-suspend-param =3D <0x40000004>; + entry-latency-us =3D <702>; + exit-latency-us =3D <1061>; + min-residency-us =3D <4488>; + local-timer-stop; + }; + }; + + domain-idle-states { + silver_cluster_sleep: cluster-sleep-0 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x41000044>; + entry-latency-us =3D <2552>; + exit-latency-us =3D <2848>; + min-residency-us =3D <5908>; + }; + + gold_cluster_sleep: cluster-sleep-1 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x41000044>; + entry-latency-us =3D <2752>; + exit-latency-us =3D <3048>; + min-residency-us =3D <6118>; + }; + + system_sleep: domain-sleep { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x42000144>; + entry-latency-us =3D <3263>; + exit-latency-us =3D <6562>; + min-residency-us =3D <9987>; + }; + }; + }; + + firmware { + scm: scm { + compatible =3D "qcom,scm-qcs8300", "qcom,scm"; + qcom,dload-mode =3D <&tcsr 0x13000>; + }; + }; + + memory@80000000 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the size */ + reg =3D <0x0 0x80000000 0x0 0x0>; + }; + + clk_virt: interconnect-0 { + compatible =3D "qcom,qcs8300-clk-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + mc_virt: interconnect-1 { + compatible =3D "qcom,qcs8300-mc-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + + cpu_pd0: power-domain-cpu0 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd0>; + domain-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; + }; + + cpu_pd1: power-domain-cpu1 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd0>; + domain-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; + }; + + cpu_pd2: power-domain-cpu2 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd0>; + domain-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; + }; + + cpu_pd3: power-domain-cpu3 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd0>; + domain-idle-states =3D <&big_cpu_sleep_0 &big_cpu_sleep_1>; + }; + + cpu_pd4: power-domain-cpu4 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd1>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; + }; + + cpu_pd5: power-domain-cpu5 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd1>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; + }; + + cpu_pd6: power-domain-cpu6 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd1>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; + }; + + cpu_pd7: power-domain-cpu7 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd1>; + domain-idle-states =3D <&little_cpu_sleep_0 &little_cpu_sleep_1>; + }; + + cluster_pd0: power-domain-cluster0 { + #power-domain-cells =3D <0>; + power-domains =3D <&system_pd>; + domain-idle-states =3D <&gold_cluster_sleep>; + }; + + cluster_pd1: power-domain-cluster1 { + #power-domain-cells =3D <0>; + power-domains =3D <&system_pd>; + domain-idle-states =3D <&silver_cluster_sleep>; + }; + + system_pd: power-domain-system { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&system_sleep>; + }; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + aop_image_mem: aop-image-region@90800000 { + reg =3D <0x0 0x90800000 0x0 0x60000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db-region@90860000 { + compatible =3D "qcom,cmd-db"; + reg =3D <0x0 0x90860000 0x0 0x20000>; + no-map; + }; + + smem_mem: smem@90900000 { + compatible =3D "qcom,smem"; + reg =3D <0x0 0x90900000 0x0 0x200000>; + no-map; + hwlocks =3D <&tcsr_mutex 3>; + }; + + lpass_machine_learning_mem: lpass-machine-learning-region@93b00000 { + reg =3D <0x0 0x93b00000 0x0 0xf00000>; + no-map; + }; + + adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap-region@94a00000 { + reg =3D <0x0 0x94a00000 0x0 0x800000>; + no-map; + }; + + camera_mem: camera-region@95200000 { + reg =3D <0x0 0x95200000 0x0 0x500000>; + no-map; + }; + + adsp_mem: adsp-region@95c00000 { + no-map; + reg =3D <0x0 0x95c00000 0x0 0x1e00000>; + }; + + q6_adsp_dtb_mem: q6-adsp-dtb-region@97a00000 { + reg =3D <0x0 0x97a00000 0x0 0x80000>; + no-map; + }; + + q6_gpdsp_dtb_mem: q6-gpdsp-dtb-region@97a80000 { + reg =3D <0x0 0x97a80000 0x0 0x80000>; + no-map; + }; + + gpdsp_mem: gpdsp-region@97b00000 { + reg =3D <0x0 0x97b00000 0x0 0x1e00000>; + no-map; + }; + + q6_cdsp_dtb_mem: q6-cdsp-dtb-region@99900000 { + reg =3D <0x0 0x99900000 0x0 0x80000>; + no-map; + }; + + cdsp_mem: cdsp-region@99980000 { + reg =3D <0x0 0x99980000 0x0 0x1e00000>; + no-map; + }; + + gpu_microcode_mem: gpu-microcode-region@9b780000 { + reg =3D <0x0 0x9b780000 0x0 0x2000>; + no-map; + }; + + cvp_mem: cvp-region@9b782000 { + reg =3D <0x0 0x9b782000 0x0 0x700000>; + no-map; + }; + + video_mem: video-region@9be82000 { + reg =3D <0x0 0x9be82000 0x0 0x700000>; + no-map; + }; + }; + + smp2p-adsp { + compatible =3D "qcom,smp2p"; + interrupts-extended =3D <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem =3D <443>, <429>; + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <2>; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + smp2p_adsp_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + }; + + smp2p-cdsp { + compatible =3D "qcom,smp2p"; + interrupts-extended =3D <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem =3D <94>, <432>; + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <5>; + + smp2p_cdsp_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + smp2p_cdsp_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + }; + + smp2p-gpdsp { + compatible =3D "qcom,smp2p"; + interrupts-extended =3D <&ipcc IPCC_CLIENT_GPDSP0 + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_GPDSP0 + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem =3D <617>, <616>; + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <17>; + + smp2p_gpdsp_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + smp2p_gpdsp_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + ranges =3D <0 0 0 0 0x10 0>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + gcc: clock-controller@100000 { + compatible =3D "qcom,qcs8300-gcc"; + reg =3D <0x0 0x00100000 0x0 0xc7018>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + ipcc: mailbox@408000 { + compatible =3D "qcom,qcs8300-ipcc", "qcom,ipcc"; + reg =3D <0x0 0x408000 0x0 0x1000>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <3>; + #mbox-cells =3D <2>; + }; + + qfprom: efuse@784000 { + compatible =3D "qcom,qcs8300-qfprom", "qcom,qfprom"; + reg =3D <0x0 0x00784000 0x0 0x1200>; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; + + qupv3_id_0: geniqup@9c0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x9c0000 0x0 0x2000>; + ranges; + clocks =3D <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names =3D "m-ahb", + "s-ahb"; + #address-cells =3D <2>; + #size-cells =3D <2>; + status =3D "disabled"; + + uart7: serial@99c000 { + compatible =3D "qcom,geni-debug-uart"; + reg =3D <0x0 0x0099c000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart7_default>; + pinctrl-names =3D "default"; + interrupts =3D ; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 + &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 + &config_noc SLAVE_QUP_0 0>; + interconnect-names =3D "qup-core", + "qup-config"; + status =3D "disabled"; + }; + }; + + config_noc: interconnect@14c0000 { + compatible =3D "qcom,qcs8300-config-noc"; + reg =3D <0x0 0x014c0000 0x0 0x13080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + system_noc: interconnect@1680000 { + compatible =3D "qcom,qcs8300-system-noc"; + reg =3D <0x0 0x01680000 0x0 0x15080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16c0000 { + compatible =3D "qcom,qcs8300-aggre1-noc"; + reg =3D <0x0 0x016c0000 0x0 0x17080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible =3D "qcom,qcs8300-aggre2-noc"; + reg =3D <0x0 0x01700000 0x0 0x1a080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + pcie_anoc: interconnect@1760000 { + compatible =3D "qcom,qcs8300-pcie-anoc"; + reg =3D <0x0 0x01760000 0x0 0xc080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + gpdsp_anoc: interconnect@1780000 { + compatible =3D "qcom,qcs8300-gpdsp-anoc"; + reg =3D <0x0 0x01780000 0x0 0xd080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@17a0000 { + compatible =3D "qcom,qcs8300-mmss-noc"; + reg =3D <0x0 0x017a0000 0x0 0x40000>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + ufs_mem_hc: ufs@1d84000 { + compatible =3D "qcom,qcs8300-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; + reg =3D <0x0 0x01d84000 0x0 0x3000>; + interrupts =3D ; + phys =3D <&ufs_mem_phy>; + phy-names =3D "ufsphy"; + lanes-per-direction =3D <2>; + #reset-cells =3D <1>; + resets =3D <&gcc GCC_UFS_PHY_BCR>; + reset-names =3D "rst"; + + power-domains =3D <&gcc GCC_UFS_PHY_GDSC>; + required-opps =3D <&rpmhpd_opp_nom>; + + iommus =3D <&apps_smmu 0x100 0x0>; + dma-coherent; + + interconnects =3D <&aggre1_noc MASTER_UFS_MEM 0 + &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 + &config_noc SLAVE_UFS_MEM_CFG 0>; + interconnect-names =3D "ufs-ddr", + "cpu-ufs"; + + clocks =3D <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names =3D "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + freq-table-hz =3D <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + status =3D "disabled"; + }; + + ufs_mem_phy: phy@1d87000 { + compatible =3D "qcom,qcs8300-qmp-ufs-phy", "qcom,sa8775p-qmp-ufs-phy"; + reg =3D <0x0 0x01d87000 0x0 0xe10>; + /* + * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It + * enables the CXO clock to eDP *and* UFS PHY. + */ + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_EDP_REF_CLKREF_EN>; + clock-names =3D "ref", + "ref_aux", + "qref"; + power-domains =3D <&gcc GCC_UFS_PHY_GDSC>; + + resets =3D <&ufs_mem_hc 0>; + reset-names =3D "ufsphy"; + + #phy-cells =3D <0>; + status =3D "disabled"; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x0 0x01f40000 0x0 0x20000>; + #hwlock-cells =3D <1>; + }; + + tcsr: syscon@1fc0000 { + compatible =3D "qcom,qcs8300-tcsr", "syscon"; + reg =3D <0x0 0x1fc0000 0x0 0x30000>; + }; + + remoteproc_adsp: remoteproc@3000000 { + compatible =3D "qcom,qcs8300-adsp-pas", "qcom,sa8775p-adsp-pas"; + reg =3D <0x0 0x3000000 0x0 0x00100>; + + interrupts-extended =3D <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + power-domains =3D <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; + power-domain-names =3D "lcx", + "lmx"; + + memory-region =3D <&adsp_mem>; + + qcom,qmp =3D <&aoss_qmp>; + + qcom,smem-states =3D <&smp2p_adsp_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + remoteproc_adsp_glink: glink-edge { + interrupts-extended =3D <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label =3D "lpass"; + qcom,remote-pid =3D <2>; + }; + }; + + lpass_ag_noc: interconnect@3c40000 { + compatible =3D "qcom,qcs8300-lpass-ag-noc"; + reg =3D <0x0 0x03c40000 0x0 0x17200>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + pmu@9091000 { + compatible =3D "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; + reg =3D <0x0 0x9091000 0x0 0x1000>; + + interrupts =3D ; + + interconnects =3D <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 =3D <&llcc_bwmon_opp_table>; + + llcc_bwmon_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-0 { + opp-peak-kBps =3D <762000>; + }; + + opp-1 { + opp-peak-kBps =3D <1720000>; + }; + + opp-2 { + opp-peak-kBps =3D <2086000>; + }; + + opp-3 { + opp-peak-kBps =3D <2601000>; + }; + + opp-4 { + opp-peak-kBps =3D <2929000>; + }; + + opp-5 { + opp-peak-kBps =3D <5931000>; + }; + + opp-6 { + opp-peak-kBps =3D <6515000>; + }; + + opp-7 { + opp-peak-kBps =3D <7984000>; + }; + + opp-8 { + opp-peak-kBps =3D <10437000>; + }; + + opp-9 { + opp-peak-kBps =3D <12195000>; + }; + }; + }; + + pmu@90b5400 { + compatible =3D "qcom,qcs8300-cpu-bwmon", "qcom,sdm845-bwmon"; + reg =3D <0x0 0x90b5400 0x0 0x600>; + interrupts =3D ; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 =3D <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-0 { + opp-peak-kBps =3D <9155000>; + }; + + opp-1 { + opp-peak-kBps =3D <12298000>; + }; + + opp-2 { + opp-peak-kBps =3D <14236000>; + }; + + opp-3 { + opp-peak-kBps =3D <16265000>; + }; + }; + }; + + pmu@90b6400 { + compatible =3D "qcom,qcs8300-cpu-bwmon", "qcom,sdm845-bwmon"; + reg =3D <0x0 0x90b6400 0x0 0x600>; + interrupts =3D ; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 =3D <&cpu_bwmon_opp_table>; + }; + + dc_noc: interconnect@90e0000 { + compatible =3D "qcom,qcs8300-dc-noc"; + reg =3D <0x0 0x090e0000 0x0 0x5080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + gem_noc: interconnect@9100000 { + compatible =3D "qcom,qcs8300-gem-noc"; + reg =3D <0x0 0x9100000 0x0 0xf7080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + pdc: interrupt-controller@b220000 { + compatible =3D "qcom,qcs8300-pdc", "qcom,pdc"; + reg =3D <0x0 0xb220000 0x0 0x30000>, + <0x0 0x17c000f0 0x0 0x64>; + interrupt-parent =3D <&intc>; + #interrupt-cells =3D <2>; + interrupt-controller; + qcom,pdc-ranges =3D <0 480 40>, + <40 140 14>, + <54 263 1>, + <55 306 4>, + <59 312 3>, + <62 374 2>, + <64 434 2>, + <66 438 2>, + <70 520 1>, + <73 523 1>, + <118 568 6>, + <124 609 3>, + <159 638 1>, + <160 720 3>, + <169 728 30>, + <199 416 2>, + <201 449 1>, + <202 89 1>, + <203 451 1>, + <204 462 1>, + <205 264 1>, + <206 579 1>, + <207 653 1>, + <208 656 1>, + <209 659 1>, + <210 122 1>, + <211 699 1>, + <212 705 1>, + <213 450 1>, + <214 643 2>, + <216 646 5>, + <221 390 5>, + <226 700 2>, + <228 440 1>, + <229 663 1>, + <230 524 2>, + <232 612 3>, + <235 723 5>; + }; + + aoss_qmp: power-management@c300000 { + compatible =3D "qcom,qcs8300-aoss-qmp", "qcom,aoss-qmp"; + reg =3D <0x0 0x0c300000 0x0 0x400>; + interrupts-extended =3D <&ipcc IPCC_CLIENT_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + #clock-cells =3D <0>; + }; + + tlmm: pinctrl@f100000 { + compatible =3D "qcom,qcs8300-tlmm"; + reg =3D <0x0 0x0f100000 0x0 0x300000>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 133>; + interrupt-controller; + #interrupt-cells =3D <2>; + wakeup-parent =3D <&pdc>; + + qup_uart7_default: qup-uart7-state { + /* TX, RX */ + pins =3D "gpio43", "gpio44"; + function =3D "qup0_se7"; + }; + }; + + sram: sram@146d8000 { + compatible =3D "qcom,qcs8300-imem", "syscon", "simple-mfd"; + reg =3D <0x0 0x146d8000 0x0 0x1000>; + ranges =3D <0x0 0x0 0x146d8000 0x1000>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + + pil-reloc@94c { + compatible =3D "qcom,pil-reloc-info"; + reg =3D <0x94c 0xc8>; + }; + }; + + apps_smmu: iommu@15000000 { + compatible =3D "qcom,qcs8300-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + + reg =3D <0x0 0x15000000 0x0 0x100000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <2>; + dma-coherent; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + intc: interrupt-controller@17a00000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x17a00000 0x0 0x10000>, /* GICD */ + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ + interrupts =3D ; + #interrupt-cells =3D <3>; + interrupt-controller; + #redistributor-regions =3D <1>; + redistributor-stride =3D <0x0 0x20000>; + }; + + memtimer: timer@17c20000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0 0x17c20000 0x0 0x1000>; + ranges =3D <0x0 0x0 0x0 0x20000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + frame@17c21000 { + reg =3D <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + frame-number =3D <0>; + interrupts =3D , + ; + }; + + frame@17c23000 { + reg =3D <0x17c23000 0x1000>; + frame-number =3D <1>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@17c25000 { + reg =3D <0x17c25000 0x1000>; + frame-number =3D <2>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@17c27000 { + reg =3D <0x17c27000 0x1000>; + frame-number =3D <3>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@17c29000 { + reg =3D <0x17c29000 0x1000>; + frame-number =3D <4>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@17c2b000 { + reg =3D <0x17c2b000 0x1000>; + frame-number =3D <5>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@17c2d000 { + reg =3D <0x17c2d000 0x1000>; + frame-number =3D <6>; + interrupts =3D ; + status =3D "disabled"; + }; + }; + + apps_rsc: rsc@18200000 { + compatible =3D "qcom,rpmh-rsc"; + reg =3D <0x0 0x18200000 0x0 0x10000>, + <0x0 0x18210000 0x0 0x10000>, + <0x0 0x18220000 0x0 0x10000>; + reg-names =3D "drv-0", + "drv-1", + "drv-2"; + interrupts =3D , + , + ; + + power-domains =3D <&system_pd>; + label =3D "apps_rsc"; + + qcom,tcs-offset =3D <0xd00>; + qcom,drv-id =3D <2>; + qcom,tcs-config =3D , + , + , + ; + + apps_bcm_voter: bcm-voter { + compatible =3D "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible =3D "qcom,sa8775p-rpmh-clk"; + #clock-cells =3D <1>; + }; + + rpmhpd: power-controller { + compatible =3D "qcom,qcs8300-rpmhpd"; + #power-domain-cells =3D <1>; + operating-points-v2 =3D <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + rpmhpd_opp_ret: opp-0 { + opp-level =3D ; + }; + + rpmhpd_opp_min_svs: opp-1 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs: opp-2 { + opp-level =3D ; + }; + + rpmhpd_opp_svs: opp-3 { + opp-level =3D ; + }; + + rpmhpd_opp_svs_l1: opp-4 { + opp-level =3D ; + }; + + rpmhpd_opp_nom: opp-5 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l1: opp-6 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l2: opp-7 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo: opp-8 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l1: opp-9 { + opp-level =3D ; + }; + }; + }; + }; + + remoteproc_gpdsp: remoteproc@20c00000 { + compatible =3D "qcom,qcs8300-gpdsp-pas", "qcom,sa8775p-gpdsp0-pas"; + reg =3D <0x0 0x20c00000 0x0 0x10000>; + + interrupts-extended =3D <&intc GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, + <&smp2p_gpdsp_in 0 0>, + <&smp2p_gpdsp_in 1 0>, + <&smp2p_gpdsp_in 2 0>, + <&smp2p_gpdsp_in 3 0>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + power-domains =3D <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MXC>; + power-domain-names =3D "cx", + "mxc"; + + interconnects =3D <&gpdsp_anoc MASTER_DSP0 0 &config_noc SLAVE_CLK_CTL = 0>; + + memory-region =3D <&gpdsp_mem>; + + qcom,qmp =3D <&aoss_qmp>; + + qcom,smem-states =3D <&smp2p_gpdsp_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + glink-edge { + interrupts-extended =3D <&ipcc IPCC_CLIENT_GPDSP0 + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_GPDSP0 + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label =3D "gpdsp"; + qcom,remote-pid =3D <17>; + }; + }; + + nspa_noc: interconnect@260c0000 { + compatible =3D "qcom,qcs8300-nspa-noc"; + reg =3D <0x0 0x260c0000 0x0 0x16080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + remoteproc_cdsp: remoteproc@26300000 { + compatible =3D "qcom,qcs8300-cdsp-pas", "qcom,sa8775p-cdsp0-pas"; + reg =3D <0x0 0x26300000 0x0 0x10000>; + + interrupts-extended =3D <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + power-domains =3D <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_NSP0>; + + power-domain-names =3D "cx", + "mxc", + "nsp"; + + interconnects =3D <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; + + memory-region =3D <&cdsp_mem>; + + qcom,qmp =3D <&aoss_qmp>; + + qcom,smem-states =3D <&smp2p_cdsp_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + glink-edge { + interrupts-extended =3D <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label =3D "cdsp"; + qcom,remote-pid =3D <5>; + }; + }; + }; + + arch_timer: timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; +}; --=20 2.25.1