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[87.7.171.42]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a93930cae0fsm72612766b.120.2024.09.24.04.30.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Sep 2024 04:30:56 -0700 (PDT) From: Antonino Maniscalco Date: Tue, 24 Sep 2024 13:30:45 +0200 Subject: [PATCH v5 10/11] drm/msm/A6xx: Enable preemption for A750 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240924-preemption-a750-t-v5-10-0be2bf81c187@gmail.com> References: <20240924-preemption-a750-t-v5-0-0be2bf81c187@gmail.com> In-Reply-To: <20240924-preemption-a750-t-v5-0-0be2bf81c187@gmail.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Jonathan Corbet Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Antonino Maniscalco , Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727177437; l=3953; i=antomani103@gmail.com; s=20240815; h=from:subject:message-id; bh=sm9hanaGRS16RZfX1ly7ITrlxWebFBdSbkyJsPoWlBc=; b=5jfqYFhN2eShGqsYyYpOlxaTj84UM3HppgBbzgf3lt8IUti4AVbDgN7q71k7ecpT0AeYM81n0 7XPW2ONeBHJCF+NeEn+fg5T6o6TysRAytAwMTgegbVVPq8JuxZfx/aj X-Developer-Key: i=antomani103@gmail.com; a=ed25519; pk=0zicFb38tVla+iHRo4kWpOMsmtUrpGBEa7LkFF81lyY= Initialize with 4 rings to enable preemption. For now only on A750 as other targets require testing. Add the "preemption_enabled" module parameter to override this for other A7xx targets. Tested-by: Neil Armstrong # on SM8650-QRD Tested-by: Neil Armstrong # on SM8550-QRD Tested-by: Neil Armstrong # on SM8450-HDK Signed-off-by: Antonino Maniscalco --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 3 ++- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +++++- drivers/gpu/drm/msm/adreno/adreno_device.c | 4 ++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + 4 files changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/ms= m/adreno/a6xx_catalog.c index 316f23ca91671d973797f2a5b69344f376707325..0e3041b2941905f1acdc9e571e0= 549a960a7edfa 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -1240,7 +1240,8 @@ static const struct adreno_info a7xx_gpus[] =3D { .gmem =3D 3 * SZ_1M, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, + ADRENO_QUIRK_HAS_HW_APRIV | + ADRENO_QUIRK_PREEMPTION, .init =3D a6xx_gpu_init, .zapfw =3D "gen70900_zap.mbn", .a6xx =3D &(const struct a6xx_info) { diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index edbcb6d229ba614be910ee70e75731538116e4a4..4760f9469613c0bf208f56be960= 8747b5aa75606 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2529,6 +2529,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) struct a6xx_gpu *a6xx_gpu; struct adreno_gpu *adreno_gpu; struct msm_gpu *gpu; + extern int enable_preemption; bool is_a7xx; int ret; =20 @@ -2567,7 +2568,10 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) return ERR_PTR(ret); } =20 - if (is_a7xx) + if ((enable_preemption =3D=3D 1) || (enable_preemption =3D=3D -1 && + (config->info->quirks & ADRENO_QUIRK_PREEMPTION))) + ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 4); + else if (is_a7xx) ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 1); else if (adreno_has_gmu_wrapper(adreno_gpu)) ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_gmuwrapper, 1); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/m= sm/adreno/adreno_device.c index cfc74a9e2646d3de76a06bd67457d69afa49e309..9ffe91920fbfb4841b28aabec9f= bde94539fdd83 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -20,6 +20,10 @@ bool allow_vram_carveout =3D false; MODULE_PARM_DESC(allow_vram_carveout, "Allow using VRAM Carveout, in place= of IOMMU"); module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600); =20 +int enable_preemption =3D -1; +MODULE_PARM_DESC(enable_preemption, "Enable preemption (A7xx only) (1=3Don= , 0=3Ddisable, -1=3Dauto (default))"); +module_param(enable_preemption, int, 0600); + extern const struct adreno_gpulist a2xx_gpulist; extern const struct adreno_gpulist a3xx_gpulist; extern const struct adreno_gpulist a4xx_gpulist; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index 87098567483b69c21025b80f356e0a68f0e7f172..d1cd53f05de68b3873f35520655= e09e82fc40449 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -56,6 +56,7 @@ enum adreno_family { #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2) #define ADRENO_QUIRK_HAS_HW_APRIV BIT(3) #define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4) +#define ADRENO_QUIRK_PREEMPTION BIT(5) =20 /* Helper for formating the chip_id in the way that userspace tools like * crashdec expect. --=20 2.46.1