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Most system it is the same as CPU address, but some hardware like i.MX8QXP convert it to difference address by bus fabric. See below diagram: =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 =E2=94=8C=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 =E2= =94=82 =E2=94=82 IA: 0x8ff0_0000 =E2=94=82 =E2=94=82 =E2=94=82 CPU =E2=94=9C=E2=94=80=E2=94=80=E2=94=80=E2=96=BA=E2=94=82 B= US =E2=94=9C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=90 =E2=94=82 PCI =E2=94=82 =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=98 =E2= =94=82 =E2=94=82 IA: 0x8ff8_0000 =E2=94=82 =E2=94=82 = =E2=94=82 CPU Addr =E2=94=82 Fabric =E2=94=9C=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=90 =E2=94=82 =E2=94=82 Controller =E2=94=82 0x7000_0000 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94= =82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94= =82 =E2=94=82 =E2=94=82 PCI Addr =E2=94=82 =E2=94=82 =E2=94=82 =E2=94= =94=E2=94=80=E2=94=80=E2=96=BA CfgSpace =E2=94=80=E2=94=BC=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=96=BA =E2=94=82 =E2=94=9C=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 =E2=94=82 = =E2=94=82 =E2=94=82 0 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 = =E2=94=82 =E2=94=82 =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=98 =E2=94=82 =E2=94=94=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=96=BA IOSpace =E2= =94=80=E2=94=BC=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=96=BA =E2=94=82 =E2=94=82 = =E2=94=82 0 =E2=94=82 =E2=94=82 = =E2=94=82 =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=96=BA MemSp= ace =E2=94=80=E2=94=BC=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=96=BA IA: 0x8000_0000 =E2=94=82 =E2=94= =82 0x8000_0000 =E2=94=94=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=98 bus@5f000000 { compatible =3D "simple-bus"; #address-cells =3D <1>; #size-cells =3D <1>; ranges =3D <0x5f000000 0x0 0x5f000000 0x21000000>, <0x80000000 0x0 0x70000000 0x10000000>; pcie@5f010000 { compatible =3D "fsl,imx8q-pcie"; reg =3D <0x5f010000 0x10000>, <0x8ff00000 0x80000>; reg-names =3D "dbi", "config"; #address-cells =3D <3>; #size-cells =3D <2>; device_type =3D "pci"; bus-range =3D <0x00 0xff>; ranges =3D <0x81000000 0 0x00000000 0x8ff80000 0 0x00010000>, <0x82000000 0 0x80000000 0x80000000 0 0x0ff00000>; ... }; }; Term 'IA' here means the address just before PCIe controle. After ATU use this IA instead CPU address, cpu_addr_fixup() can be removed. Signed-off-by: Frank Li --- drivers/pci/controller/dwc/pcie-designware-host.c | 33 +++++++++++++++++++= ++++ 1 file changed, 33 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 3e41865c72904..68c679a2e1737 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -418,6 +418,27 @@ static void dw_pcie_host_request_msg_tlp_res(struct dw= _pcie_rp *pp) } } =20 +static int dw_pcie_get_untranslate_addr(struct device_node *np, resource_s= ize_t pci_addr, + resource_size_t *i_addr) +{ + struct of_range_parser parser; + struct of_range range; + int ret; + + ret =3D of_range_parser_init(&parser, np); + if (ret) + return ret; + + for_each_of_pci_range_untranslate(&parser, &range) { + if (pci_addr =3D=3D range.bus_addr) { + *i_addr =3D range.cpu_addr; + break; + } + } + + return 0; +} + int dw_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); @@ -427,6 +448,7 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) struct resource_entry *win; struct pci_host_bridge *bridge; struct resource *res; + int index; int ret; =20 raw_spin_lock_init(&pp->lock); @@ -440,6 +462,11 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) pp->cfg0_size =3D resource_size(res); pp->cfg0_base =3D res->start; =20 + index =3D of_property_match_string(np, "reg-names", "config"); + if (index < 0) + return -EINVAL; + of_property_read_reg(np, index, &pp->cfg0_base, NULL); + pp->va_cfg0_base =3D devm_pci_remap_cfg_resource(dev, res); if (IS_ERR(pp->va_cfg0_base)) return PTR_ERR(pp->va_cfg0_base); @@ -462,6 +489,9 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) pp->io_base =3D pci_pio_to_address(win->res->start); } =20 + if (dw_pcie_get_untranslate_addr(np, pp->io_bus_addr, &pp->io_base)) + return -ENODEV; + /* Set default bus ops */ bridge->ops =3D &dw_pcie_ops; bridge->child_ops =3D &dw_child_pcie_ops; @@ -733,6 +763,9 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) atu.cpu_addr =3D entry->res->start; atu.pci_addr =3D entry->res->start - entry->offset; =20 + if (dw_pcie_get_untranslate_addr(pci->dev->of_node, atu.pci_addr, &atu.c= pu_addr)) + return -EINVAL; + /* Adjust iATU size if MSG TLP region was allocated before */ if (pp->msg_res && pp->msg_res->parent =3D=3D entry->res) atu.size =3D resource_size(entry->res) - --=20 2.34.1