From nobody Fri Nov 29 04:52:37 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D1AD1184542; Tue, 24 Sep 2024 23:00:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727218813; cv=none; b=Y2slj4aIEd84kClvz0MCzBnlNOChyQ6R3HDP/W0/HioJzOCkProhZKdtW8dtvtXmesKD9t7PFhdBn7oQi6nqv8wafoXP0nPTPizaVJtpE8fFRnDwoMIpnQG4cILajmLNrsOHdYzI+T9qxm3ai6ARIWczX/Qs9MKng5etBcw7wP8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727218813; c=relaxed/simple; bh=JNjsyxr7h+o+Kb9s5nKCBdxnC/conEUGzeA4SzkTxZA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=L3LVol5msV7/GcrskLSg+hAq3N1IEkFh+6Aj31AKYICuH104xnFv5g8iiBgLzw5v1TAvxn73GEyMNsZBNfxnFzCXHz9Owj6L6AMyQIVk2geJoT8vvcwEtRxCJrh0FV+Kedqt6LwS+kxuS1JgGs6u01tGfGxwFY+Fhy5U89Rfhj0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=LnX+BnHD; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="LnX+BnHD" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48OIsLu4028605; Tue, 24 Sep 2024 22:59:57 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= w+0qHGI77WRaIvh6JH326plqIfcdSuUh91ymPBt412o=; b=LnX+BnHDxrUCuk98 hZAe4uErwpd3Rs4tL4ZOcMuXYXLOUZF+9Yt7fp9XoN68Bnaj6GULUSAI7dLBV4Vn 5TfNoOvuCaLGjni8+BusfiFPKFhy5aKw+VdMyinDIs+riRJ15xbfJoAtXUrkJalt qv2ICqlidXkC3ToYvDoglPlfykRWI9er4bCHFeIk+dV1WOCsRdPK+eFu0exm5sUh hBQNEXGjrpyUo/1xNksGDyjoeS236hsNRRf++o+UkzVQgC71iZOedctbB5RMvupB O9rogwhgGFjg0D3Y/ZVKvEnnpQtkgMPnuI70wCSbfBkLx5WkXI/IJj4f/UD8Ucds Hs/KHg== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 41skuet6gt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 24 Sep 2024 22:59:56 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48OMxtnj027313 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 24 Sep 2024 22:59:56 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 24 Sep 2024 15:59:55 -0700 From: Jessica Zhang Date: Tue, 24 Sep 2024 15:59:23 -0700 Subject: [PATCH v2 07/22] drm/msm/dpu: Add CWB entry to catalog for SM8650 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240924-concurrent-wb-v2-7-7849f900e863@quicinc.com> References: <20240924-concurrent-wb-v2-0-7849f900e863@quicinc.com> In-Reply-To: <20240924-concurrent-wb-v2-0-7849f900e863@quicinc.com> To: Rob Clark , Dmitry Baryshkov , , Sean Paul , Marijn Suijten , "David Airlie" , Daniel Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann CC: , , , , , Rob Clark , =?utf-8?q?Ville_Syrj=C3=A4l=C3=A4?= , "Jessica Zhang" X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727218793; l=2555; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=IkX+OpqK4f1IF+L/KY5nLbNxU3aEcm80r3xuNrtqub0=; b=xQOvW5pRpeFAaREm8Equ/rkMhu7j4E22nqavHYd1iQEAku0/CyfnCedIlGt7UIp/1elDbG8B/ Zr22LhdM+otBEzyvAv6NHJ48er5icBS88YSwvddW2EXvDjDDRNgq8u6 X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: jqZXHya_zcS5rOaxT_t5pckzvk1lUSG4 X-Proofpoint-ORIG-GUID: jqZXHya_zcS5rOaxT_t5pckzvk1lUSG4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 adultscore=0 clxscore=1015 lowpriorityscore=0 suspectscore=0 malwarescore=0 impostorscore=0 mlxlogscore=999 bulkscore=0 mlxscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409240160 From: Esha Bharadwaj Add a new block for concurrent writeback mux to the SM8650 HW catalog Signed-off-by: Esha Bharadwaj Signed-off-by: Jessica Zhang Reviewed-by: Dmitry Baryshkov --- .../gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 21 +++++++++++++++++= ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 13 +++++++++++++ 2 files changed, 34 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h index eb5dfff2ec4f..33f5faf4833f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h @@ -350,6 +350,25 @@ static const struct dpu_wb_cfg sm8650_wb[] =3D { }, }; =20 +static const struct dpu_cwb_cfg sm8650_cwb[] =3D { + { + .name =3D "cwb_0", .id =3D CWB_0, + .base =3D 0x66200, .len =3D 0x8, + }, + { + .name =3D "cwb_1", .id =3D CWB_1, + .base =3D 0x66600, .len =3D 0x8, + }, + { + .name =3D "cwb_2", .id =3D CWB_2, + .base =3D 0x7E200, .len =3D 0x8, + }, + { + .name =3D "cwb_3", .id =3D CWB_3, + .base =3D 0x7E600, .len =3D 0x8, + }, +}; + static const struct dpu_intf_cfg sm8650_intf[] =3D { { .name =3D "intf_0", .id =3D INTF_0, @@ -447,6 +466,8 @@ const struct dpu_mdss_cfg dpu_sm8650_cfg =3D { .merge_3d =3D sm8650_merge_3d, .wb_count =3D ARRAY_SIZE(sm8650_wb), .wb =3D sm8650_wb, + .cwb_count =3D ARRAY_SIZE(sm8650_cwb), + .cwb =3D sm8650_cwb, .intf_count =3D ARRAY_SIZE(sm8650_intf), .intf =3D sm8650_intf, .vbif_count =3D ARRAY_SIZE(sm8650_vbif), diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 37e18e820a20..b42d8b3640e2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -621,6 +621,16 @@ struct dpu_wb_cfg { enum dpu_clk_ctrl_type clk_ctrl; }; =20 +/* + * struct dpu_cwb_cfg : MDP CWB mux instance info + * @id: enum identifying this block + * @base: register base offset to mdss + * @features bit mask identifying sub-blocks/features + */ +struct dpu_cwb_cfg { + DPU_HW_BLK_INFO; +}; + /** * struct dpu_vbif_dynamic_ot_cfg - dynamic OT setting * @pps pixel per seconds @@ -823,6 +833,9 @@ struct dpu_mdss_cfg { u32 dspp_count; const struct dpu_dspp_cfg *dspp; =20 + u32 cwb_count; + const struct dpu_cwb_cfg *cwb; + /* Add additional block data structures here */ =20 const struct dpu_perf_cfg *perf; --=20 2.34.1