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Tue, 24 Sep 2024 22:59:57 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48OMxtAo027310 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 24 Sep 2024 22:59:55 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 24 Sep 2024 15:59:55 -0700 From: Jessica Zhang Date: Tue, 24 Sep 2024 15:59:22 -0700 Subject: [PATCH v2 06/22] drm/msm/dpu: fill CRTC resources in dpu_crtc.c Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240924-concurrent-wb-v2-6-7849f900e863@quicinc.com> References: <20240924-concurrent-wb-v2-0-7849f900e863@quicinc.com> In-Reply-To: <20240924-concurrent-wb-v2-0-7849f900e863@quicinc.com> To: Rob Clark , Dmitry Baryshkov , , Sean Paul , Marijn Suijten , "David Airlie" , Daniel Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann CC: , , , , , Rob Clark , =?utf-8?q?Ville_Syrj=C3=A4l=C3=A4?= , "Jessica Zhang" X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727218793; l=5380; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=wa02VAz1lsE/a59qGp6WdtoskrjUP+nnQZmoavxRym0=; b=NNIjM37Dbw7pL7IJ9D8zD7Q6PuHlQ8mCjCK28T7/62P3sk9qBdFx7iJsxePVhW6VsgRsaM7v+ PsRKA3h8bQVDtbGExxhuFJqeeTfwy+kAQXSaCB7iwDWOOpJuRPkeCDm X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 8_NU8s9YQt8wMXLgsiU7fwHD6jwa6DdW X-Proofpoint-ORIG-GUID: 8_NU8s9YQt8wMXLgsiU7fwHD6jwa6DdW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 mlxlogscore=999 mlxscore=0 phishscore=0 suspectscore=0 impostorscore=0 spamscore=0 malwarescore=0 priorityscore=1501 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409240159 From: Dmitry Baryshkov Stop poking into CRTC state from dpu_encoder.c, fill CRTC HW resources from dpu_crtc_assign_resources(). Signed-off-by: Dmitry Baryshkov [quic_abhinavk@quicinc.com: cleaned up formatting] Signed-off-by: Abhinav Kumar [quic_jesszhan@quicinc.com: dropped clearing num_mixers in CRTC disable path] Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 32 +++++++++++++++++++++++++= +--- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 24 ++-------------------- 2 files changed, 31 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index b918c80d30b3..d53e986eee54 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1091,9 +1091,6 @@ static void dpu_crtc_disable(struct drm_crtc *crtc, =20 dpu_core_perf_crtc_update(crtc, 0); =20 - memset(cstate->mixers, 0, sizeof(cstate->mixers)); - cstate->num_mixers =3D 0; - /* disable clk & bw control until clk & bw properties are set */ cstate->bw_control =3D false; cstate->bw_split_vote =3D false; @@ -1164,6 +1161,7 @@ static bool dpu_crtc_needs_dirtyfb(struct drm_crtc_st= ate *cstate) } =20 #define MAX_HDISPLAY_SPLIT 1080 +#define MAX_CHANNELS_PER_CRTC 2 =20 static struct msm_display_topology dpu_crtc_get_topology( struct drm_crtc *crtc, @@ -1208,9 +1206,14 @@ static struct msm_display_topology dpu_crtc_get_topo= logy( =20 static int dpu_crtc_assign_resources(struct drm_crtc *crtc, struct drm_crt= c_state *crtc_state) { + struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_CRTC]; + struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_CRTC]; + struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_CRTC]; + int i, num_lm, num_ctl, num_dspp; struct dpu_kms *dpu_kms =3D _dpu_crtc_get_kms(crtc); struct dpu_global_state *global_state; struct msm_display_topology topology; + struct dpu_crtc_state *cstate; int ret; =20 /* @@ -1232,6 +1235,29 @@ static int dpu_crtc_assign_resources(struct drm_crtc= *crtc, struct drm_crtc_stat if (ret) return ret; =20 + cstate =3D to_dpu_crtc_state(crtc_state); + + num_ctl =3D dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, + crtc, DPU_HW_BLK_CTL, hw_ctl, + ARRAY_SIZE(hw_ctl)); + num_lm =3D dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, + crtc, DPU_HW_BLK_LM, hw_lm, + ARRAY_SIZE(hw_lm)); + num_dspp =3D dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, + crtc, DPU_HW_BLK_DSPP, hw_dspp, + ARRAY_SIZE(hw_dspp)); + + for (i =3D 0; i < num_lm; i++) { + int ctl_idx =3D (i < num_ctl) ? i : (num_ctl-1); + + cstate->mixers[i].hw_lm =3D to_dpu_hw_mixer(hw_lm[i]); + cstate->mixers[i].lm_ctl =3D to_dpu_hw_ctl(hw_ctl[ctl_idx]); + if (i < num_dspp) + cstate->mixers[i].hw_dspp =3D to_dpu_hw_dspp(hw_dspp[i]); + } + + cstate->num_mixers =3D num_lm; + return 0; } =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index ada9119326ca..36b677cf9c7a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1049,14 +1049,11 @@ static void dpu_encoder_virt_atomic_mode_set(struct= drm_encoder *drm_enc, struct dpu_encoder_virt *dpu_enc; struct msm_drm_private *priv; struct dpu_kms *dpu_kms; - struct dpu_crtc_state *cstate; struct dpu_global_state *global_state; struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC]; struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC]; - struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC]; - struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] =3D { NULL }; struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC]; - int num_lm, num_ctl, num_pp, num_dsc; + int num_pp, num_dsc; unsigned int dsc_mask =3D 0; int i; =20 @@ -1083,13 +1080,8 @@ static void dpu_encoder_virt_atomic_mode_set(struct = drm_encoder *drm_enc, num_pp =3D dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, drm_enc->crtc, DPU_HW_BLK_PINGPONG, hw_pp, ARRAY_SIZE(hw_pp)); - num_ctl =3D dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->crtc, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); - num_lm =3D dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->crtc, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->crtc, DPU_HW_BLK_DSPP, hw_dspp, - ARRAY_SIZE(hw_dspp)); + drm_enc->crtc, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); =20 for (i =3D 0; i < MAX_CHANNELS_PER_ENC; i++) dpu_enc->hw_pp[i] =3D i < num_pp ? to_dpu_hw_pingpong(hw_pp[i]) @@ -1115,18 +1107,6 @@ static void dpu_encoder_virt_atomic_mode_set(struct = drm_encoder *drm_enc, dpu_enc->cur_master->hw_cdm =3D hw_cdm ? to_dpu_hw_cdm(hw_cdm) : NULL; } =20 - cstate =3D to_dpu_crtc_state(crtc_state); - - for (i =3D 0; i < num_lm; i++) { - int ctl_idx =3D (i < num_ctl) ? i : (num_ctl-1); - - cstate->mixers[i].hw_lm =3D to_dpu_hw_mixer(hw_lm[i]); - cstate->mixers[i].lm_ctl =3D to_dpu_hw_ctl(hw_ctl[ctl_idx]); - cstate->mixers[i].hw_dspp =3D to_dpu_hw_dspp(hw_dspp[i]); - } - - cstate->num_mixers =3D num_lm; - for (i =3D 0; i < dpu_enc->num_phys_encs; i++) { struct dpu_encoder_phys *phys =3D dpu_enc->phys_encs[i]; =20 --=20 2.34.1